#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00 - I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub conset: CONSET,
#[doc = "0x04 - I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub stat: STAT,
#[doc = "0x08 - I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub dat: DAT,
#[doc = "0x0c - I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr0: ADR0,
#[doc = "0x10 - SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub sclh: SCLH,
#[doc = "0x14 - SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub scll: SCLL,
#[doc = "0x18 - I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub conclr: CONCLR,
#[doc = "0x1c - Monitor mode control register."]
pub mmctrl: MMCTRL,
#[doc = "0x20..0x2c - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub adr: [ADR; 3],
#[doc = "0x2c - Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub data_buffer: DATA_BUFFER,
#[doc = "0x30..0x40 - I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."]
pub mask: [MASK; 4],
}
impl RegisterBlock {
#[doc = "0x20 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub fn adr1(&self) -> &ADR {
&self.adr[0]
}
#[doc = "0x24 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub fn adr2(&self) -> &ADR {
&self.adr[1]
}
#[doc = "0x28 - I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
#[inline(always)]
pub fn adr3(&self) -> &ADR {
&self.adr[2]
}
}
#[doc = "CONSET (rw) register accessor: an alias for `Reg<CONSET_SPEC>`"]
pub type CONSET = crate::Reg<conset::CONSET_SPEC>;
#[doc = "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conset;
#[doc = "STAT (r) register accessor: an alias for `Reg<STAT_SPEC>`"]
pub type STAT = crate::Reg<stat::STAT_SPEC>;
#[doc = "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed."]
pub mod stat;
#[doc = "DAT (rw) register accessor: an alias for `Reg<DAT_SPEC>`"]
pub type DAT = crate::Reg<dat::DAT_SPEC>;
#[doc = "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register."]
pub mod dat;
#[doc = "ADR0 (rw) register accessor: an alias for `Reg<ADR0_SPEC>`"]
pub type ADR0 = crate::Reg<adr0::ADR0_SPEC>;
#[doc = "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr0;
#[doc = "SCLH (rw) register accessor: an alias for `Reg<SCLH_SPEC>`"]
pub type SCLH = crate::Reg<sclh::SCLH_SPEC>;
#[doc = "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock."]
pub mod sclh;
#[doc = "SCLL (rw) register accessor: an alias for `Reg<SCLL_SPEC>`"]
pub type SCLL = crate::Reg<scll::SCLL_SPEC>;
#[doc = "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode."]
pub mod scll;
#[doc = "CONCLR (w) register accessor: an alias for `Reg<CONCLR_SPEC>`"]
pub type CONCLR = crate::Reg<conclr::CONCLR_SPEC>;
#[doc = "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register."]
pub mod conclr;
#[doc = "MMCTRL (rw) register accessor: an alias for `Reg<MMCTRL_SPEC>`"]
pub type MMCTRL = crate::Reg<mmctrl::MMCTRL_SPEC>;
#[doc = "Monitor mode control register."]
pub mod mmctrl;
#[doc = "ADR (rw) register accessor: an alias for `Reg<ADR_SPEC>`"]
pub type ADR = crate::Reg<adr::ADR_SPEC>;
#[doc = "I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address."]
pub mod adr;
#[doc = "DATA_BUFFER (r) register accessor: an alias for `Reg<DATA_BUFFER_SPEC>`"]
pub type DATA_BUFFER = crate::Reg<data_buffer::DATA_BUFFER_SPEC>;
#[doc = "Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus."]
pub mod data_buffer;
#[doc = "MASK (rw) register accessor: an alias for `Reg<MASK_SPEC>`"]
pub type MASK = crate::Reg<mask::MASK_SPEC>;
#[doc = "I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)."]
pub mod mask;