#[doc = "Register `IMSC` reader"]
pub struct R(crate::R<IMSC_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<IMSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<IMSC_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<IMSC_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `IMSC` writer"]
pub struct W(crate::W<IMSC_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<IMSC_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<IMSC_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<IMSC_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `RORIM` reader - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
pub type RORIM_R = crate::BitReader<bool>;
#[doc = "Field `RORIM` writer - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
pub type RORIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>;
#[doc = "Field `RTIM` reader - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."]
pub type RTIM_R = crate::BitReader<bool>;
#[doc = "Field `RTIM` writer - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."]
pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>;
#[doc = "Field `RXIM` reader - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
pub type RXIM_R = crate::BitReader<bool>;
#[doc = "Field `RXIM` writer - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>;
#[doc = "Field `TXIM` reader - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
pub type TXIM_R = crate::BitReader<bool>;
#[doc = "Field `TXIM` writer - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, bool, O>;
impl R {
#[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
#[inline(always)]
pub fn rorim(&self) -> RORIM_R {
RORIM_R::new((self.bits & 1) != 0)
}
#[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."]
#[inline(always)]
pub fn rtim(&self) -> RTIM_R {
RTIM_R::new(((self.bits >> 1) & 1) != 0)
}
#[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
#[inline(always)]
pub fn rxim(&self) -> RXIM_R {
RXIM_R::new(((self.bits >> 2) & 1) != 0)
}
#[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
#[inline(always)]
pub fn txim(&self) -> TXIM_R {
TXIM_R::new(((self.bits >> 3) & 1) != 0)
}
}
impl W {
#[doc = "Bit 0 - Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs."]
#[inline(always)]
pub fn rorim(&mut self) -> RORIM_W<0> {
RORIM_W::new(self)
}
#[doc = "Bit 1 - Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x \\[SCR+1\\])."]
#[inline(always)]
pub fn rtim(&mut self) -> RTIM_W<1> {
RTIM_W::new(self)
}
#[doc = "Bit 2 - Software should set this bit to enable interrupt when the Rx FIFO is at least half full."]
#[inline(always)]
pub fn rxim(&mut self) -> RXIM_W<2> {
RXIM_W::new(self)
}
#[doc = "Bit 3 - Software should set this bit to enable interrupt when the Tx FIFO is at least half empty."]
#[inline(always)]
pub fn txim(&mut self) -> TXIM_W<3> {
TXIM_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt Mask Set and Clear Register.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"]
pub struct IMSC_SPEC;
impl crate::RegisterSpec for IMSC_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [imsc::R](R) reader structure"]
impl crate::Readable for IMSC_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"]
impl crate::Writable for IMSC_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets IMSC to value 0"]
impl crate::Resettable for IMSC_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}