lpc13xx_pac/lpc1342/usb/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RD_EN` reader - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
38pub type RD_EN_R = crate::BitReader<RD_EN_A>;
39#[doc = "Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq)]
41pub enum RD_EN_A {
42    #[doc = "0: Read mode is disabled."]
43    READ_MODE_IS_DISABLE = 0,
44    #[doc = "1: Read mode is enabled."]
45    READ_MODE_IS_ENABLED = 1,
46}
47impl From<RD_EN_A> for bool {
48    #[inline(always)]
49    fn from(variant: RD_EN_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl RD_EN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> RD_EN_A {
57        match self.bits {
58            false => RD_EN_A::READ_MODE_IS_DISABLE,
59            true => RD_EN_A::READ_MODE_IS_ENABLED,
60        }
61    }
62    #[doc = "Checks if the value of the field is `READ_MODE_IS_DISABLE`"]
63    #[inline(always)]
64    pub fn is_read_mode_is_disable(&self) -> bool {
65        *self == RD_EN_A::READ_MODE_IS_DISABLE
66    }
67    #[doc = "Checks if the value of the field is `READ_MODE_IS_ENABLED`"]
68    #[inline(always)]
69    pub fn is_read_mode_is_enabled(&self) -> bool {
70        *self == RD_EN_A::READ_MODE_IS_ENABLED
71    }
72}
73#[doc = "Field `RD_EN` writer - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
74pub type RD_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, RD_EN_A, O>;
75impl<'a, const O: u8> RD_EN_W<'a, O> {
76    #[doc = "Read mode is disabled."]
77    #[inline(always)]
78    pub fn read_mode_is_disable(self) -> &'a mut W {
79        self.variant(RD_EN_A::READ_MODE_IS_DISABLE)
80    }
81    #[doc = "Read mode is enabled."]
82    #[inline(always)]
83    pub fn read_mode_is_enabled(self) -> &'a mut W {
84        self.variant(RD_EN_A::READ_MODE_IS_ENABLED)
85    }
86}
87#[doc = "Field `WR_EN` reader - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
88pub type WR_EN_R = crate::BitReader<WR_EN_A>;
89#[doc = "Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq)]
91pub enum WR_EN_A {
92    #[doc = "0: Write mode is disabled."]
93    WRITE_MODE_IS_DISABL = 0,
94    #[doc = "1: Write mode is enabled."]
95    WRITE_MODE_IS_ENABLE = 1,
96}
97impl From<WR_EN_A> for bool {
98    #[inline(always)]
99    fn from(variant: WR_EN_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl WR_EN_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> WR_EN_A {
107        match self.bits {
108            false => WR_EN_A::WRITE_MODE_IS_DISABL,
109            true => WR_EN_A::WRITE_MODE_IS_ENABLE,
110        }
111    }
112    #[doc = "Checks if the value of the field is `WRITE_MODE_IS_DISABL`"]
113    #[inline(always)]
114    pub fn is_write_mode_is_disabl(&self) -> bool {
115        *self == WR_EN_A::WRITE_MODE_IS_DISABL
116    }
117    #[doc = "Checks if the value of the field is `WRITE_MODE_IS_ENABLE`"]
118    #[inline(always)]
119    pub fn is_write_mode_is_enable(&self) -> bool {
120        *self == WR_EN_A::WRITE_MODE_IS_ENABLE
121    }
122}
123#[doc = "Field `WR_EN` writer - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
124pub type WR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, WR_EN_A, O>;
125impl<'a, const O: u8> WR_EN_W<'a, O> {
126    #[doc = "Write mode is disabled."]
127    #[inline(always)]
128    pub fn write_mode_is_disabl(self) -> &'a mut W {
129        self.variant(WR_EN_A::WRITE_MODE_IS_DISABL)
130    }
131    #[doc = "Write mode is enabled."]
132    #[inline(always)]
133    pub fn write_mode_is_enable(self) -> &'a mut W {
134        self.variant(WR_EN_A::WRITE_MODE_IS_ENABLE)
135    }
136}
137#[doc = "Field `LOG_ENDPOINT` reader - Logical Endpoint number."]
138pub type LOG_ENDPOINT_R = crate::FieldReader<u8, u8>;
139#[doc = "Field `LOG_ENDPOINT` writer - Logical Endpoint number."]
140pub type LOG_ENDPOINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 4, O>;
141impl R {
142    #[doc = "Bit 0 - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
143    #[inline(always)]
144    pub fn rd_en(&self) -> RD_EN_R {
145        RD_EN_R::new((self.bits & 1) != 0)
146    }
147    #[doc = "Bit 1 - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
148    #[inline(always)]
149    pub fn wr_en(&self) -> WR_EN_R {
150        WR_EN_R::new(((self.bits >> 1) & 1) != 0)
151    }
152    #[doc = "Bits 2:5 - Logical Endpoint number."]
153    #[inline(always)]
154    pub fn log_endpoint(&self) -> LOG_ENDPOINT_R {
155        LOG_ENDPOINT_R::new(((self.bits >> 2) & 0x0f) as u8)
156    }
157}
158impl W {
159    #[doc = "Bit 0 - Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData."]
160    #[inline(always)]
161    pub fn rd_en(&mut self) -> RD_EN_W<0> {
162        RD_EN_W::new(self)
163    }
164    #[doc = "Bit 1 - Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent."]
165    #[inline(always)]
166    pub fn wr_en(&mut self) -> WR_EN_W<1> {
167        WR_EN_W::new(self)
168    }
169    #[doc = "Bits 2:5 - Logical Endpoint number."]
170    #[inline(always)]
171    pub fn log_endpoint(&mut self) -> LOG_ENDPOINT_W<2> {
172        LOG_ENDPOINT_W::new(self)
173    }
174    #[doc = "Writes raw bits to the register."]
175    #[inline(always)]
176    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
177        self.0.bits(bits);
178        self
179    }
180}
181#[doc = "USB Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
182pub struct CTRL_SPEC;
183impl crate::RegisterSpec for CTRL_SPEC {
184    type Ux = u32;
185}
186#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
187impl crate::Readable for CTRL_SPEC {
188    type Reader = R;
189}
190#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
191impl crate::Writable for CTRL_SPEC {
192    type Writer = W;
193}
194#[doc = "`reset()` method sets CTRL to value 0"]
195impl crate::Resettable for CTRL_SPEC {
196    #[inline(always)]
197    fn reset_value() -> Self::Ux {
198        0
199    }
200}
lpc13xx_pac/lpc1342/usb/ctrl.rs

lpc13xx_pac/lpc1342/usb/
ctrl.rs
