1#[doc = "Reader of register MMCTRL"]
2pub type R = crate::R<u32, super::MMCTRL>;
3#[doc = "Writer for register MMCTRL"]
4pub type W = crate::W<u32, super::MMCTRL>;
5#[doc = "Register MMCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::MMCTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Monitor mode enable.\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum MM_ENA_A {
16 #[doc = "0: Monitor mode disabled"]
17 MONITOR_MODE_DISABLE,
18 #[doc = "1: The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line"]
19 THE_I2C_MODULE_WILL_,
20}
21impl From<MM_ENA_A> for bool {
22 #[inline(always)]
23 fn from(variant: MM_ENA_A) -> Self {
24 match variant {
25 MM_ENA_A::MONITOR_MODE_DISABLE => false,
26 MM_ENA_A::THE_I2C_MODULE_WILL_ => true,
27 }
28 }
29}
30#[doc = "Reader of field `MM_ENA`"]
31pub type MM_ENA_R = crate::R<bool, MM_ENA_A>;
32impl MM_ENA_R {
33 #[doc = r"Get enumerated values variant"]
34 #[inline(always)]
35 pub fn variant(&self) -> MM_ENA_A {
36 match self.bits {
37 false => MM_ENA_A::MONITOR_MODE_DISABLE,
38 true => MM_ENA_A::THE_I2C_MODULE_WILL_,
39 }
40 }
41 #[doc = "Checks if the value of the field is `MONITOR_MODE_DISABLE`"]
42 #[inline(always)]
43 pub fn is_monitor_mode_disable(&self) -> bool {
44 *self == MM_ENA_A::MONITOR_MODE_DISABLE
45 }
46 #[doc = "Checks if the value of the field is `THE_I2C_MODULE_WILL_`"]
47 #[inline(always)]
48 pub fn is_the_i2c_module_will_(&self) -> bool {
49 *self == MM_ENA_A::THE_I2C_MODULE_WILL_
50 }
51}
52#[doc = "Write proxy for field `MM_ENA`"]
53pub struct MM_ENA_W<'a> {
54 w: &'a mut W,
55}
56impl<'a> MM_ENA_W<'a> {
57 #[doc = r"Writes `variant` to the field"]
58 #[inline(always)]
59 pub fn variant(self, variant: MM_ENA_A) -> &'a mut W {
60 {
61 self.bit(variant.into())
62 }
63 }
64 #[doc = "Monitor mode disabled"]
65 #[inline(always)]
66 pub fn monitor_mode_disable(self) -> &'a mut W {
67 self.variant(MM_ENA_A::MONITOR_MODE_DISABLE)
68 }
69 #[doc = "The I2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I 2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line"]
70 #[inline(always)]
71 pub fn the_i2c_module_will_(self) -> &'a mut W {
72 self.variant(MM_ENA_A::THE_I2C_MODULE_WILL_)
73 }
74 #[doc = r"Sets the field bit"]
75 #[inline(always)]
76 pub fn set_bit(self) -> &'a mut W {
77 self.bit(true)
78 }
79 #[doc = r"Clears the field bit"]
80 #[inline(always)]
81 pub fn clear_bit(self) -> &'a mut W {
82 self.bit(false)
83 }
84 #[doc = r"Writes raw bits to the field"]
85 #[inline(always)]
86 pub fn bit(self, value: bool) -> &'a mut W {
87 self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
88 self.w
89 }
90}
91#[doc = "SCL output enable.\n\nValue on reset: 0"]
92#[derive(Clone, Copy, Debug, PartialEq)]
93pub enum ENA_SCL_A {
94 #[doc = "0: When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line"]
95 HIGH,
96 #[doc = "1: When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt."]
97 NORMAL,
98}
99impl From<ENA_SCL_A> for bool {
100 #[inline(always)]
101 fn from(variant: ENA_SCL_A) -> Self {
102 match variant {
103 ENA_SCL_A::HIGH => false,
104 ENA_SCL_A::NORMAL => true,
105 }
106 }
107}
108#[doc = "Reader of field `ENA_SCL`"]
109pub type ENA_SCL_R = crate::R<bool, ENA_SCL_A>;
110impl ENA_SCL_R {
111 #[doc = r"Get enumerated values variant"]
112 #[inline(always)]
113 pub fn variant(&self) -> ENA_SCL_A {
114 match self.bits {
115 false => ENA_SCL_A::HIGH,
116 true => ENA_SCL_A::NORMAL,
117 }
118 }
119 #[doc = "Checks if the value of the field is `HIGH`"]
120 #[inline(always)]
121 pub fn is_high(&self) -> bool {
122 *self == ENA_SCL_A::HIGH
123 }
124 #[doc = "Checks if the value of the field is `NORMAL`"]
125 #[inline(always)]
126 pub fn is_normal(&self) -> bool {
127 *self == ENA_SCL_A::NORMAL
128 }
129}
130#[doc = "Write proxy for field `ENA_SCL`"]
131pub struct ENA_SCL_W<'a> {
132 w: &'a mut W,
133}
134impl<'a> ENA_SCL_W<'a> {
135 #[doc = r"Writes `variant` to the field"]
136 #[inline(always)]
137 pub fn variant(self, variant: ENA_SCL_A) -> &'a mut W {
138 {
139 self.bit(variant.into())
140 }
141 }
142 #[doc = "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line"]
143 #[inline(always)]
144 pub fn high(self) -> &'a mut W {
145 self.variant(ENA_SCL_A::HIGH)
146 }
147 #[doc = "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt."]
148 #[inline(always)]
149 pub fn normal(self) -> &'a mut W {
150 self.variant(ENA_SCL_A::NORMAL)
151 }
152 #[doc = r"Sets the field bit"]
153 #[inline(always)]
154 pub fn set_bit(self) -> &'a mut W {
155 self.bit(true)
156 }
157 #[doc = r"Clears the field bit"]
158 #[inline(always)]
159 pub fn clear_bit(self) -> &'a mut W {
160 self.bit(false)
161 }
162 #[doc = r"Writes raw bits to the field"]
163 #[inline(always)]
164 pub fn bit(self, value: bool) -> &'a mut W {
165 self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
166 self.w
167 }
168}
169#[doc = "Select interrupt register match.\n\nValue on reset: 0"]
170#[derive(Clone, Copy, Debug, PartialEq)]
171pub enum MATCH_ALL_A {
172 #[doc = "0: When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned"]
173 MATCH,
174 #[doc = "1: When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus"]
175 ANYADDRESS,
176}
177impl From<MATCH_ALL_A> for bool {
178 #[inline(always)]
179 fn from(variant: MATCH_ALL_A) -> Self {
180 match variant {
181 MATCH_ALL_A::MATCH => false,
182 MATCH_ALL_A::ANYADDRESS => true,
183 }
184 }
185}
186#[doc = "Reader of field `MATCH_ALL`"]
187pub type MATCH_ALL_R = crate::R<bool, MATCH_ALL_A>;
188impl MATCH_ALL_R {
189 #[doc = r"Get enumerated values variant"]
190 #[inline(always)]
191 pub fn variant(&self) -> MATCH_ALL_A {
192 match self.bits {
193 false => MATCH_ALL_A::MATCH,
194 true => MATCH_ALL_A::ANYADDRESS,
195 }
196 }
197 #[doc = "Checks if the value of the field is `MATCH`"]
198 #[inline(always)]
199 pub fn is_match_(&self) -> bool {
200 *self == MATCH_ALL_A::MATCH
201 }
202 #[doc = "Checks if the value of the field is `ANYADDRESS`"]
203 #[inline(always)]
204 pub fn is_anyaddress(&self) -> bool {
205 *self == MATCH_ALL_A::ANYADDRESS
206 }
207}
208#[doc = "Write proxy for field `MATCH_ALL`"]
209pub struct MATCH_ALL_W<'a> {
210 w: &'a mut W,
211}
212impl<'a> MATCH_ALL_W<'a> {
213 #[doc = r"Writes `variant` to the field"]
214 #[inline(always)]
215 pub fn variant(self, variant: MATCH_ALL_A) -> &'a mut W {
216 {
217 self.bit(variant.into())
218 }
219 }
220 #[doc = "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned"]
221 #[inline(always)]
222 pub fn match_(self) -> &'a mut W {
223 self.variant(MATCH_ALL_A::MATCH)
224 }
225 #[doc = "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus"]
226 #[inline(always)]
227 pub fn anyaddress(self) -> &'a mut W {
228 self.variant(MATCH_ALL_A::ANYADDRESS)
229 }
230 #[doc = r"Sets the field bit"]
231 #[inline(always)]
232 pub fn set_bit(self) -> &'a mut W {
233 self.bit(true)
234 }
235 #[doc = r"Clears the field bit"]
236 #[inline(always)]
237 pub fn clear_bit(self) -> &'a mut W {
238 self.bit(false)
239 }
240 #[doc = r"Writes raw bits to the field"]
241 #[inline(always)]
242 pub fn bit(self, value: bool) -> &'a mut W {
243 self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
244 self.w
245 }
246}
247impl R {
248 #[doc = "Bit 0 - Monitor mode enable."]
249 #[inline(always)]
250 pub fn mm_ena(&self) -> MM_ENA_R {
251 MM_ENA_R::new((self.bits & 0x01) != 0)
252 }
253 #[doc = "Bit 1 - SCL output enable."]
254 #[inline(always)]
255 pub fn ena_scl(&self) -> ENA_SCL_R {
256 ENA_SCL_R::new(((self.bits >> 1) & 0x01) != 0)
257 }
258 #[doc = "Bit 2 - Select interrupt register match."]
259 #[inline(always)]
260 pub fn match_all(&self) -> MATCH_ALL_R {
261 MATCH_ALL_R::new(((self.bits >> 2) & 0x01) != 0)
262 }
263}
264impl W {
265 #[doc = "Bit 0 - Monitor mode enable."]
266 #[inline(always)]
267 pub fn mm_ena(&mut self) -> MM_ENA_W {
268 MM_ENA_W { w: self }
269 }
270 #[doc = "Bit 1 - SCL output enable."]
271 #[inline(always)]
272 pub fn ena_scl(&mut self) -> ENA_SCL_W {
273 ENA_SCL_W { w: self }
274 }
275 #[doc = "Bit 2 - Select interrupt register match."]
276 #[inline(always)]
277 pub fn match_all(&mut self) -> MATCH_ALL_W {
278 MATCH_ALL_W { w: self }
279 }
280}