lpc11xx/syscon/
wdtoscctrl.rs

1#[doc = "Reader of register WDTOSCCTRL"]
2pub type R = crate::R<u32, super::WDTOSCCTRL>;
3#[doc = "Writer for register WDTOSCCTRL"]
4pub type W = crate::W<u32, super::WDTOSCCTRL>;
5#[doc = "Register WDTOSCCTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::WDTOSCCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `DIVSEL`"]
14pub type DIVSEL_R = crate::R<u8, u8>;
15#[doc = "Write proxy for field `DIVSEL`"]
16pub struct DIVSEL_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> DIVSEL_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u8) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x1f) | ((value as u32) & 0x1f);
24        self.w
25    }
26}
27#[doc = "Select watchdog oscillator analog output frequency (Fclkana).\n\nValue on reset: 0"]
28#[derive(Clone, Copy, Debug, PartialEq)]
29pub enum FREQSEL_A {
30    #[doc = "1: 0.5 MHz"]
31    _0_5_MHZ,
32    #[doc = "2: 0.8 MHz"]
33    _0_8_MHZ,
34    #[doc = "3: 1.1 MHz"]
35    _1_1_MHZ,
36    #[doc = "4: 1.4 MHz"]
37    _1_4_MHZ,
38    #[doc = "5: 1.6 MHz"]
39    _1_6_MHZ,
40    #[doc = "6: 1.8 MHz"]
41    _1_8_MHZ,
42    #[doc = "7: 2.0 MHz"]
43    _2_0_MHZ,
44    #[doc = "8: 2.2 MHz"]
45    _2_2_MHZ,
46    #[doc = "9: 2.4 MHz"]
47    _2_4_MHZ,
48    #[doc = "10: 2.6 MHz"]
49    _2_6_MHZ,
50    #[doc = "11: 2.7 MHz"]
51    _2_7_MHZ,
52    #[doc = "12: 2.9 MHz"]
53    _2_9_MHZ,
54    #[doc = "13: 3.1 MHz"]
55    _3_1_MHZ,
56    #[doc = "14: 3.2 MHz"]
57    _3_2_MHZ,
58    #[doc = "15: 3.4 MHz"]
59    _3_4_MHZ,
60}
61impl From<FREQSEL_A> for u8 {
62    #[inline(always)]
63    fn from(variant: FREQSEL_A) -> Self {
64        match variant {
65            FREQSEL_A::_0_5_MHZ => 1,
66            FREQSEL_A::_0_8_MHZ => 2,
67            FREQSEL_A::_1_1_MHZ => 3,
68            FREQSEL_A::_1_4_MHZ => 4,
69            FREQSEL_A::_1_6_MHZ => 5,
70            FREQSEL_A::_1_8_MHZ => 6,
71            FREQSEL_A::_2_0_MHZ => 7,
72            FREQSEL_A::_2_2_MHZ => 8,
73            FREQSEL_A::_2_4_MHZ => 9,
74            FREQSEL_A::_2_6_MHZ => 10,
75            FREQSEL_A::_2_7_MHZ => 11,
76            FREQSEL_A::_2_9_MHZ => 12,
77            FREQSEL_A::_3_1_MHZ => 13,
78            FREQSEL_A::_3_2_MHZ => 14,
79            FREQSEL_A::_3_4_MHZ => 15,
80        }
81    }
82}
83#[doc = "Reader of field `FREQSEL`"]
84pub type FREQSEL_R = crate::R<u8, FREQSEL_A>;
85impl FREQSEL_R {
86    #[doc = r"Get enumerated values variant"]
87    #[inline(always)]
88    pub fn variant(&self) -> crate::Variant<u8, FREQSEL_A> {
89        use crate::Variant::*;
90        match self.bits {
91            1 => Val(FREQSEL_A::_0_5_MHZ),
92            2 => Val(FREQSEL_A::_0_8_MHZ),
93            3 => Val(FREQSEL_A::_1_1_MHZ),
94            4 => Val(FREQSEL_A::_1_4_MHZ),
95            5 => Val(FREQSEL_A::_1_6_MHZ),
96            6 => Val(FREQSEL_A::_1_8_MHZ),
97            7 => Val(FREQSEL_A::_2_0_MHZ),
98            8 => Val(FREQSEL_A::_2_2_MHZ),
99            9 => Val(FREQSEL_A::_2_4_MHZ),
100            10 => Val(FREQSEL_A::_2_6_MHZ),
101            11 => Val(FREQSEL_A::_2_7_MHZ),
102            12 => Val(FREQSEL_A::_2_9_MHZ),
103            13 => Val(FREQSEL_A::_3_1_MHZ),
104            14 => Val(FREQSEL_A::_3_2_MHZ),
105            15 => Val(FREQSEL_A::_3_4_MHZ),
106            i => Res(i),
107        }
108    }
109    #[doc = "Checks if the value of the field is `_0_5_MHZ`"]
110    #[inline(always)]
111    pub fn is_0_5_mhz(&self) -> bool {
112        *self == FREQSEL_A::_0_5_MHZ
113    }
114    #[doc = "Checks if the value of the field is `_0_8_MHZ`"]
115    #[inline(always)]
116    pub fn is_0_8_mhz(&self) -> bool {
117        *self == FREQSEL_A::_0_8_MHZ
118    }
119    #[doc = "Checks if the value of the field is `_1_1_MHZ`"]
120    #[inline(always)]
121    pub fn is_1_1_mhz(&self) -> bool {
122        *self == FREQSEL_A::_1_1_MHZ
123    }
124    #[doc = "Checks if the value of the field is `_1_4_MHZ`"]
125    #[inline(always)]
126    pub fn is_1_4_mhz(&self) -> bool {
127        *self == FREQSEL_A::_1_4_MHZ
128    }
129    #[doc = "Checks if the value of the field is `_1_6_MHZ`"]
130    #[inline(always)]
131    pub fn is_1_6_mhz(&self) -> bool {
132        *self == FREQSEL_A::_1_6_MHZ
133    }
134    #[doc = "Checks if the value of the field is `_1_8_MHZ`"]
135    #[inline(always)]
136    pub fn is_1_8_mhz(&self) -> bool {
137        *self == FREQSEL_A::_1_8_MHZ
138    }
139    #[doc = "Checks if the value of the field is `_2_0_MHZ`"]
140    #[inline(always)]
141    pub fn is_2_0_mhz(&self) -> bool {
142        *self == FREQSEL_A::_2_0_MHZ
143    }
144    #[doc = "Checks if the value of the field is `_2_2_MHZ`"]
145    #[inline(always)]
146    pub fn is_2_2_mhz(&self) -> bool {
147        *self == FREQSEL_A::_2_2_MHZ
148    }
149    #[doc = "Checks if the value of the field is `_2_4_MHZ`"]
150    #[inline(always)]
151    pub fn is_2_4_mhz(&self) -> bool {
152        *self == FREQSEL_A::_2_4_MHZ
153    }
154    #[doc = "Checks if the value of the field is `_2_6_MHZ`"]
155    #[inline(always)]
156    pub fn is_2_6_mhz(&self) -> bool {
157        *self == FREQSEL_A::_2_6_MHZ
158    }
159    #[doc = "Checks if the value of the field is `_2_7_MHZ`"]
160    #[inline(always)]
161    pub fn is_2_7_mhz(&self) -> bool {
162        *self == FREQSEL_A::_2_7_MHZ
163    }
164    #[doc = "Checks if the value of the field is `_2_9_MHZ`"]
165    #[inline(always)]
166    pub fn is_2_9_mhz(&self) -> bool {
167        *self == FREQSEL_A::_2_9_MHZ
168    }
169    #[doc = "Checks if the value of the field is `_3_1_MHZ`"]
170    #[inline(always)]
171    pub fn is_3_1_mhz(&self) -> bool {
172        *self == FREQSEL_A::_3_1_MHZ
173    }
174    #[doc = "Checks if the value of the field is `_3_2_MHZ`"]
175    #[inline(always)]
176    pub fn is_3_2_mhz(&self) -> bool {
177        *self == FREQSEL_A::_3_2_MHZ
178    }
179    #[doc = "Checks if the value of the field is `_3_4_MHZ`"]
180    #[inline(always)]
181    pub fn is_3_4_mhz(&self) -> bool {
182        *self == FREQSEL_A::_3_4_MHZ
183    }
184}
185#[doc = "Write proxy for field `FREQSEL`"]
186pub struct FREQSEL_W<'a> {
187    w: &'a mut W,
188}
189impl<'a> FREQSEL_W<'a> {
190    #[doc = r"Writes `variant` to the field"]
191    #[inline(always)]
192    pub fn variant(self, variant: FREQSEL_A) -> &'a mut W {
193        unsafe { self.bits(variant.into()) }
194    }
195    #[doc = "0.5 MHz"]
196    #[inline(always)]
197    pub fn _0_5_mhz(self) -> &'a mut W {
198        self.variant(FREQSEL_A::_0_5_MHZ)
199    }
200    #[doc = "0.8 MHz"]
201    #[inline(always)]
202    pub fn _0_8_mhz(self) -> &'a mut W {
203        self.variant(FREQSEL_A::_0_8_MHZ)
204    }
205    #[doc = "1.1 MHz"]
206    #[inline(always)]
207    pub fn _1_1_mhz(self) -> &'a mut W {
208        self.variant(FREQSEL_A::_1_1_MHZ)
209    }
210    #[doc = "1.4 MHz"]
211    #[inline(always)]
212    pub fn _1_4_mhz(self) -> &'a mut W {
213        self.variant(FREQSEL_A::_1_4_MHZ)
214    }
215    #[doc = "1.6 MHz"]
216    #[inline(always)]
217    pub fn _1_6_mhz(self) -> &'a mut W {
218        self.variant(FREQSEL_A::_1_6_MHZ)
219    }
220    #[doc = "1.8 MHz"]
221    #[inline(always)]
222    pub fn _1_8_mhz(self) -> &'a mut W {
223        self.variant(FREQSEL_A::_1_8_MHZ)
224    }
225    #[doc = "2.0 MHz"]
226    #[inline(always)]
227    pub fn _2_0_mhz(self) -> &'a mut W {
228        self.variant(FREQSEL_A::_2_0_MHZ)
229    }
230    #[doc = "2.2 MHz"]
231    #[inline(always)]
232    pub fn _2_2_mhz(self) -> &'a mut W {
233        self.variant(FREQSEL_A::_2_2_MHZ)
234    }
235    #[doc = "2.4 MHz"]
236    #[inline(always)]
237    pub fn _2_4_mhz(self) -> &'a mut W {
238        self.variant(FREQSEL_A::_2_4_MHZ)
239    }
240    #[doc = "2.6 MHz"]
241    #[inline(always)]
242    pub fn _2_6_mhz(self) -> &'a mut W {
243        self.variant(FREQSEL_A::_2_6_MHZ)
244    }
245    #[doc = "2.7 MHz"]
246    #[inline(always)]
247    pub fn _2_7_mhz(self) -> &'a mut W {
248        self.variant(FREQSEL_A::_2_7_MHZ)
249    }
250    #[doc = "2.9 MHz"]
251    #[inline(always)]
252    pub fn _2_9_mhz(self) -> &'a mut W {
253        self.variant(FREQSEL_A::_2_9_MHZ)
254    }
255    #[doc = "3.1 MHz"]
256    #[inline(always)]
257    pub fn _3_1_mhz(self) -> &'a mut W {
258        self.variant(FREQSEL_A::_3_1_MHZ)
259    }
260    #[doc = "3.2 MHz"]
261    #[inline(always)]
262    pub fn _3_2_mhz(self) -> &'a mut W {
263        self.variant(FREQSEL_A::_3_2_MHZ)
264    }
265    #[doc = "3.4 MHz"]
266    #[inline(always)]
267    pub fn _3_4_mhz(self) -> &'a mut W {
268        self.variant(FREQSEL_A::_3_4_MHZ)
269    }
270    #[doc = r"Writes raw bits to the field"]
271    #[inline(always)]
272    pub unsafe fn bits(self, value: u8) -> &'a mut W {
273        self.w.bits = (self.w.bits & !(0x0f << 5)) | (((value as u32) & 0x0f) << 5);
274        self.w
275    }
276}
277impl R {
278    #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64."]
279    #[inline(always)]
280    pub fn divsel(&self) -> DIVSEL_R {
281        DIVSEL_R::new((self.bits & 0x1f) as u8)
282    }
283    #[doc = "Bits 5:8 - Select watchdog oscillator analog output frequency (Fclkana)."]
284    #[inline(always)]
285    pub fn freqsel(&self) -> FREQSEL_R {
286        FREQSEL_R::new(((self.bits >> 5) & 0x0f) as u8)
287    }
288}
289impl W {
290    #[doc = "Bits 0:4 - Select divider for Fclkana. wdt_osc_clk = Fclkana/ (2 x (1 + DIVSEL)) 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64."]
291    #[inline(always)]
292    pub fn divsel(&mut self) -> DIVSEL_W {
293        DIVSEL_W { w: self }
294    }
295    #[doc = "Bits 5:8 - Select watchdog oscillator analog output frequency (Fclkana)."]
296    #[inline(always)]
297    pub fn freqsel(&mut self) -> FREQSEL_W {
298        FREQSEL_W { w: self }
299    }
300}
lpc11xx/syscon/wdtoscctrl.rs

lpc11xx/syscon/
wdtoscctrl.rs
