1#[doc = "Reader of register CTCR"]
2pub type R = crate::R<u32, super::CTCR>;
3#[doc = "Writer for register CTCR"]
4pub type W = crate::W<u32, super::CTCR>;
5#[doc = "Register CTCR `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTCR {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type {
10 0
11 }
12}
13#[doc = "Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge.\n\nValue on reset: 0"]
14#[derive(Clone, Copy, Debug, PartialEq)]
15pub enum CTM_A {
16 #[doc = "0: Timer Mode: every rising PCLK edge"]
17 TIMER_MODE_EVERY_RI,
18 #[doc = "1: Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2"]
19 COUNTER_MODE_TC_IS_RISING,
20 #[doc = "2: Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2"]
21 COUNTER_MODE_TC_IS_FALLING,
22 #[doc = "3: Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2"]
23 COUNTER_MODE_TC_IS_BOTH,
24}
25impl From<CTM_A> for u8 {
26 #[inline(always)]
27 fn from(variant: CTM_A) -> Self {
28 match variant {
29 CTM_A::TIMER_MODE_EVERY_RI => 0,
30 CTM_A::COUNTER_MODE_TC_IS_RISING => 1,
31 CTM_A::COUNTER_MODE_TC_IS_FALLING => 2,
32 CTM_A::COUNTER_MODE_TC_IS_BOTH => 3,
33 }
34 }
35}
36#[doc = "Reader of field `CTM`"]
37pub type CTM_R = crate::R<u8, CTM_A>;
38impl CTM_R {
39 #[doc = r"Get enumerated values variant"]
40 #[inline(always)]
41 pub fn variant(&self) -> CTM_A {
42 match self.bits {
43 0 => CTM_A::TIMER_MODE_EVERY_RI,
44 1 => CTM_A::COUNTER_MODE_TC_IS_RISING,
45 2 => CTM_A::COUNTER_MODE_TC_IS_FALLING,
46 3 => CTM_A::COUNTER_MODE_TC_IS_BOTH,
47 _ => unreachable!(),
48 }
49 }
50 #[doc = "Checks if the value of the field is `TIMER_MODE_EVERY_RI`"]
51 #[inline(always)]
52 pub fn is_timer_mode_every_ri(&self) -> bool {
53 *self == CTM_A::TIMER_MODE_EVERY_RI
54 }
55 #[doc = "Checks if the value of the field is `COUNTER_MODE_TC_IS_RISING`"]
56 #[inline(always)]
57 pub fn is_counter_mode_tc_is_rising(&self) -> bool {
58 *self == CTM_A::COUNTER_MODE_TC_IS_RISING
59 }
60 #[doc = "Checks if the value of the field is `COUNTER_MODE_TC_IS_FALLING`"]
61 #[inline(always)]
62 pub fn is_counter_mode_tc_is_falling(&self) -> bool {
63 *self == CTM_A::COUNTER_MODE_TC_IS_FALLING
64 }
65 #[doc = "Checks if the value of the field is `COUNTER_MODE_TC_IS_BOTH`"]
66 #[inline(always)]
67 pub fn is_counter_mode_tc_is_both(&self) -> bool {
68 *self == CTM_A::COUNTER_MODE_TC_IS_BOTH
69 }
70}
71#[doc = "Write proxy for field `CTM`"]
72pub struct CTM_W<'a> {
73 w: &'a mut W,
74}
75impl<'a> CTM_W<'a> {
76 #[doc = r"Writes `variant` to the field"]
77 #[inline(always)]
78 pub fn variant(self, variant: CTM_A) -> &'a mut W {
79 {
80 self.bits(variant.into())
81 }
82 }
83 #[doc = "Timer Mode: every rising PCLK edge"]
84 #[inline(always)]
85 pub fn timer_mode_every_ri(self) -> &'a mut W {
86 self.variant(CTM_A::TIMER_MODE_EVERY_RI)
87 }
88 #[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2"]
89 #[inline(always)]
90 pub fn counter_mode_tc_is_rising(self) -> &'a mut W {
91 self.variant(CTM_A::COUNTER_MODE_TC_IS_RISING)
92 }
93 #[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2"]
94 #[inline(always)]
95 pub fn counter_mode_tc_is_falling(self) -> &'a mut W {
96 self.variant(CTM_A::COUNTER_MODE_TC_IS_FALLING)
97 }
98 #[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2"]
99 #[inline(always)]
100 pub fn counter_mode_tc_is_both(self) -> &'a mut W {
101 self.variant(CTM_A::COUNTER_MODE_TC_IS_BOTH)
102 }
103 #[doc = r"Writes raw bits to the field"]
104 #[inline(always)]
105 pub fn bits(self, value: u8) -> &'a mut W {
106 self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
107 self.w
108 }
109}
110#[doc = "Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:.\n\nValue on reset: 0"]
111#[derive(Clone, Copy, Debug, PartialEq)]
112pub enum CIS_A {
113 #[doc = "0: CT32Bn_CAP0"]
114 CT32BN_CAP0,
115 #[doc = "1: CT32Bn_CAP1"]
116 CT32BN_CAP1,
117 #[doc = "3: Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000"]
118 RESERVED_NOTE_IF_CO,
119}
120impl From<CIS_A> for u8 {
121 #[inline(always)]
122 fn from(variant: CIS_A) -> Self {
123 match variant {
124 CIS_A::CT32BN_CAP0 => 0,
125 CIS_A::CT32BN_CAP1 => 1,
126 CIS_A::RESERVED_NOTE_IF_CO => 3,
127 }
128 }
129}
130#[doc = "Reader of field `CIS`"]
131pub type CIS_R = crate::R<u8, CIS_A>;
132impl CIS_R {
133 #[doc = r"Get enumerated values variant"]
134 #[inline(always)]
135 pub fn variant(&self) -> CIS_A {
136 match self.bits {
137 0 => CIS_A::CT32BN_CAP0,
138 1 => CIS_A::CT32BN_CAP1,
139 3 => CIS_A::RESERVED_NOTE_IF_CO,
140 _ => unreachable!(),
141 }
142 }
143 #[doc = "Checks if the value of the field is `CT32BN_CAP0`"]
144 #[inline(always)]
145 pub fn is_ct32bn_cap0(&self) -> bool {
146 *self == CIS_A::CT32BN_CAP0
147 }
148 #[doc = "Checks if the value of the field is `CT32BN_CAP1`"]
149 #[inline(always)]
150 pub fn is_ct32bn_cap1(&self) -> bool {
151 *self == CIS_A::CT32BN_CAP1
152 }
153 #[doc = "Checks if the value of the field is `RESERVED_NOTE_IF_CO`"]
154 #[inline(always)]
155 pub fn is_reserved_note_if_co(&self) -> bool {
156 *self == CIS_A::RESERVED_NOTE_IF_CO
157 }
158}
159#[doc = "Write proxy for field `CIS`"]
160pub struct CIS_W<'a> {
161 w: &'a mut W,
162}
163impl<'a> CIS_W<'a> {
164 #[doc = r"Writes `variant` to the field"]
165 #[inline(always)]
166 pub fn variant(self, variant: CIS_A) -> &'a mut W {
167 unsafe { self.bits(variant.into()) }
168 }
169 #[doc = "CT32Bn_CAP0"]
170 #[inline(always)]
171 pub fn ct32bn_cap0(self) -> &'a mut W {
172 self.variant(CIS_A::CT32BN_CAP0)
173 }
174 #[doc = "CT32Bn_CAP1"]
175 #[inline(always)]
176 pub fn ct32bn_cap1(self) -> &'a mut W {
177 self.variant(CIS_A::CT32BN_CAP1)
178 }
179 #[doc = "Reserved Note: If Counter mode is selected in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000"]
180 #[inline(always)]
181 pub fn reserved_note_if_co(self) -> &'a mut W {
182 self.variant(CIS_A::RESERVED_NOTE_IF_CO)
183 }
184 #[doc = r"Writes raw bits to the field"]
185 #[inline(always)]
186 pub unsafe fn bits(self, value: u8) -> &'a mut W {
187 self.w.bits = (self.w.bits & !(0x03 << 2)) | (((value as u32) & 0x03) << 2);
188 self.w
189 }
190}
191#[doc = "Reader of field `ENCC`"]
192pub type ENCC_R = crate::R<bool, bool>;
193#[doc = "Write proxy for field `ENCC`"]
194pub struct ENCC_W<'a> {
195 w: &'a mut W,
196}
197impl<'a> ENCC_W<'a> {
198 #[doc = r"Sets the field bit"]
199 #[inline(always)]
200 pub fn set_bit(self) -> &'a mut W {
201 self.bit(true)
202 }
203 #[doc = r"Clears the field bit"]
204 #[inline(always)]
205 pub fn clear_bit(self) -> &'a mut W {
206 self.bit(false)
207 }
208 #[doc = r"Writes raw bits to the field"]
209 #[inline(always)]
210 pub fn bit(self, value: bool) -> &'a mut W {
211 self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
212 self.w
213 }
214}
215#[doc = "When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero.\n\nValue on reset: 0"]
216#[derive(Clone, Copy, Debug, PartialEq)]
217pub enum SELCC_A {
218 #[doc = "0: Rising Edge of CAP0 clears the timer (if bit 4 is set)"]
219 RISING_EDGE_OF_CAP0_,
220 #[doc = "1: Falling Edge of CAP0 clears the timer (if bit 4 is set)"]
221 FALLING_EDGE_OF_CAP0,
222 #[doc = "2: Rising Edge of CAP1 clears the timer (if bit 4 is set)"]
223 RISING_EDGE_OF_CAP1_,
224 #[doc = "3: Falling Edge of CAP1 clears the timer (if bit 4 is set)"]
225 FALLING_EDGE_OF_CAP1,
226}
227impl From<SELCC_A> for u8 {
228 #[inline(always)]
229 fn from(variant: SELCC_A) -> Self {
230 match variant {
231 SELCC_A::RISING_EDGE_OF_CAP0_ => 0,
232 SELCC_A::FALLING_EDGE_OF_CAP0 => 1,
233 SELCC_A::RISING_EDGE_OF_CAP1_ => 2,
234 SELCC_A::FALLING_EDGE_OF_CAP1 => 3,
235 }
236 }
237}
238#[doc = "Reader of field `SELCC`"]
239pub type SELCC_R = crate::R<u8, SELCC_A>;
240impl SELCC_R {
241 #[doc = r"Get enumerated values variant"]
242 #[inline(always)]
243 pub fn variant(&self) -> crate::Variant<u8, SELCC_A> {
244 use crate::Variant::*;
245 match self.bits {
246 0 => Val(SELCC_A::RISING_EDGE_OF_CAP0_),
247 1 => Val(SELCC_A::FALLING_EDGE_OF_CAP0),
248 2 => Val(SELCC_A::RISING_EDGE_OF_CAP1_),
249 3 => Val(SELCC_A::FALLING_EDGE_OF_CAP1),
250 i => Res(i),
251 }
252 }
253 #[doc = "Checks if the value of the field is `RISING_EDGE_OF_CAP0_`"]
254 #[inline(always)]
255 pub fn is_rising_edge_of_cap0_(&self) -> bool {
256 *self == SELCC_A::RISING_EDGE_OF_CAP0_
257 }
258 #[doc = "Checks if the value of the field is `FALLING_EDGE_OF_CAP0`"]
259 #[inline(always)]
260 pub fn is_falling_edge_of_cap0(&self) -> bool {
261 *self == SELCC_A::FALLING_EDGE_OF_CAP0
262 }
263 #[doc = "Checks if the value of the field is `RISING_EDGE_OF_CAP1_`"]
264 #[inline(always)]
265 pub fn is_rising_edge_of_cap1_(&self) -> bool {
266 *self == SELCC_A::RISING_EDGE_OF_CAP1_
267 }
268 #[doc = "Checks if the value of the field is `FALLING_EDGE_OF_CAP1`"]
269 #[inline(always)]
270 pub fn is_falling_edge_of_cap1(&self) -> bool {
271 *self == SELCC_A::FALLING_EDGE_OF_CAP1
272 }
273}
274#[doc = "Write proxy for field `SELCC`"]
275pub struct SELCC_W<'a> {
276 w: &'a mut W,
277}
278impl<'a> SELCC_W<'a> {
279 #[doc = r"Writes `variant` to the field"]
280 #[inline(always)]
281 pub fn variant(self, variant: SELCC_A) -> &'a mut W {
282 unsafe { self.bits(variant.into()) }
283 }
284 #[doc = "Rising Edge of CAP0 clears the timer (if bit 4 is set)"]
285 #[inline(always)]
286 pub fn rising_edge_of_cap0_(self) -> &'a mut W {
287 self.variant(SELCC_A::RISING_EDGE_OF_CAP0_)
288 }
289 #[doc = "Falling Edge of CAP0 clears the timer (if bit 4 is set)"]
290 #[inline(always)]
291 pub fn falling_edge_of_cap0(self) -> &'a mut W {
292 self.variant(SELCC_A::FALLING_EDGE_OF_CAP0)
293 }
294 #[doc = "Rising Edge of CAP1 clears the timer (if bit 4 is set)"]
295 #[inline(always)]
296 pub fn rising_edge_of_cap1_(self) -> &'a mut W {
297 self.variant(SELCC_A::RISING_EDGE_OF_CAP1_)
298 }
299 #[doc = "Falling Edge of CAP1 clears the timer (if bit 4 is set)"]
300 #[inline(always)]
301 pub fn falling_edge_of_cap1(self) -> &'a mut W {
302 self.variant(SELCC_A::FALLING_EDGE_OF_CAP1)
303 }
304 #[doc = r"Writes raw bits to the field"]
305 #[inline(always)]
306 pub unsafe fn bits(self, value: u8) -> &'a mut W {
307 self.w.bits = (self.w.bits & !(0x07 << 5)) | (((value as u32) & 0x07) << 5);
308 self.w
309 }
310}
311impl R {
312 #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge."]
313 #[inline(always)]
314 pub fn ctm(&self) -> CTM_R {
315 CTM_R::new((self.bits & 0x03) as u8)
316 }
317 #[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:."]
318 #[inline(always)]
319 pub fn cis(&self) -> CIS_R {
320 CIS_R::new(((self.bits >> 2) & 0x03) as u8)
321 }
322 #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
323 #[inline(always)]
324 pub fn encc(&self) -> ENCC_R {
325 ENCC_R::new(((self.bits >> 4) & 0x01) != 0)
326 }
327 #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
328 #[inline(always)]
329 pub fn selcc(&self) -> SELCC_R {
330 SELCC_R::new(((self.bits >> 5) & 0x07) as u8)
331 }
332}
333impl W {
334 #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge."]
335 #[inline(always)]
336 pub fn ctm(&mut self) -> CTM_W {
337 CTM_W { w: self }
338 }
339 #[doc = "Bits 2:3 - Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking:."]
340 #[inline(always)]
341 pub fn cis(&mut self) -> CIS_W {
342 CIS_W { w: self }
343 }
344 #[doc = "Bit 4 - Setting this bit to one enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
345 #[inline(always)]
346 pub fn encc(&mut self) -> ENCC_W {
347 ENCC_W { w: self }
348 }
349 #[doc = "Bits 5:7 - When bit 4 is one, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is zero."]
350 #[inline(always)]
351 pub fn selcc(&mut self) -> SELCC_W {
352 SELCC_W { w: self }
353 }
354}