1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CTCR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `CTM`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum CTMR {
48 #[doc = "Timer Mode: every rising PCLK edge"]
49 TIMER_MODE_EVERY_RI,
50 #[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
51 RISING,
52 #[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
53 FALLING,
54 #[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
55 BOTH,
56}
57impl CTMR {
58 #[doc = r" Value of the field as raw bits"]
59 #[inline]
60 pub fn bits(&self) -> u8 {
61 match *self {
62 CTMR::TIMER_MODE_EVERY_RI => 0,
63 CTMR::RISING => 1,
64 CTMR::FALLING => 2,
65 CTMR::BOTH => 3,
66 }
67 }
68 #[allow(missing_docs)]
69 #[doc(hidden)]
70 #[inline]
71 pub fn _from(value: u8) -> CTMR {
72 match value {
73 0 => CTMR::TIMER_MODE_EVERY_RI,
74 1 => CTMR::RISING,
75 2 => CTMR::FALLING,
76 3 => CTMR::BOTH,
77 _ => unreachable!(),
78 }
79 }
80 #[doc = "Checks if the value of the field is `TIMER_MODE_EVERY_RI`"]
81 #[inline]
82 pub fn is_timer_mode_every_ri(&self) -> bool {
83 *self == CTMR::TIMER_MODE_EVERY_RI
84 }
85 #[doc = "Checks if the value of the field is `RISING`"]
86 #[inline]
87 pub fn is_rising(&self) -> bool {
88 *self == CTMR::RISING
89 }
90 #[doc = "Checks if the value of the field is `FALLING`"]
91 #[inline]
92 pub fn is_falling(&self) -> bool {
93 *self == CTMR::FALLING
94 }
95 #[doc = "Checks if the value of the field is `BOTH`"]
96 #[inline]
97 pub fn is_both(&self) -> bool {
98 *self == CTMR::BOTH
99 }
100}
101#[doc = "Possible values of the field `CIS`"]
102#[derive(Clone, Copy, Debug, PartialEq)]
103pub enum CISR {
104 #[doc = "CT16B0_CAP0."]
105 CT16B0_CAP0,
106 #[doc = "Reserved."]
107 RESERVED_1,
108 #[doc = "CT16B0_CAP1."]
109 CT16B0_CAP1,
110 #[doc = r" Reserved"]
111 _Reserved(u8),
112}
113impl CISR {
114 #[doc = r" Value of the field as raw bits"]
115 #[inline]
116 pub fn bits(&self) -> u8 {
117 match *self {
118 CISR::CT16B0_CAP0 => 0,
119 CISR::RESERVED_1 => 1,
120 CISR::CT16B0_CAP1 => 2,
121 CISR::_Reserved(bits) => bits,
122 }
123 }
124 #[allow(missing_docs)]
125 #[doc(hidden)]
126 #[inline]
127 pub fn _from(value: u8) -> CISR {
128 match value {
129 0 => CISR::CT16B0_CAP0,
130 1 => CISR::RESERVED_1,
131 2 => CISR::CT16B0_CAP1,
132 i => CISR::_Reserved(i),
133 }
134 }
135 #[doc = "Checks if the value of the field is `CT16B0_CAP0`"]
136 #[inline]
137 pub fn is_ct16b0_cap0(&self) -> bool {
138 *self == CISR::CT16B0_CAP0
139 }
140 #[doc = "Checks if the value of the field is `RESERVED_1`"]
141 #[inline]
142 pub fn is_reserved_1(&self) -> bool {
143 *self == CISR::RESERVED_1
144 }
145 #[doc = "Checks if the value of the field is `CT16B0_CAP1`"]
146 #[inline]
147 pub fn is_ct16b0_cap1(&self) -> bool {
148 *self == CISR::CT16B0_CAP1
149 }
150}
151#[doc = r" Value of the field"]
152pub struct ENCCR {
153 bits: bool,
154}
155impl ENCCR {
156 #[doc = r" Value of the field as raw bits"]
157 #[inline]
158 pub fn bit(&self) -> bool {
159 self.bits
160 }
161 #[doc = r" Returns `true` if the bit is clear (0)"]
162 #[inline]
163 pub fn bit_is_clear(&self) -> bool {
164 !self.bit()
165 }
166 #[doc = r" Returns `true` if the bit is set (1)"]
167 #[inline]
168 pub fn bit_is_set(&self) -> bool {
169 self.bit()
170 }
171}
172#[doc = "Possible values of the field `SELCC`"]
173#[derive(Clone, Copy, Debug, PartialEq)]
174pub enum SELCCR {
175 #[doc = "Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
176 RISING_EDGE_OF_CT16B_CAP0,
177 #[doc = "Falling Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
178 FALLING_EDGE_OF_CT16_CAP0,
179 #[doc = "Reserved."]
180 RESERVED_2,
181 #[doc = "Reserved."]
182 RESERVED_3,
183 #[doc = "Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
184 RISING_EDGE_OF_CT16B_CAP1,
185 #[doc = "Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
186 FALLING_EDGE_OF_CT16_CAP1,
187 #[doc = r" Reserved"]
188 _Reserved(u8),
189}
190impl SELCCR {
191 #[doc = r" Value of the field as raw bits"]
192 #[inline]
193 pub fn bits(&self) -> u8 {
194 match *self {
195 SELCCR::RISING_EDGE_OF_CT16B_CAP0 => 0,
196 SELCCR::FALLING_EDGE_OF_CT16_CAP0 => 1,
197 SELCCR::RESERVED_2 => 2,
198 SELCCR::RESERVED_3 => 3,
199 SELCCR::RISING_EDGE_OF_CT16B_CAP1 => 4,
200 SELCCR::FALLING_EDGE_OF_CT16_CAP1 => 5,
201 SELCCR::_Reserved(bits) => bits,
202 }
203 }
204 #[allow(missing_docs)]
205 #[doc(hidden)]
206 #[inline]
207 pub fn _from(value: u8) -> SELCCR {
208 match value {
209 0 => SELCCR::RISING_EDGE_OF_CT16B_CAP0,
210 1 => SELCCR::FALLING_EDGE_OF_CT16_CAP0,
211 2 => SELCCR::RESERVED_2,
212 3 => SELCCR::RESERVED_3,
213 4 => SELCCR::RISING_EDGE_OF_CT16B_CAP1,
214 5 => SELCCR::FALLING_EDGE_OF_CT16_CAP1,
215 i => SELCCR::_Reserved(i),
216 }
217 }
218 #[doc = "Checks if the value of the field is `RISING_EDGE_OF_CT16B_CAP0`"]
219 #[inline]
220 pub fn is_rising_edge_of_ct16b_cap0(&self) -> bool {
221 *self == SELCCR::RISING_EDGE_OF_CT16B_CAP0
222 }
223 #[doc = "Checks if the value of the field is `FALLING_EDGE_OF_CT16_CAP0`"]
224 #[inline]
225 pub fn is_falling_edge_of_ct16_cap0(&self) -> bool {
226 *self == SELCCR::FALLING_EDGE_OF_CT16_CAP0
227 }
228 #[doc = "Checks if the value of the field is `RESERVED_2`"]
229 #[inline]
230 pub fn is_reserved_2(&self) -> bool {
231 *self == SELCCR::RESERVED_2
232 }
233 #[doc = "Checks if the value of the field is `RESERVED_3`"]
234 #[inline]
235 pub fn is_reserved_3(&self) -> bool {
236 *self == SELCCR::RESERVED_3
237 }
238 #[doc = "Checks if the value of the field is `RISING_EDGE_OF_CT16B_CAP1`"]
239 #[inline]
240 pub fn is_rising_edge_of_ct16b_cap1(&self) -> bool {
241 *self == SELCCR::RISING_EDGE_OF_CT16B_CAP1
242 }
243 #[doc = "Checks if the value of the field is `FALLING_EDGE_OF_CT16_CAP1`"]
244 #[inline]
245 pub fn is_falling_edge_of_ct16_cap1(&self) -> bool {
246 *self == SELCCR::FALLING_EDGE_OF_CT16_CAP1
247 }
248}
249#[doc = "Values that can be written to the field `CTM`"]
250pub enum CTMW {
251 #[doc = "Timer Mode: every rising PCLK edge"]
252 TIMER_MODE_EVERY_RI,
253 #[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
254 RISING,
255 #[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
256 FALLING,
257 #[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
258 BOTH,
259}
260impl CTMW {
261 #[allow(missing_docs)]
262 #[doc(hidden)]
263 #[inline]
264 pub fn _bits(&self) -> u8 {
265 match *self {
266 CTMW::TIMER_MODE_EVERY_RI => 0,
267 CTMW::RISING => 1,
268 CTMW::FALLING => 2,
269 CTMW::BOTH => 3,
270 }
271 }
272}
273#[doc = r" Proxy"]
274pub struct _CTMW<'a> {
275 w: &'a mut W,
276}
277impl<'a> _CTMW<'a> {
278 #[doc = r" Writes `variant` to the field"]
279 #[inline]
280 pub fn variant(self, variant: CTMW) -> &'a mut W {
281 {
282 self.bits(variant._bits())
283 }
284 }
285 #[doc = "Timer Mode: every rising PCLK edge"]
286 #[inline]
287 pub fn timer_mode_every_ri(self) -> &'a mut W {
288 self.variant(CTMW::TIMER_MODE_EVERY_RI)
289 }
290 #[doc = "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2."]
291 #[inline]
292 pub fn rising(self) -> &'a mut W {
293 self.variant(CTMW::RISING)
294 }
295 #[doc = "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2."]
296 #[inline]
297 pub fn falling(self) -> &'a mut W {
298 self.variant(CTMW::FALLING)
299 }
300 #[doc = "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2."]
301 #[inline]
302 pub fn both(self) -> &'a mut W {
303 self.variant(CTMW::BOTH)
304 }
305 #[doc = r" Writes raw bits to the field"]
306 #[inline]
307 pub fn bits(self, value: u8) -> &'a mut W {
308 const MASK: u8 = 3;
309 const OFFSET: u8 = 0;
310 self.w.bits &= !((MASK as u32) << OFFSET);
311 self.w.bits |= ((value & MASK) as u32) << OFFSET;
312 self.w
313 }
314}
315#[doc = "Values that can be written to the field `CIS`"]
316pub enum CISW {
317 #[doc = "CT16B0_CAP0."]
318 CT16B0_CAP0,
319 #[doc = "Reserved."]
320 RESERVED_1,
321 #[doc = "CT16B0_CAP1."]
322 CT16B0_CAP1,
323}
324impl CISW {
325 #[allow(missing_docs)]
326 #[doc(hidden)]
327 #[inline]
328 pub fn _bits(&self) -> u8 {
329 match *self {
330 CISW::CT16B0_CAP0 => 0,
331 CISW::RESERVED_1 => 1,
332 CISW::CT16B0_CAP1 => 2,
333 }
334 }
335}
336#[doc = r" Proxy"]
337pub struct _CISW<'a> {
338 w: &'a mut W,
339}
340impl<'a> _CISW<'a> {
341 #[doc = r" Writes `variant` to the field"]
342 #[inline]
343 pub fn variant(self, variant: CISW) -> &'a mut W {
344 unsafe { self.bits(variant._bits()) }
345 }
346 #[doc = "CT16B0_CAP0."]
347 #[inline]
348 pub fn ct16b0_cap0(self) -> &'a mut W {
349 self.variant(CISW::CT16B0_CAP0)
350 }
351 #[doc = "Reserved."]
352 #[inline]
353 pub fn reserved_1(self) -> &'a mut W {
354 self.variant(CISW::RESERVED_1)
355 }
356 #[doc = "CT16B0_CAP1."]
357 #[inline]
358 pub fn ct16b0_cap1(self) -> &'a mut W {
359 self.variant(CISW::CT16B0_CAP1)
360 }
361 #[doc = r" Writes raw bits to the field"]
362 #[inline]
363 pub unsafe fn bits(self, value: u8) -> &'a mut W {
364 const MASK: u8 = 3;
365 const OFFSET: u8 = 2;
366 self.w.bits &= !((MASK as u32) << OFFSET);
367 self.w.bits |= ((value & MASK) as u32) << OFFSET;
368 self.w
369 }
370}
371#[doc = r" Proxy"]
372pub struct _ENCCW<'a> {
373 w: &'a mut W,
374}
375impl<'a> _ENCCW<'a> {
376 #[doc = r" Sets the field bit"]
377 pub fn set_bit(self) -> &'a mut W {
378 self.bit(true)
379 }
380 #[doc = r" Clears the field bit"]
381 pub fn clear_bit(self) -> &'a mut W {
382 self.bit(false)
383 }
384 #[doc = r" Writes raw bits to the field"]
385 #[inline]
386 pub fn bit(self, value: bool) -> &'a mut W {
387 const MASK: bool = true;
388 const OFFSET: u8 = 4;
389 self.w.bits &= !((MASK as u32) << OFFSET);
390 self.w.bits |= ((value & MASK) as u32) << OFFSET;
391 self.w
392 }
393}
394#[doc = "Values that can be written to the field `SELCC`"]
395pub enum SELCCW {
396 #[doc = "Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
397 RISING_EDGE_OF_CT16B_CAP0,
398 #[doc = "Falling Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
399 FALLING_EDGE_OF_CT16_CAP0,
400 #[doc = "Reserved."]
401 RESERVED_2,
402 #[doc = "Reserved."]
403 RESERVED_3,
404 #[doc = "Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
405 RISING_EDGE_OF_CT16B_CAP1,
406 #[doc = "Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
407 FALLING_EDGE_OF_CT16_CAP1,
408}
409impl SELCCW {
410 #[allow(missing_docs)]
411 #[doc(hidden)]
412 #[inline]
413 pub fn _bits(&self) -> u8 {
414 match *self {
415 SELCCW::RISING_EDGE_OF_CT16B_CAP0 => 0,
416 SELCCW::FALLING_EDGE_OF_CT16_CAP0 => 1,
417 SELCCW::RESERVED_2 => 2,
418 SELCCW::RESERVED_3 => 3,
419 SELCCW::RISING_EDGE_OF_CT16B_CAP1 => 4,
420 SELCCW::FALLING_EDGE_OF_CT16_CAP1 => 5,
421 }
422 }
423}
424#[doc = r" Proxy"]
425pub struct _SELCCW<'a> {
426 w: &'a mut W,
427}
428impl<'a> _SELCCW<'a> {
429 #[doc = r" Writes `variant` to the field"]
430 #[inline]
431 pub fn variant(self, variant: SELCCW) -> &'a mut W {
432 unsafe { self.bits(variant._bits()) }
433 }
434 #[doc = "Rising Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
435 #[inline]
436 pub fn rising_edge_of_ct16b_cap0(self) -> &'a mut W {
437 self.variant(SELCCW::RISING_EDGE_OF_CT16B_CAP0)
438 }
439 #[doc = "Falling Edge of CT16B0_CAP0 clears the timer (if bit 4 is set)."]
440 #[inline]
441 pub fn falling_edge_of_ct16_cap0(self) -> &'a mut W {
442 self.variant(SELCCW::FALLING_EDGE_OF_CT16_CAP0)
443 }
444 #[doc = "Reserved."]
445 #[inline]
446 pub fn reserved_2(self) -> &'a mut W {
447 self.variant(SELCCW::RESERVED_2)
448 }
449 #[doc = "Reserved."]
450 #[inline]
451 pub fn reserved_3(self) -> &'a mut W {
452 self.variant(SELCCW::RESERVED_3)
453 }
454 #[doc = "Rising Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
455 #[inline]
456 pub fn rising_edge_of_ct16b_cap1(self) -> &'a mut W {
457 self.variant(SELCCW::RISING_EDGE_OF_CT16B_CAP1)
458 }
459 #[doc = "Falling Edge of CT16B0_CAP1 clears the timer (if bit 4 is set)."]
460 #[inline]
461 pub fn falling_edge_of_ct16_cap1(self) -> &'a mut W {
462 self.variant(SELCCW::FALLING_EDGE_OF_CT16_CAP1)
463 }
464 #[doc = r" Writes raw bits to the field"]
465 #[inline]
466 pub unsafe fn bits(self, value: u8) -> &'a mut W {
467 const MASK: u8 = 7;
468 const OFFSET: u8 = 5;
469 self.w.bits &= !((MASK as u32) << OFFSET);
470 self.w.bits |= ((value & MASK) as u32) << OFFSET;
471 self.w
472 }
473}
474impl R {
475 #[doc = r" Value of the register as raw bits"]
476 #[inline]
477 pub fn bits(&self) -> u32 {
478 self.bits
479 }
480 #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
481 #[inline]
482 pub fn ctm(&self) -> CTMR {
483 CTMR::_from({
484 const MASK: u8 = 3;
485 const OFFSET: u8 = 0;
486 ((self.bits >> OFFSET) & MASK as u32) as u8
487 })
488 }
489 #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved."]
490 #[inline]
491 pub fn cis(&self) -> CISR {
492 CISR::_from({
493 const MASK: u8 = 3;
494 const OFFSET: u8 = 2;
495 ((self.bits >> OFFSET) & MASK as u32) as u8
496 })
497 }
498 #[doc = "Bit 4 - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
499 #[inline]
500 pub fn encc(&self) -> ENCCR {
501 let bits = {
502 const MASK: bool = true;
503 const OFFSET: u8 = 4;
504 ((self.bits >> OFFSET) & MASK as u32) != 0
505 };
506 ENCCR { bits }
507 }
508 #[doc = "Bits 5:7 - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
509 #[inline]
510 pub fn selcc(&self) -> SELCCR {
511 SELCCR::_from({
512 const MASK: u8 = 7;
513 const OFFSET: u8 = 5;
514 ((self.bits >> OFFSET) & MASK as u32) as u8
515 })
516 }
517}
518impl W {
519 #[doc = r" Reset value of the register"]
520 #[inline]
521 pub fn reset_value() -> W {
522 W { bits: 0 }
523 }
524 #[doc = r" Writes raw bits to the register"]
525 #[inline]
526 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
527 self.bits = bits;
528 self
529 }
530 #[doc = "Bits 0:1 - Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). If Counter mode is selected in the CTCR, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000."]
531 #[inline]
532 pub fn ctm(&mut self) -> _CTMW {
533 _CTMW { w: self }
534 }
535 #[doc = "Bits 2:3 - Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin or comparator output is sampled for clocking. Values 0x1 and 0x3 are reserved."]
536 #[inline]
537 pub fn cis(&mut self) -> _CISW {
538 _CISW { w: self }
539 }
540 #[doc = "Bit 4 - Setting this bit to 1 enables clearing of the timer and the prescaler when the capture-edge event specified in bits 7:5 occurs."]
541 #[inline]
542 pub fn encc(&mut self) -> _ENCCW {
543 _ENCCW { w: self }
544 }
545 #[doc = "Bits 5:7 - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved."]
546 #[inline]
547 pub fn selcc(&mut self) -> _SELCCW {
548 _SELCCW { w: self }
549 }
550}