logiclib/
lib.rs

1//! A logic library containing the compiled truth tables of a
2//! VLSI cell library.
3//!
4//! We accept parsed Liberty file ([`libertyparse::Liberty`]) as
5//! input, and will output a flattened truth table list.
6//!
7//! The truth table is special in that:
8//! 1. The truth table is related to every output pin, instead of
9//!    every cell.
10//! 2. Both sequential and combinational elements can be modeled.
11//!    Sequential elements have internal states. The state transition
12//!    can be either modeled by R/F events (e.g., flip-flops), or
13//!    pure 0/1 states (e.g., latches), or any their combination.
14//! 3. There are 5 basic states: 0, 1, X, Z, UNK. UNK stands for
15//!    unknown input. In reality, it can be any of 0, 1, X, Z.
16//!    For FF clock pins, we have 7 basic states, the above 5 + R, F.
17
18use indexmap::IndexMap;
19use compact_str::CompactString;
20use zeroable::Zeroable;
21use ulib::UVec;
22use std::hash::Hash;
23
24/// The inputs and outputs of logic.
25/// 
26/// The number assignments should satisfy
27/// {LHXZ} = 0..4, {LHXZU} = 0..5, and {LHXZURF} = 0..7,
28/// because they are used as compressed table index.
29#[cfg_attr(feature = "cuda", derive(cust::DeviceCopy))]
30#[derive(Debug, Copy, Clone, PartialEq, Eq, Zeroable, Hash)]
31#[repr(u8)]
32pub enum LogicVal {
33    L = 0, H = 1, X = 2, Z = 3,
34    U = 4,
35    R = 5, F = 6
36}
37
38impl From<u8> for LogicVal {
39    fn from(v: u8) -> LogicVal {
40        use LogicVal::*;
41        match v {
42            0 => L, 1 => H, 2 => X, 3 => Z,
43            4 => U,
44            5 => R, 6 => F,
45            _ => unreachable!()
46        }
47    }
48}
49
50/// The entry of logic library.
51///
52/// Marked read only outside the crate.
53#[readonly::make]
54#[derive(Debug)]
55pub struct LogicLib {
56    /// All cells.
57    pub logic_cells: IndexMap<CompactString, LogicCell>,
58    /// The flattened logic truth table.
59    ///
60    /// Each table of pin consists of a consecutive range in
61    /// this table.
62    /// 
63    /// The encoding of states is **little-endian**.
64    /// As a result, the state->array transition is forward,
65    /// but the array->state transition is backward.
66    /// 
67    /// * RF-sensitive pins take 01XZURF as 0, 1, 2, 3, 4, 5, 6;
68    /// * other normal pins take 01XZU as 0, 1, 2, 3, 4;
69    /// * internal pins take 01XZ as 0, 1, 2, 3.
70    /// * Output is either 01XZ as 0, 1, 2, 3, or all U's (4's)
71    pub truthtable: UVec<LogicVal>
72}
73
74/// A logic cell.
75#[derive(Debug)]
76pub struct LogicCell {
77    /// The output pins are mapped to functions.
78    /// 
79    /// Some pins can fail to build their logic. They will instead
80    /// record an error type in this map.
81    pub output_pins: IndexMap<
82            CompactString, Result<LogicOutputPin, &'static str>>
83}
84
85/// An output pin of logic cell.
86/// 
87/// This struct contains essentially the metadata of related input
88/// pins and a pointer to the flattened table.
89#[derive(Debug)]
90pub struct LogicOutputPin {
91    /// The set of related input names. Not including the internal
92    /// states.
93    ///
94    /// This IndexMap has order, which is used as the truthtable
95    /// array index order.
96    ///
97    /// The bool value of the map indicates whether it is
98    /// *RF-sensitive*.
99    /// If true, it will take 01XZURF in the truth table.
100    /// Otherwise, it will take 01XZU.
101    pub related_inputs: IndexMap<CompactString, bool>,
102    /// The number of internal states.
103    /// 
104    /// All internal states take 01XZ.
105    pub num_internals: u8,
106    /// The size of truth table (in the number of `u8`s).
107    /// It should be:
108    /// `(5 or 7).pow(related_inputs.len()) * 4.pow(num_internals) * (1 + num_internals)`
109    pub table_size: usize,
110    /// The starting index of truth table.
111    ///
112    /// In implementation, we have two passes. The first pass
113    /// only computes the table size and start. The second pass
114    /// actually fills in the table elements in the global array.
115    pub table_start: usize
116}
117
118mod combinational;
119mod sequential;
120
121mod builder;
logiclib/lib.rs

logiclib/
lib.rs
