Struct logiclib::LogicLib

pub struct LogicLib {
    pub logic_cells: IndexMap<CompactString, LogicCell>,
    pub truthtable: Vec<LogicVal>,
}

The entry of logic library.

Marked read only outside the crate.

Fields

logic_cells: IndexMap<CompactString, LogicCell>

All cells.

truthtable: Vec<LogicVal>

The flattened logic truth table.

Each table of pin consists of a consecutive range in this table.

The encoding of states is little-endian. As a result, the array->state transition is forward, but the state->array transition is backward.

• RF-sensitive pins take 01XZURF as 0, 1, 2, 3, 4, 5, 6;
• other normal pins take 01XZU as 0, 1, 2, 3, 4;
• internal pins take 01XZ as 0, 1, 2, 3.
• Output is either 01XZ as 0, 1, 2, 3, or all U’s (4’s)

Implementations

impl LogicLib

pub fn from(liberty: &Liberty) -> LogicLib

Build the logic library from a parsed liberty library.

Trait Implementations

impl Debug for LogicLib

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.