logical 0.2.1

Library for simulating digital circuit networks.
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use std::sync::RwLock;

mod portconnector;
mod portdirection;
mod pport;

pub(crate) use self::portconnector::PortConnector;

pub use self::portdirection::{Dir, InOut, Input, MaybeRead, MaybeWrite, Off, Output, PortDirection, Read, Write};
pub use self::pport::Port;

#[derive(Debug)]
pub(crate) struct InnerPort<T> {
    value: RwLock<T>,
}