llvm-native-core 0.1.9

LLVM-native core semantic engine — IR, CodeGen, X86 MC, Clang frontend pipeline
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//! Synopsys ARC Target Backend — 32-bit RISC processor.
//!
//! The ARC (Argonaut RISC Core) is a configurable 32-bit RISC processor
//! widely used in embedded systems, automotive, storage, and IoT.
//! This backend provides complete instruction set metadata, instruction
//! selection, and target machine definition for the ARCv2 ISA.
//!
//! Clean-room behavioral reconstruction from the Synopsys ARC
//! Programmer's Reference Manual, the GCC `arc` backend, and published
//! specifications. Zero LLVM source code consultation.

pub mod arc_instr_info;
pub mod arc_isel;
pub mod arc_target_machine;
pub mod arc_x86_bridge;

pub use arc_instr_info::{ArcInstrDesc, ArcInstrInfo, ArcOpcode};
pub use arc_isel::ArcInstructionSelector;
pub use arc_target_machine::ArcTargetMachine;

/// ARC is a 32-bit architecture.
pub const ARC_POINTER_SIZE: u32 = 4;

/// ARC is little-endian (optionally big-endian ARCompact).
pub const ARC_ENDIANNESS: &str = "little";

/// ARC stack alignment (4 bytes — word aligned).
pub const ARC_STACK_ALIGNMENT: u32 = 4;

/// ARC has a red zone of 0.
pub const ARC_RED_ZONE_SIZE: u32 = 0;

/// Maximum number of ARC GPRs (r0–r31).
pub const ARC_GPR_COUNT: u8 = 32;

/// Register ID base for ARC registers.
pub const ARC_REG_ID_BASE: u32 = 13000;