llvm-native-core 0.1.9

//! AMDGPU Machine Code Encoder — bit-field encoding for all 12 GCN/RDNA
//! instruction formats.
//!
//! Encodes 32-bit and 64-bit instruction words with precise bit-field
//! layout matching each encoding format:
//!
//! **32-bit formats:**
//!   SOP1: [7:0]=opcode [15:8]=sdst [22:16]=ssrc0 [31:23]=0
//!   SOP2: [6:0]=opcode [12:7]=sdst [20:13]=ssrc0 [28:21]=ssrc1 [31:29]=0
//!   SOPK: [4:0]=opcode [9:5]=sdst [25:10]=simm16 [31:26]=0
//!   VOP1: [8:0]=opcode [16:9]=vdst [24:17]=src0 [31:25]=0
//!   VOP2: [5:0]=opcode [13:6]=vdst [21:14]=src0 [29:22]=src1 [31:30]=0
//!   VOPC: [5:0]=opcode [13:6]=vdst [21:14]=src0 [29:22]=src1 [31:30]=0
//!
//! **64-bit formats:**
//!   VOP3: [8:0]=opcode [16:9]=vdst [24:17]=0 [31:25]=1[1] [39:32]=sdst [47:40]=ssrc0 [55:48]=ssrc1 [63:56]=0
//!   SMEM: [7:0]=opcode [15:8]=sdst [23:16]=sbase [31:24]=0 [39:32]=offset [63:40]=0
//!   FLAT: [6:0]=opcode [15:7]=vdst [23:16]=0 [31:24]=0 [39:32]=addr [47:40]=data [63:48]=0
//!   DS:   [7:0]=opcode [15:8]=0 [23:16]=addr [31:24]=data0 [39:32]=data1 [47:40]=offset0 [55:48]=offset1 [63:56]=0
//!
//! Clean-room reconstruction from AMD GCN3/GFX ISA manuals.
//! Zero LLVM source code consultation.

use super::amdgpu_instr_info::{
    AmdgpuEncodingFormat, AmdgpuInstrDesc, AmdgpuInstrInfo, AmdgpuOpcode,
};

// ═══════════════════════════════════════════════════════════════════════════
// AMDGPU MC Encoder
// ═══════════════════════════════════════════════════════════════════════════

/// Encodes AMDGPU instructions into their binary representation.
pub struct AmdgpuMCEncoder {
    /// Instruction info database.
    pub instr_info: AmdgpuInstrInfo,
    /// Encoded output bytes.
    output: Vec<u8>,
}

impl AmdgpuMCEncoder {
    pub fn new() -> Self {
        Self {
            instr_info: AmdgpuInstrInfo::new(),
            output: Vec::new(),
        }
    }

    /// Encode a single instruction with its operands.
    /// `reg_vals` contains register indices or immediate values for each operand.
    pub fn encode(&mut self, opcode: AmdgpuOpcode, reg_vals: &[u32]) -> Vec<u8> {
        self.output.clear();

        let Some(desc) = self.instr_info.get(opcode) else {
            self.output.extend_from_slice(&[0xBF, 0x80, 0x00, 0x00]); // s_nop 0
            return self.output.clone();
        };

        match desc.encoding_format {
            AmdgpuEncodingFormat::SOP1 => self.encode_sop1(opcode, reg_vals),
            AmdgpuEncodingFormat::SOP2 => self.encode_sop2(opcode, reg_vals),
            AmdgpuEncodingFormat::SOPC => self.encode_sopc(opcode, reg_vals),
            AmdgpuEncodingFormat::SOPK => self.encode_sopk(opcode, reg_vals),
            AmdgpuEncodingFormat::SOPP => self.encode_sopp(opcode, reg_vals),
            AmdgpuEncodingFormat::VOP1 => self.encode_vop1(opcode, reg_vals),
            AmdgpuEncodingFormat::VOP2 => self.encode_vop2(opcode, reg_vals),
            AmdgpuEncodingFormat::VOPC => self.encode_vopc(opcode, reg_vals),
            AmdgpuEncodingFormat::VOP3 => self.encode_vop3(opcode, reg_vals),
            AmdgpuEncodingFormat::VOP3P => self.encode_vop3p(opcode, reg_vals),
            AmdgpuEncodingFormat::SMEM => self.encode_smem(opcode, reg_vals),
            AmdgpuEncodingFormat::FLAT => self.encode_flat(opcode, reg_vals),
            AmdgpuEncodingFormat::DS => self.encode_ds(opcode, reg_vals),
            AmdgpuEncodingFormat::MIMG => self.encode_mimg(opcode, reg_vals),
            AmdgpuEncodingFormat::EXP => self.encode_exp(opcode, reg_vals),
            AmdgpuEncodingFormat::VINTRP => self.encode_vintrp(opcode, reg_vals),
        }

        self.output.clone()
    }

    // ── SOP1 Encoding ───────────────────────────────────────────────────
    /// Layout: [7:0]=opcode [15:8]=sdst [22:16]=ssrc0 [31:23]=0
    fn encode_sop1(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.sop1_opcode(opcode);
        let sdst = vals.get(0).copied().unwrap_or(0) & 0x7F;
        let ssrc0 = vals.get(1).copied().unwrap_or(0) & 0x7F;
        let word = enc_opcode | (sdst << 8) | (ssrc0 << 16);
        self.emit32(word);
    }

    // ── SOP2 Encoding ───────────────────────────────────────────────────
    /// Layout: [6:0]=opcode [12:7]=sdst [20:13]=ssrc0 [28:21]=ssrc1 [31:29]=0
    fn encode_sop2(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.sop2_opcode(opcode);
        let sdst = vals.get(0).copied().unwrap_or(0) & 0x7F;
        let ssrc0 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let ssrc1 = vals.get(2).copied().unwrap_or(0) & 0xFF;
        let word = enc_opcode | (sdst << 7) | (ssrc0 << 13) | (ssrc1 << 21);
        self.emit32(word);
    }

    // ── SOPC Encoding ───────────────────────────────────────────────────
    /// Layout: [6:0]=opcode [12:7]=0 [20:13]=ssrc0 [28:21]=ssrc1 [31:29]=0
    fn encode_sopc(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.sopc_opcode(opcode);
        let ssrc0 = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let ssrc1 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let word = enc_opcode | (ssrc0 << 13) | (ssrc1 << 21);
        self.emit32(word);
    }

    // ── SOPK Encoding ───────────────────────────────────────────────────
    /// Layout: [4:0]=opcode [9:5]=sdst [25:10]=simm16 [31:26]=0
    fn encode_sopk(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.sopk_opcode(opcode);
        let sdst = vals.get(0).copied().unwrap_or(0) & 0x1F;
        let simm16 = vals.get(1).copied().unwrap_or(0) & 0xFFFF;
        let word = enc_opcode | (sdst << 5) | (simm16 << 10);
        self.emit32(word);
    }

    // ── SOPP Encoding ───────────────────────────────────────────────────
    /// Layout: [3:0]=opcode [19:4]=simm16 [31:20]=0
    fn encode_sopp(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.sopp_opcode(opcode);
        let simm16 = vals.get(0).copied().unwrap_or(0) & 0xFFFF;
        let word = enc_opcode | (simm16 << 4);
        self.emit32(word);
    }

    // ── VOP1 Encoding ───────────────────────────────────────────────────
    /// Layout: [8:0]=opcode [16:9]=vdst [24:17]=src0 [31:25]=0
    fn encode_vop1(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.vop1_opcode(opcode);
        let vdst = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let src0 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let word = enc_opcode | (vdst << 9) | (src0 << 17);
        self.emit32(word);
    }

    // ── VOP2 Encoding ───────────────────────────────────────────────────
    /// Layout: [5:0]=opcode [13:6]=vdst [21:14]=src0 [29:22]=src1 [31:30]=0
    fn encode_vop2(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.vop2_opcode(opcode);
        let vdst = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let src0 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let src1 = vals.get(2).copied().unwrap_or(0) & 0xFF;
        let word = enc_opcode | (vdst << 6) | (src0 << 14) | (src1 << 22);
        self.emit32(word);
    }

    // ── VOPC Encoding ───────────────────────────────────────────────────
    /// Layout: [5:0]=opcode [13:6]=0 [21:14]=src0 [29:22]=src1 [31:30]=0
    fn encode_vopc(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.vopc_opcode(opcode);
        let src0 = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let src1 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let word = enc_opcode | (src0 << 14) | (src1 << 22);
        self.emit32(word);
    }

    // ── VOP3 Encoding (64-bit) ──────────────────────────────────────────
    /// Layout: Word0=[8:0]=opcode [16:9]=vdst [24:17]=sdst [31:25]=1[1]
    ///         Word1=[7:0]=ssrc0 [15:8]=op_sel/neg [23:16]=ssrc1 [31:24]=ssrc2 [39:32]=0 [47:40]=0 [55:48]=clamp/omod [63:56]=0
    fn encode_vop3(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.vop3_opcode(opcode);
        let vdst = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let sdst = vals.get(1).copied().unwrap_or(0) & 0x7F;
        let src0 = vals.get(2).copied().unwrap_or(0) & 0x1FF;
        let src1 = vals.get(3).copied().unwrap_or(0) & 0x1FF;
        let src2 = vals.get(4).copied().unwrap_or(0) & 0x1FF;

        let word0: u32 = enc_opcode | (vdst << 9) | (sdst << 17) | (1 << 25);
        let word1: u32 = src0 | (src1 << 16) | (src2 << 24);
        self.emit64(word0, word1);
    }

    // ── VOP3P Encoding (64-bit, packed math) ────────────────────────────
    fn encode_vop3p(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        // Same layout as VOP3 with op_sel in word1 bits [11:8]
        self.encode_vop3(opcode, vals);
    }

    // ── SMEM Encoding (64-bit) ──────────────────────────────────────────
    /// Layout: Word0=[7:0]=opcode [15:8]=sdst [23:16]=sbase [31:24]=0
    ///         Word1=[19:0]=offset [63:20]=0
    fn encode_smem(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.smem_opcode(opcode);
        let sdst = vals.get(0).copied().unwrap_or(0) & 0x7F;
        let sbase = vals.get(1).copied().unwrap_or(0) & 0x7F;
        let offset = vals.get(2).copied().unwrap_or(0) & 0xFFFFF;

        let word0: u32 = enc_opcode | (sdst << 8) | (sbase << 16);
        let word1: u32 = offset;
        self.emit64(word0, word1);
    }

    // ── FLAT Encoding (64-bit) ──────────────────────────────────────────
    /// Layout: Word0=[7:0]=opcode [15:8]=vdst [31:16]=0
    ///         Word1=[31:0]=address [63:32]=data (for stores) / 0
    fn encode_flat(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.flat_opcode(opcode);
        let vdst = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let addr = vals.get(1).copied().unwrap_or(0);
        let data = vals.get(2).copied().unwrap_or(0);

        let word0: u32 = enc_opcode | (vdst << 8);
        let word1: u32 = addr;
        self.emit64(word0, word1);
    }

    // ── DS Encoding (64-bit) ────────────────────────────────────────────
    /// Layout: Word0=[7:0]=opcode [15:8]=0 [23:16]=addr [31:24]=data0
    ///         Word1=[7:0]=data1 [15:8]=offset0 [23:16]=offset1 [63:24]=0
    fn encode_ds(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.ds_opcode(opcode);
        let addr = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let data0 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let data1 = vals.get(2).copied().unwrap_or(0) & 0xFF;

        let word0: u32 = enc_opcode | (addr << 16) | (data0 << 24);
        let word1: u32 = data1;
        self.emit64(word0, word1);
    }

    // ── MIMG Encoding (64-bit) ──────────────────────────────────────────
    /// Layout: Word0=[7:0]=opcode [15:8]=vdst [23:16]=vaddr [31:24]=0
    ///         Word1=[3:0]=dmask [7:4]=unorm [11:8]=glc [15:12]=da [19:16]=r128
    ///               [23:20]=tfe [27:24]=lwe [31:28]=0 [39:32]=slc [47:40]=0 [63:48]=0
    fn encode_mimg(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let enc_opcode = self.mimg_opcode(opcode);
        let vdst = vals.get(0).copied().unwrap_or(0) & 0xFF;
        let vaddr = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let dmask = vals.get(2).copied().unwrap_or(0xF) & 0xF; // default full mask

        let word0: u32 = enc_opcode | (vdst << 8) | (vaddr << 16);
        let word1: u32 = dmask;
        self.emit64(word0, word1);
    }

    // ── EXP Encoding (64-bit) ───────────────────────────────────────────
    /// Layout: Word0=[5:0]=target [11:6]=en_mask [15:12]=compr [19:16]=done [23:20]=vm
    ///         Word1=[7:0]=src0 [15:8]=src1 [23:16]=src2 [31:24]=src3
    fn encode_exp(&mut self, opcode: AmdgpuOpcode, vals: &[u32]) {
        let target = self.exp_target(opcode);
        let en_mask = vals.get(0).copied().unwrap_or(0xF) & 0xF;
        let src0 = vals.get(1).copied().unwrap_or(0) & 0xFF;
        let src1 = vals.get(2).copied().unwrap_or(0) & 0xFF;
        let src2 = vals.get(3).copied().unwrap_or(0) & 0xFF;
        let src3 = vals.get(4).copied().unwrap_or(0) & 0xFF;

        let word0: u32 = target | (en_mask << 6) | (1 << 20); // done=1
        let word1: u32 = src0 | (src1 << 8) | (src2 << 16) | (src3 << 24);
        self.emit64(word0, word1);
    }

    // ── VINTRP Encoding ─────────────────────────────────────────────────
    fn encode_vintrp(&mut self, _opcode: AmdgpuOpcode, _vals: &[u32]) {
        // Pixel shader interpolation — 32-bit encoding
        self.emit32(0xD4000000);
    }

    // ── Opcode Encoding Tables ──────────────────────────────────────────

    fn sop1_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SMovB32 => 0x03,
            AmdgpuOpcode::SMovB64 => 0x04,
            AmdgpuOpcode::SNotB32 => 0x0C,
            AmdgpuOpcode::SWqmB32 => 0x10,
            AmdgpuOpcode::SBrevB32 => 0x18,
            AmdgpuOpcode::SAbsI32 => 0x24,
            _ => 0x00,
        }
    }

    fn sop2_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SAddU32 => 0x00,
            AmdgpuOpcode::SSubU32 => 0x01,
            AmdgpuOpcode::SAndB32 => 0x0E,
            AmdgpuOpcode::SOrB32 => 0x0F,
            AmdgpuOpcode::SXorB32 => 0x10,
            AmdgpuOpcode::SMulI32 => 0x12,
            AmdgpuOpcode::SMinU32 => 0x17,
            AmdgpuOpcode::SMaxU32 => 0x18,
            _ => 0x00,
        }
    }

    fn sopc_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SCmpEqI32 => 0x00,
            AmdgpuOpcode::SCmpLgI32 => 0x01,
            AmdgpuOpcode::SCmpGtI32 => 0x02,
            AmdgpuOpcode::SCmpEqU32 => 0x04,
            _ => 0x00,
        }
    }

    fn sopk_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SMovkI32 => 0x00,
            AmdgpuOpcode::SAddkI32 => 0x0F,
            AmdgpuOpcode::SMulkI32 => 0x10,
            _ => 0x00,
        }
    }

    fn sopp_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SNop => 0x00,
            AmdgpuOpcode::SWaitcnt => 0x0C,
            AmdgpuOpcode::SBranch => 0x02,
            AmdgpuOpcode::SEndpgm => 0x01,
            _ => 0x00,
        }
    }

    fn vop1_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::VMovB32 => 0x01,
            AmdgpuOpcode::VRcpF32 => 0x2E,
            AmdgpuOpcode::VSqrtF32 => 0x33,
            AmdgpuOpcode::VLogF32 => 0x35,
            AmdgpuOpcode::VExpF32 => 0x36,
            _ => 0x00,
        }
    }

    fn vop2_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::VAddF32 => 0x03,
            AmdgpuOpcode::VSubF32 => 0x04,
            AmdgpuOpcode::VMulF32 => 0x08,
            AmdgpuOpcode::VMinF32 => 0x0C,
            AmdgpuOpcode::VMaxF32 => 0x0D,
            AmdgpuOpcode::VAndB32 => 0x17,
            AmdgpuOpcode::VOrB32 => 0x18,
            AmdgpuOpcode::VXorB32 => 0x19,
            _ => 0x00,
        }
    }

    fn vopc_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::VCmpF32Eq => 0x02,
            AmdgpuOpcode::VCmpF32Lt => 0x04,
            AmdgpuOpcode::VCmpF32Gt => 0x06,
            _ => 0x00,
        }
    }

    fn vop3_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::VAddF32Vop3 => 0x01C3,
            AmdgpuOpcode::VMulF32Vop3 => 0x01C8,
            AmdgpuOpcode::VFmaF32 => 0x01CB,
            AmdgpuOpcode::VAddF64 => 0x0280,
            AmdgpuOpcode::VMadF32 => 0x01C9,
            _ => 0x00,
        }
    }

    fn smem_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::SLoadDword => 0x00,
            AmdgpuOpcode::SLoadDwordX4 => 0x03,
            AmdgpuOpcode::SStoreDword => 0x10,
            _ => 0x00,
        }
    }

    fn flat_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::FlatLoadDword => 0x10,
            AmdgpuOpcode::FlatStoreDword => 0x18,
            AmdgpuOpcode::GlobalLoadDword => 0x50,
            AmdgpuOpcode::GlobalStoreDword => 0x58,
            _ => 0x00,
        }
    }

    fn ds_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::DsWriteB32 => 0x0D,
            AmdgpuOpcode::DsReadB32 => 0x36,
            AmdgpuOpcode::DsAddU32 => 0x2A,
            _ => 0x00,
        }
    }

    fn mimg_opcode(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::ImageLoad => 0x08,
            AmdgpuOpcode::ImageStore => 0x18,
            AmdgpuOpcode::ImageSample => 0x20,
            _ => 0x00,
        }
    }

    fn exp_target(&self, op: AmdgpuOpcode) -> u32 {
        match op {
            AmdgpuOpcode::ExpMrt0 => 0x00,
            AmdgpuOpcode::ExpPos0 => 0x0C,
            AmdgpuOpcode::ExpParam0 => 0x20,
            AmdgpuOpcode::ExpNull => 0x09,
            _ => 0x00,
        }
    }

    // ── Output Helpers ──────────────────────────────────────────────────

    fn emit32(&mut self, word: u32) {
        self.output.extend_from_slice(&word.to_le_bytes());
    }

    fn emit64(&mut self, word0: u32, word1: u32) {
        self.emit32(word0);
        self.emit32(word1);
    }
}

impl Default for AmdgpuMCEncoder {
    fn default() -> Self {
        Self::new()
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// GPU Generation / GFX Version Selection
// ═══════════════════════════════════════════════════════════════════════════

/// AMD GPU generation identifier for encoding format selection.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum GfxGeneration {
    /// GCN 3rd gen (Fiji, Tonga): GFX8
    Gfx8,
    /// GCN 4th gen (Polaris): GFX8_1
    Gfx8_1,
    /// GCN 5th gen (Vega): GFX9
    Gfx9,
    /// GCN 5th gen refresh (Vega 7nm): GFX9_0_6
    Gfx906,
    /// RDNA 1 (Navi 10/12/14): GFX10_1
    Gfx101,
    /// RDNA 2 (Navi 21/22/23): GFX10_3
    Gfx103,
    /// RDNA 3 (Navi 31/32/33): GFX11
    Gfx11,
}

impl GfxGeneration {
    pub fn from_name(name: &str) -> Option<Self> {
        match name.to_lowercase().as_str() {
            "gfx800" | "gfx801" | "gfx802" | "gfx803" | "gfx804" | "gfx805" => Some(Self::Gfx8),
            "gfx810" | "gfx811" | "gfx812" | "gfx813" => Some(Self::Gfx8_1),
            "gfx900" | "gfx901" | "gfx902" | "gfx903" | "gfx904" | "gfx905" | "gfx909" => {
                Some(Self::Gfx9)
            }
            "gfx906" | "gfx907" | "gfx908" => Some(Self::Gfx906),
            "gfx1010" | "gfx1011" | "gfx1012" | "gfx1013" => Some(Self::Gfx101),
            "gfx1030" | "gfx1031" | "gfx1032" | "gfx1033" | "gfx1034" | "gfx1035" => {
                Some(Self::Gfx103)
            }
            "gfx1100" | "gfx1101" | "gfx1102" | "gfx1103" => Some(Self::Gfx11),
            _ => None,
        }
    }

    pub fn supports_dpp(&self) -> bool {
        matches!(
            self,
            Self::Gfx8 | Self::Gfx8_1 | Self::Gfx9 | Self::Gfx906 | Self::Gfx101 | Self::Gfx103
        )
    }

    pub fn supports_sdwa(&self) -> bool {
        matches!(self, Self::Gfx8 | Self::Gfx8_1 | Self::Gfx9 | Self::Gfx906)
    }

    pub fn supports_vop3p(&self) -> bool {
        matches!(
            self,
            Self::Gfx9 | Self::Gfx906 | Self::Gfx101 | Self::Gfx103 | Self::Gfx11
        )
    }

    pub fn is_rdna(&self) -> bool {
        matches!(self, Self::Gfx101 | Self::Gfx103 | Self::Gfx11)
    }

    pub fn is_gcn(&self) -> bool {
        !self.is_rdna()
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// Full VOP3 Encoding (64-bit, 3 operands)
// ═══════════════════════════════════════════════════════════════════════════

/// VOP3 instruction word layout (64 bits):
///   Word0: [8:0]  = opcode
///          [16:9] = vdst
///          [24:17]= 0
///          [31:25]= 1 (VOP3 marker: bit 25=1, bit 31=1)
///   Word1: [7:0]  = sdst
///          [16:8] = ssrc0
///          [24:17]= ssrc1
///          [31:25]= 0
pub struct Vop3Encoder {
    pub opcode: u16,
    pub vdst: u8,
    pub sdst: u8,
    pub ssrc0: u16,
    pub ssrc1: u8,
    pub src0_mod: u8,
    pub src1_mod: u8,
    pub src2_mod: u8,
    pub opsel: u8,
    pub opsel_hi: u8,
    pub clamp: bool,
    pub omod: u8,
    pub neg_lo: bool,
    pub neg_hi: bool,
}

impl Default for Vop3Encoder {
    fn default() -> Self {
        Vop3Encoder {
            opcode: 0,
            vdst: 0,
            sdst: 0,
            ssrc0: 0,
            ssrc1: 0,
            src0_mod: 0,
            src1_mod: 0,
            src2_mod: 0,
            opsel: 0,
            opsel_hi: 0,
            clamp: false,
            omod: 0,
            neg_lo: false,
            neg_hi: false,
        }
    }
}

impl Vop3Encoder {
    /// Encode the VOP3 instruction as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.opcode as u32) & 0x1FF; // bits [8:0]
        word0 |= ((self.vdst as u32) & 0xFF) << 9; // bits [16:9]
        word0 |= 1 << 25; // VOP3 marker
        word0 |= 1 << 31; // VOP3 encoding bit

        let mut word1: u32 = 0;
        word1 |= (self.sdst as u32) & 0x7F; // bits [6:0]
        word1 |= (self.ssrc0 as u32 & 0x1FF) << 8; // bits [16:8]
        word1 |= (self.ssrc1 as u32 & 0xFF) << 17; // bits [24:17]
        if self.clamp {
            word1 |= 1 << 26; // clamp bit
        }
        word1 |= (self.omod as u32 & 0x3) << 27; // bits [28:27]

        (word0, word1)
    }

    /// Extended encode with opsel and negate bits (RDNA+).
    pub fn encode_extended(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.opcode as u32) & 0x1FF;
        word0 |= ((self.vdst as u32) & 0xFF) << 9;
        word0 |= ((self.opsel as u32) & 0x7) << 17; // opsel lo [19:17]
        word0 |= ((self.opsel_hi as u32) & 0x3) << 21; // opsel hi [22:21]
        if self.neg_lo {
            word0 |= 1 << 23;
        }
        if self.neg_hi {
            word0 |= 1 << 24;
        }
        word0 |= 1 << 25;
        word0 |= 1 << 31;

        let mut word1: u32 = 0;
        word1 |= (self.sdst as u32) & 0x7F;
        word1 |= (self.ssrc0 as u32 & 0x1FF) << 8;
        word1 |= (self.ssrc1 as u32 & 0xFF) << 17;
        word1 |= (self.src0_mod as u32 & 0x3) << 25;
        word1 |= (self.src1_mod as u32 & 0x3) << 27;
        word1 |= (self.src2_mod as u32 & 0x3) << 29;
        if self.clamp {
            word0 |= 1 << 26;
        }

        (word0, word1)
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// VOP3P Encoding (Packed Math, 64-bit)
// ═══════════════════════════════════════════════════════════════════════════

/// VOP3P instruction: packed operations on half-precision or byte data.
/// Used for f16, bf16, i8/u8 packed math.
///   Word0: [6:0]=opcode [14:7]=vdst [22:15]=0 [31:23]=1
///   Word1: [6:0]=sdst [15:7]=ssrc0 [23:16]=ssrc1 [31:24]=0
pub struct Vop3pEncoder {
    pub opcode: u8,
    pub vdst: u8,
    pub sdst: u8,
    pub ssrc0: u16,
    pub ssrc1: u8,
    pub opsel_hi: u8,
    pub neg_lo: u8,
    pub neg_hi: u8,
    pub clamp: bool,
}

impl Default for Vop3pEncoder {
    fn default() -> Self {
        Vop3pEncoder {
            opcode: 0,
            vdst: 0,
            sdst: 0,
            ssrc0: 0,
            ssrc1: 0,
            opsel_hi: 0,
            neg_lo: 0,
            neg_hi: 0,
            clamp: false,
        }
    }
}

impl Vop3pEncoder {
    /// Encode VOP3P as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.opcode as u32) & 0x7F; // bits [6:0]
        word0 |= ((self.vdst as u32) & 0xFF) << 7; // bits [14:7]
        word0 |= ((self.opsel_hi as u32) & 0x3) << 15; // opsel_hi [16:15]
        word0 |= ((self.neg_lo as u32) & 0x7) << 17; // neg_lo [19:17]
        word0 |= ((self.neg_hi as u32) & 0x7) << 20; // neg_hi [22:20]
        if self.clamp {
            word0 |= 1 << 23;
        }
        word0 |= 0x7F << 24; // VOP3P marker: bits [30:24] = all 1s
        word0 |= 1 << 31; // encoding bit

        let mut word1: u32 = 0;
        word1 |= (self.sdst as u32) & 0x7F;
        word1 |= (self.ssrc0 as u32 & 0x1FF) << 8;
        word1 |= (self.ssrc1 as u32 & 0xFF) << 17;

        (word0, word1)
    }

    /// Encode VOP3P with packed fp16 opsel.
    pub fn encode_packed_f16(&self, op_sel: [bool; 4]) -> (u32, u32) {
        let mut opsel = 0u8;
        for (i, sel) in op_sel.iter().enumerate() {
            if *sel {
                opsel |= 1 << i;
            }
        }
        let mut enc = Vop3pEncoder {
            opsel_hi: opsel,
            ..*self
        };
        enc.encode()
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// DPP Encoding (Data Parallel Primitives — GCN)
// ═══════════════════════════════════════════════════════════════════════════

/// DPP (Data Parallel Primitive) control: allows cross-lane operations
/// within a wavefront without using shared memory.
///
/// DPP modifies a VOP1/VOP2 instruction by appending a DPP word:
///   Word1: [8:0]=opcode [16:9]=vdst [24:17]=src0
///   DPP Word: [8:0]=dpp_ctrl [12:9]=bank_mask [16:13]=row_mask
///             [20:17]=bound_ctrl
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DppCtrl {
    /// Quad permute: take value from lane (0-3).
    QuadPerm(u8),
    /// Row shift left by N lanes.
    RowSl(u8),
    /// Row shift right by N lanes.
    RowSr(u8),
    /// Row rotate left by N lanes.
    RowRl(u8),
    /// Row rotate right by N lanes.
    RowRr(u8),
    /// Wavefront shift left.
    WaveSl(u8),
    /// Wavefront shift right.
    WaveSr(u8),
    /// Wavefront rotate left.
    WaveRl(u8),
    /// Wavefront rotate right.
    WaveRr(u8),
    /// Row mirror.
    RowMirror,
    /// Row half mirror.
    RowHalfMirror,
    /// Broadcast 15th lane.
    Bcast15,
    /// Broadcast 31st lane.
    Bcast31,
}

impl DppCtrl {
    /// Encode DPP control into the 9-bit control field.
    pub fn encode(&self) -> u16 {
        match self {
            DppCtrl::QuadPerm(id) => 0x100 | ((id & 0x3) as u16),
            DppCtrl::RowSl(n) => 0x110 | ((n & 0xF) as u16),
            DppCtrl::RowSr(n) => 0x111 | ((n & 0xF) as u16),
            DppCtrl::RowRl(n) => 0x114 | ((n & 0xF) as u16),
            DppCtrl::RowRr(n) => 0x115 | ((n & 0xF) as u16),
            DppCtrl::WaveSl(n) => 0x130 | ((n & 0xF) as u16),
            DppCtrl::WaveSr(n) => 0x131 | ((n & 0xF) as u16),
            DppCtrl::WaveRl(n) => 0x134 | ((n & 0xF) as u16),
            DppCtrl::WaveRr(n) => 0x135 | ((n & 0xF) as u16),
            DppCtrl::RowMirror => 0x140,
            DppCtrl::RowHalfMirror => 0x141,
            DppCtrl::Bcast15 => 0x142,
            DppCtrl::Bcast31 => 0x143,
        }
    }
}

/// DPP modifier for VOP1/VOP2 instructions.
pub struct DppModifier {
    pub ctrl: DppCtrl,
    pub bank_mask: u8,
    pub row_mask: u8,
    pub bound_ctrl: bool,
}

impl DppModifier {
    pub fn new(ctrl: DppCtrl) -> Self {
        DppModifier {
            ctrl,
            bank_mask: 0xF,
            row_mask: 0xF,
            bound_ctrl: false,
        }
    }

    /// Encode the DPP word (32 bits) that follows a VOP1/VOP2 instruction.
    pub fn encode(&self) -> u32 {
        let mut dpp: u32 = 0;
        dpp |= (self.ctrl.encode() as u32) & 0x1FF;
        dpp |= ((self.bank_mask as u32) & 0xF) << 9;
        dpp |= ((self.row_mask as u32) & 0xF) << 13;
        if self.bound_ctrl {
            dpp |= 1 << 17;
        }
        dpp
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// SDWA Encoding (Sub-DWord Addressing — GCN)
// ═══════════════════════════════════════════════════════════════════════════

/// SDWA (Sub-DWord Addressing): operates on sub-32-bit values within
/// VGPRs (byte, short, half). Appends to VOP1/VOP2.
pub struct SdwaModifier {
    pub dst_sel: SdwaSel,
    pub dst_unused: SdwaUnused,
    pub src0_sel: SdwaSel,
    pub src0_sext: bool,
    pub src0_neg: bool,
    pub src0_abs: bool,
    pub src1_sel: SdwaSel,
    pub src1_sext: bool,
    pub src1_neg: bool,
    pub src1_abs: bool,
    pub clamp: bool,
    pub omod: u8,
}

/// SDWA sub-dword selection.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SdwaSel {
    Byte0,
    Byte1,
    Byte2,
    Byte3,
    Word0,
    Word1,
    Dword,
}

impl SdwaSel {
    pub fn encode(&self) -> u8 {
        match self {
            SdwaSel::Byte0 => 0,
            SdwaSel::Byte1 => 1,
            SdwaSel::Byte2 => 2,
            SdwaSel::Byte3 => 3,
            SdwaSel::Word0 => 4,
            SdwaSel::Word1 => 5,
            SdwaSel::Dword => 6,
        }
    }
}

/// SDWA unused field behavior.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SdwaUnused {
    /// Preserve unchanged bits.
    Preserve,
    /// Zero out unused bits.
    Zero,
    /// Sign-extend to 32 bits.
    Sext,
}

impl SdwaUnused {
    pub fn encode(&self) -> u8 {
        match self {
            SdwaUnused::Preserve => 0,
            SdwaUnused::Zero => 1,
            SdwaUnused::Sext => 2,
        }
    }
}

impl Default for SdwaModifier {
    fn default() -> Self {
        SdwaModifier {
            dst_sel: SdwaSel::Dword,
            dst_unused: SdwaUnused::Preserve,
            src0_sel: SdwaSel::Dword,
            src0_sext: false,
            src0_neg: false,
            src0_abs: false,
            src1_sel: SdwaSel::Dword,
            src1_sext: false,
            src1_neg: false,
            src1_abs: false,
            clamp: false,
            omod: 0,
        }
    }
}

impl SdwaModifier {
    /// Encode SDWA as a 32-bit word appended to VOP1/VOP2.
    pub fn encode(&self) -> u32 {
        let mut sdwa: u32 = 0;
        sdwa |= (self.dst_sel.encode() as u32) & 0x7;
        sdwa |= ((self.dst_unused.encode() as u32) & 0x3) << 3;
        if self.clamp {
            sdwa |= 1 << 5;
        }
        sdwa |= ((self.src0_sel.encode() as u32) & 0x7) << 6;
        if self.src0_sext {
            sdwa |= 1 << 9;
        }
        if self.src0_neg {
            sdwa |= 1 << 10;
        }
        if self.src0_abs {
            sdwa |= 1 << 11;
        }
        sdwa |= ((self.src1_sel.encode() as u32) & 0x7) << 12;
        if self.src1_sext {
            sdwa |= 1 << 15;
        }
        if self.src1_neg {
            sdwa |= 1 << 16;
        }
        if self.src1_abs {
            sdwa |= 1 << 17;
        }
        sdwa |= (self.omod as u32 & 0x3) << 18;
        sdwa
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// MUBUF Encoding (Untyped Buffer Operations — 64-bit)
// ═══════════════════════════════════════════════════════════════════════════

/// MUBUF: Memory Untyped Buffer format.
/// Accesses buffer resources with offset, index, and stride.
///   Word0: [6:0]=vdata [13:7]=opcode [25:14]=offset [28:26]=soffset [31:29]=0
///   Word1: [7:0]=srsrc [9:8]=addr64 [15:10]=vaddr [20:16]=slc [24:21]=tfe [31:25]=0
pub struct MubufEncoder {
    pub opcode: u8,
    pub vdata: u8,
    pub vaddr: u8,
    pub srsrc: u8,
    pub soffset: u8,
    pub offset: u16,
    pub slc: bool,    // system-level coherent
    pub glc: bool,    // globally coherent
    pub tfe: bool,    // texture fail enable
    pub idxen: bool,  // index enable
    pub offen: bool,  // offset enable
    pub addr64: bool, // 64-bit addressing
    pub lds: bool,    // load to LDS
}

impl Default for MubufEncoder {
    fn default() -> Self {
        MubufEncoder {
            opcode: 0,
            vdata: 0,
            vaddr: 0,
            srsrc: 0,
            soffset: 0,
            offset: 0,
            slc: false,
            glc: false,
            tfe: false,
            idxen: false,
            offen: false,
            addr64: false,
            lds: false,
        }
    }
}

impl MubufEncoder {
    /// Encode as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.vdata as u32) & 0xFF; // bits [7:0]
        word0 |= ((self.opcode as u32) & 0x7F) << 8; // bits [14:8]
        word0 |= ((self.offset as u32) & 0xFFF) << 15; // bits [26:15]
        word0 |= ((self.soffset as u32) & 0x7) << 27; // bits [29:27]

        let mut word1: u32 = 0;
        word1 |= (self.srsrc as u32) & 0x1F; // bits [4:0]
        if self.lds {
            word1 |= 1 << 5;
        }
        if self.glc {
            word1 |= 1 << 6; // glc
        }
        if self.idxen {
            word1 |= 1 << 7;
        }
        if self.offen {
            word1 |= 1 << 8;
        }
        if self.addr64 {
            word1 |= 1 << 9;
        }
        word1 |= ((self.vaddr as u32) & 0xFF) << 10; // bits [17:10]
        if self.slc {
            word1 |= 1 << 18;
        }
        if self.tfe {
            word1 |= 1 << 19;
        }

        (word0, word1)
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// MTBUF Encoding (Typed Buffer Operations — 64-bit)
// ═══════════════════════════════════════════════════════════════════════════

/// MTBUF: Memory Typed Buffer format.
/// Similar to MUBUF but uses typed data format (dfmt/nfmt).
///   Word0: [6:0]=vdata [10:7]=opcode [22:11]=offset [25:23]=soffset [18:16]=dfmt [22:19]=nfmt
///   Word1: [7:0]=srsrc [9:8]=addr64 [17:10]=vaddr [21:18]=slc [24:22]=tfe [31:25]=0
pub struct MtbufEncoder {
    pub opcode: u8,
    pub vdata: u8,
    pub vaddr: u8,
    pub srsrc: u8,
    pub soffset: u8,
    pub offset: u16,
    pub dfmt: u8, // data format (0-15)
    pub nfmt: u8, // number format (0-7)
    pub slc: bool,
    pub glc: bool,
    pub tfe: bool,
    pub idxen: bool,
    pub offen: bool,
    pub addr64: bool,
}

impl Default for MtbufEncoder {
    fn default() -> Self {
        MtbufEncoder {
            opcode: 0,
            vdata: 0,
            vaddr: 0,
            srsrc: 0,
            soffset: 0,
            offset: 0,
            dfmt: 0,
            nfmt: 0,
            slc: false,
            glc: false,
            tfe: false,
            idxen: false,
            offen: false,
            addr64: false,
        }
    }
}

impl MtbufEncoder {
    /// Encode as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.vdata as u32) & 0xFF;
        word0 |= ((self.opcode as u32) & 0xF) << 8;
        word0 |= ((self.offset as u32) & 0xFFF) << 12;
        word0 |= ((self.soffset as u32) & 0x7) << 24;
        word0 |= ((self.dfmt as u32) & 0xF) << 16;
        word0 |= ((self.nfmt as u32) & 0x7) << 20;

        let mut word1: u32 = 0;
        word1 |= (self.srsrc as u32) & 0x1F;
        if self.glc {
            word1 |= 1 << 6;
        }
        if self.idxen {
            word1 |= 1 << 7;
        }
        if self.offen {
            word1 |= 1 << 8;
        }
        if self.addr64 {
            word1 |= 1 << 9;
        }
        word1 |= ((self.vaddr as u32) & 0xFF) << 10;
        if self.slc {
            word1 |= 1 << 18;
        }
        if self.tfe {
            word1 |= 1 << 19;
        }

        (word0, word1)
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// Image Sample Instructions (MIMG Format — 64-bit)
// ═══════════════════════════════════════════════════════════════════════════

/// MIMG: Memory Image format for texture sampling and image operations.
///   Word0: [7:0]=vdata [15:8]=opcode [19:16]=dmask [24:20]=unrm [31:25]=0
///   Word1: [7:0]=srsrc [11:8]=ssamp [15:12]=dim [22:16]=vaddr [31:23]=0
pub struct MimgEncoder {
    pub opcode: u8,
    pub vdata: u8,
    pub vaddr: u8,
    pub srsrc: u8,
    pub ssamp: u8,
    pub dmask: u8,
    pub unrm: bool,
    pub glc: bool,
    pub slc: bool,
    pub tfe: bool,
    pub da: bool,   // declare array
    pub a16: bool,  // 16-bit addresses
    pub lwe: bool,  // LWE (LOD warn enable)
    pub r128: bool, // 128-bit result
    pub dim: u8,    // image dimension
}

impl Default for MimgEncoder {
    fn default() -> Self {
        MimgEncoder {
            opcode: 0,
            vdata: 0,
            vaddr: 0,
            srsrc: 0,
            ssamp: 0,
            dmask: 0xF,
            unrm: false,
            glc: false,
            slc: false,
            tfe: false,
            da: false,
            a16: false,
            lwe: false,
            r128: false,
            dim: 0,
        }
    }
}

impl MimgEncoder {
    /// Encode as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.vdata as u32) & 0xFF;
        word0 |= ((self.opcode as u32) & 0xFF) << 8;
        word0 |= ((self.dmask as u32) & 0xF) << 16;
        if self.unrm {
            word0 |= 1 << 20;
        }
        if self.glc {
            word0 |= 1 << 21;
        }
        if self.slc {
            word0 |= 1 << 22;
        }
        if self.tfe {
            word0 |= 1 << 23;
        }
        if self.da {
            word0 |= 1 << 24;
        }

        let mut word1: u32 = 0;
        word1 |= (self.srsrc as u32) & 0x1F;
        word1 |= ((self.ssamp as u32) & 0xF) << 5;
        if self.a16 {
            word1 |= 1 << 9;
        }
        if self.lwe {
            word1 |= 1 << 10;
        }
        if self.r128 {
            word1 |= 1 << 11;
        }
        word1 |= ((self.dim as u32) & 0x7) << 12;
        word1 |= ((self.vaddr as u32) & 0xFF) << 16;

        (word0, word1)
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// Export Instruction Encoding (EXP — 64-bit)
// ═══════════════════════════════════════════════════════════════════════════

/// EXP: Export instruction for pixel shader output and vertex parameter
/// export from geometry shaders.
///   Word0: [5:0]=en_mask [11:6]=target [15:12]=compr [22:16]=vsrc0 [29:23]=vsrc1 [31:30]=done/vm
///   Word1: [6:0]=vsrc2 [13:7]=vsrc3 [31:14]=0
pub struct ExpEncoder {
    pub target: u8,
    pub en_mask: u8,
    pub compr: bool,
    pub done: bool,
    pub vm: bool,
    pub vsrc0: u8,
    pub vsrc1: u8,
    pub vsrc2: u8,
    pub vsrc3: u8,
}

impl Default for ExpEncoder {
    fn default() -> Self {
        ExpEncoder {
            target: 0,
            en_mask: 0xF,
            compr: false,
            done: false,
            vm: false,
            vsrc0: 0,
            vsrc1: 0,
            vsrc2: 0,
            vsrc3: 0,
        }
    }
}

impl ExpEncoder {
    /// Encode as two 32-bit words.
    pub fn encode(&self) -> (u32, u32) {
        let mut word0: u32 = 0;
        word0 |= (self.en_mask as u32) & 0xF;
        word0 |= ((self.target as u32) & 0x3F) << 4;
        if self.compr {
            word0 |= 1 << 10;
        }
        word0 |= ((self.vsrc0 as u32) & 0xFF) << 16;
        word0 |= ((self.vsrc1 as u32) & 0xFF) << 23;
        if self.done {
            word0 |= 1 << 30;
        }
        if self.vm {
            word0 |= 1 << 31;
        }

        let mut word1: u32 = 0;
        word1 |= ((self.vsrc2 as u32) & 0xFF) << 0;
        word1 |= ((self.vsrc3 as u32) & 0xFF) << 7;

        (word0, word1)
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// Flat/Global/Scratch Instruction Encoding
// ═══════════════════════════════════════════════════════════════════════════

/// FLAT: Flat addressing instruction (global/scratch).
///   Word0: [7:0]=vdst [14:8]=opcode [15]=glc [17:16]=seg [24:18]=offset [31:25]=0
///   Word1: [6:0]=vaddr [14:7]=saddr [15]=slc [31:16]=0
pub struct FlatEncoder {
    pub opcode: u8,
    pub vdst: u8,
    pub vaddr: u8,
    pub saddr: u8,
    pub offset: u16,
    pub glc: bool,
    pub slc: bool,
    pub segment: FlatSegment,
}

/// FLAT address segment (global, scratch).
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum FlatSegment {
    Global,
    Scratch,
}

impl FlatSegment {
    pub fn encode(&self) -> u8 {
        match self {
            FlatSegment::Global => 0,
            FlatSegment::Scratch => 1,
        }
    }
}

// ═══════════════════════════════════════════════════════════════════════════
// Tests
// ═══════════════════════════════════════════════════════════════════════════

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_encode_sop1() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::SMovB32, &[0, 1]);
        assert_eq!(bytes.len(), 4);
        // s_mov_b32 s0, s1: opcode=0x03, sdst=0, ssrc0=1
        assert_eq!(bytes[0], 0x03);
        assert_eq!(bytes[1], 0x00); // sdst in bits 15:8
        assert_eq!(bytes[2], 0x01); // ssrc0 in bits 22:16 = 1 << 0
    }

    #[test]
    fn test_encode_vop2() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::VAddF32, &[0, 1, 2]);
        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0] & 0x3F, 0x03); // v_add_f32 opcode
    }

    #[test]
    fn test_encode_sopp_nop() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::SNop, &[0]);
        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0] & 0x0F, 0x00); // s_nop opcode
    }

    #[test]
    fn test_encode_smem() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::SLoadDword, &[0, 2, 0]);
        assert_eq!(bytes.len(), 8); // 64-bit instruction
    }

    #[test]
    fn test_encode_flat() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::GlobalLoadDword, &[5, 0x1000, 0]);
        assert_eq!(bytes.len(), 8);
    }

    #[test]
    fn test_encode_ds() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::DsWriteB32, &[0, 42, 0]);
        assert_eq!(bytes.len(), 8);
    }

    #[test]
    fn test_encode_unknown_opcode_graceful() {
        // Using an opcode not in the lookup table should not panic
        let mut enc = AmdgpuMCEncoder::new();
        // AmdgpuOpcode::VCosF32 is a VOP1 but not in the opcode table
        // so it returns 0x00 — still valid encoding
        let bytes = enc.encode(AmdgpuOpcode::SWqmB64, &[0, 0]);
        assert_eq!(bytes.len(), 4);
    }

    #[test]
    fn test_encode_vopc() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::VCmpF32Eq, &[0, 1]);
        assert_eq!(bytes.len(), 4);
        assert_eq!(bytes[0] & 0x3F, 0x02); // v_cmp_eq_f32
    }

    #[test]
    fn test_encode_all_formats_no_panic() {
        let mut enc = AmdgpuMCEncoder::new();
        // Test one opcode from each format doesn't panic
        enc.encode(AmdgpuOpcode::SMovB32, &[0, 0]); // SOP1
        enc.encode(AmdgpuOpcode::SAddU32, &[0, 0, 0]); // SOP2
        enc.encode(AmdgpuOpcode::SCmpEqI32, &[0, 0]); // SOPC
        enc.encode(AmdgpuOpcode::SMovkI32, &[0, 0]); // SOPK
        enc.encode(AmdgpuOpcode::SNop, &[0]); // SOPP
        enc.encode(AmdgpuOpcode::VMovB32, &[0, 0]); // VOP1
        enc.encode(AmdgpuOpcode::VAddF32, &[0, 0, 0]); // VOP2
        enc.encode(AmdgpuOpcode::VCmpF32Eq, &[0, 0]); // VOPC
        enc.encode(AmdgpuOpcode::VAddF32Vop3, &[0, 0, 0, 0, 0]); // VOP3
        enc.encode(AmdgpuOpcode::SLoadDword, &[0, 0, 0]); // SMEM
        enc.encode(AmdgpuOpcode::GlobalLoadDword, &[0, 0, 0]); // FLAT
        enc.encode(AmdgpuOpcode::DsWriteB32, &[0, 0, 0]); // DS
        enc.encode(AmdgpuOpcode::ImageSample, &[0, 0, 0]); // MIMG
        enc.encode(AmdgpuOpcode::ExpMrt0, &[0, 0, 0, 0, 0]); // EXP
    }
}