llvm-native-core 0.1.4

LLVM-native core semantic engine — IR, CodeGen, X86 MC, Clang frontend pipeline
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//! ARM/AArch64 Target Backend — complete register information,
//! instruction set metadata, calling convention implementation,
//! instruction selection, register allocation, frame lowering,
//! MC encoding/decoding, and assembly printer for the ARM
//! architecture family.
//!
//! Clean-room behavioral reconstruction from the ARM Architecture
//! Reference Manual (ARM ARM), AAPCS64/AAPCS procedure call
//! standards, and AArch64/ARM32 instruction set encoding.
//! Zero LLVM source code consultation.
//!
//! Architecture coverage:
//! - AArch64 (ARMv8-A, 64-bit): full GP register set (x0-x30, sp),
//!   3-operand RISC instructions, AAPCS64 calling convention
//! - ARM32 (ARMv7-A, 32-bit): 16 GP registers (r0-r15), conditional
//!   execution, AAPCS calling convention
//! - Thumb/Thumb-2: 16-bit/32-bit compressed instruction sets
//!
//! Modules:
//! - arm_register_info: Complete register definitions (AArch64 + ARM32)
//! - arm_instr_info: Full instruction descriptor table covering AArch64,
//!   ARM32, and Thumb instruction sets
//! - arm_calling_convention: AAPCS64, AAPCS, AAPCS-VFP, and ATPCS
//!   calling convention implementations

pub mod aarch64_deep;
pub mod aarch64_x86_bridge;
pub mod arm_asm_printer;
pub mod arm_calling_convention;
pub mod arm_deep;
pub mod arm_frame_lowering;
pub mod arm_full_instr_info;
pub mod arm_instr_info;
pub mod arm_isel;
pub mod arm_isel_complete;
pub mod arm_isel_sme2;
pub mod arm_isel_sme21;
pub mod arm_isel_sve;
pub mod arm_isel_sve2;
pub mod arm_isel_sve21;
pub mod arm_isel_table;
pub mod arm_mc_decoder;
pub mod arm_mc_encoder;
pub mod arm_optimize;
pub mod arm_register_info;
pub mod arm_schedule_model;
pub mod arm_subtarget;
pub mod arm_target_machine;

// Re-export key types for convenience
pub use aarch64_x86_bridge::{
    A64Cond, A64InstrDesc, A64InstrTable, A64Opcode, AArch64TargetMachine, AllocationOrder,
    BridgeArch, BridgeError, BridgeFeature, BridgeFeatures, BridgeOutput, BridgeStats,
    ComparativeCost, CostEstimate, CrossABIArg, CrossABIClass, CrossABIRet, CrossOptPass,
    CrossPhysReg, CrossRegClass, CrossStackFrame, CrossTargetABI, CrossTargetFrameLowering,
    CrossTargetISel, CrossTargetOptimization, CrossTargetRegAlloc, CrossVarArgs, DAGPattern,
    GenericMachineOpcode, LegalizeAction, LegalizeRule, LiveInterval, MachineIRCond,
    MachineIRFlags, MachineIRInst, MachineIROperand, PatternNode, PatternPredicate, PatternResult,
    SpillSlot, TypeKindRepr, VectorizationHint, X86AArch64Bridge, X86AArch64CostModel,
};
pub use arm_asm_printer::ArmAsmPrinter;
pub use arm_calling_convention::{ArmArgClass, ArmArgInfo, ArmCallFrame, ArmCallingConvention};
pub use arm_frame_lowering::{ArmFrameInfo, ArmFrameLowering};
pub use arm_full_instr_info::{
    ArmFullInstrDesc, ArmFullInstrInfo, ArmFullOpcode, ArmFullOperandClass,
};
pub use arm_instr_info::{ArmInstrDesc, ArmInstrInfo, ArmOpcode, ArmOperandType};
pub use arm_isel::ArmInstructionSelector;
pub use arm_isel_complete::{build_complete_isel_table, CompleteIselEngine, CompleteIselTable};
pub use arm_isel_sme2::{sme2_isel_table, SME2IselEngine, SME2IselTable};
pub use arm_isel_sme21::{
    build_sme21_isel_table, SME21Features, SME21IselEngine, SME21IselStats, SME21IselTable,
};
pub use arm_isel_sve::{sve_isel_table, SVEIselEngine, SVEIselTable};
pub use arm_isel_sve2::{sve2_isel_table, SVE2IselEngine, SVE2IselTable};
pub use arm_isel_sve21::{
    build_sve21_isel_table, SVE21Features, SVE21IselEngine, SVE21IselStats, SVE21IselTable,
};
pub use arm_mc_decoder::ArmMCDecoder;
pub use arm_mc_encoder::{encode_bitmask_imm, encode_immediate_aarch64, ArmCond, ArmMCEncoder};
pub use arm_optimize::ArmPeepholeOptimizer;
pub use arm_register_info::{
    ArmRegClass, ArmRegisterInfo, AARCH64_REG_COUNT, ARM32_REG_COUNT, ARM_MAX_REG_ID,
};
pub use arm_target_machine::{ArmTargetMachine, OptimizationLevel};