llvm-native-core 0.1.2

//! LLVM MCAssembler — assemble MCInst to raw machine code bytes.
//! Phase 3 — LLVM.MC.ASM.1 Court.
//!
//! Clean-room behavioral reconstruction from Intel Software Developer's Manual
//! (Volumes 2A/2B), AMD Architecture Programmer's Manual, and ARM Architecture
//! Reference Manual. Zero LLVM source code consultation.
//!
//! The assembler encodes MCInst → Vec<u8> for each target architecture,
//! producing the raw instruction bytes that constitute machine code.

use crate::mc_inst::{MCInst, MCOperand};
use crate::mc_streamer::x86_opcodes;

// ============================================================================
// X86-64 Instruction Encoder
// ============================================================================

/// X86-64 register encoding: maps our internal reg IDs to 3-bit register fields.
///
/// Our register numbering for 64-bit GP registers:
///   0=rax, 1=rcx, 2=rdx, 3=rbx, 4=rsp, 5=rbp, 6=rsi, 7=rdi
///   8=r8, 9=r9, 10=r10, 11=r11, 12=r12, 13=r13, 14=r14, 15=r15
///
/// 32-bit variants: 16=eax, 17=ecx, 18=edx, 19=ebx, 20=esp, 21=ebp, 22=esi, 23=edi
///
/// For encoding, the 3-bit field is reg_id % 8 (lower 3 bits).
/// REX.B extends the r/m field, REX.R extends the reg field for regs 8-15.
fn x86_64bit_reg(reg_id: u32) -> bool {
    reg_id < 16
}

/// Determine if an MCInst should use 64-bit operand size.
/// size == 0 means default (64-bit in 64-bit mode).
fn inst_is_64bit(inst: &MCInst) -> bool {
    inst.size == 0 || inst.size >= 8
}

fn x86_reg_field(reg_id: u32) -> u8 {
    // For 64-bit regs 0-15, field is reg_id % 8
    // For 32-bit regs 16-23, field is (reg_id - 16) % 8
    if reg_id < 16 {
        (reg_id % 8) as u8
    } else if reg_id < 24 {
        ((reg_id - 16) % 8) as u8
    } else {
        (reg_id % 8) as u8
    }
}

fn x86_reg_needs_rex_b(reg_id: u32) -> bool {
    if reg_id < 16 {
        reg_id >= 8
    } else if reg_id < 24 {
        (reg_id - 16) >= 8
    } else {
        reg_id >= 8
    }
}

fn x86_reg_needs_rex_r(reg_id: u32) -> bool {
    x86_reg_needs_rex_b(reg_id)
}

/// Build a REX prefix byte.
///
/// REX byte format: 0100WRXB
///   W = 1 for 64-bit operand size
///   R = 1 to extend ModRM.reg (registers 8-15)
///   X = 1 to extend SIB.index
///   B = 1 to extend ModRM.rm or SIB.base
fn make_rex(w: bool, r: bool, x: bool, b: bool) -> u8 {
    0x40 | ((w as u8) << 3) | ((r as u8) << 2) | ((x as u8) << 1) | (b as u8)
}

/// Build a ModR/M byte.
///
/// ModR/M format: mod(2) reg/opcode(3) r/m(3)
fn make_modrm(mod_field: u8, reg_opcode: u8, rm: u8) -> u8 {
    ((mod_field & 0x03) << 6) | ((reg_opcode & 0x07) << 3) | (rm & 0x07)
}

/// Build a SIB byte.
///
/// SIB format: scale(2) index(3) base(3)
#[allow(dead_code)]
fn make_sib(scale: u8, index: u8, base: u8) -> u8 {
    ((scale & 0x03) << 6) | ((index & 0x07) << 3) | (base & 0x07)
}

/// Write a signed 32-bit little-endian value to output.
fn push_i32_le(out: &mut Vec<u8>, val: i32) {
    out.extend_from_slice(&val.to_le_bytes());
}

/// Write an unsigned 32-bit little-endian value to output.
#[allow(dead_code)]
fn push_u32_le(out: &mut Vec<u8>, val: u32) {
    out.extend_from_slice(&val.to_le_bytes());
}

/// Write a signed 64-bit little-endian value to output.
fn push_i64_le(out: &mut Vec<u8>, val: i64) {
    out.extend_from_slice(&val.to_le_bytes());
}

/// Encode an X86-64 instruction from an MCInst to raw bytes.
///
/// Returns Some(Vec<u8>) on success, None if the opcode/operand
/// combination is not yet supported.
pub fn encode_x86_64(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.opcode {
        x86_opcodes::NOP => encode_x86_nop(inst),
        x86_opcodes::RET => encode_x86_ret(inst),
        x86_opcodes::PUSH => encode_x86_push(inst),
        x86_opcodes::POP => encode_x86_pop(inst),
        x86_opcodes::MOV => encode_x86_mov(inst),
        x86_opcodes::ADD => encode_x86_add(inst),
        x86_opcodes::SUB => encode_x86_sub(inst),
        x86_opcodes::MUL => encode_x86_mul(inst),
        x86_opcodes::IMUL => encode_x86_imul(inst),
        x86_opcodes::AND => encode_x86_and(inst),
        x86_opcodes::OR => encode_x86_or(inst),
        x86_opcodes::XOR => encode_x86_xor(inst),
        x86_opcodes::CMP => encode_x86_cmp(inst),
        x86_opcodes::JMP => encode_x86_jmp(inst),
        x86_opcodes::CALL => encode_x86_call(inst),
        x86_opcodes::JE => encode_x86_jcc(inst, 0x84),
        x86_opcodes::JNE => encode_x86_jcc(inst, 0x85),
        x86_opcodes::INC => encode_x86_inc(inst),
        x86_opcodes::DEC => encode_x86_dec(inst),
        x86_opcodes::LEA => encode_x86_lea(inst),
        x86_opcodes::NOT => encode_x86_not(inst),
        x86_opcodes::NEG => encode_x86_neg(inst),
        x86_opcodes::SHL => encode_x86_shift(inst, 4),
        x86_opcodes::SHR => encode_x86_shift(inst, 5),
        x86_opcodes::SAR => encode_x86_shift(inst, 7),
        x86_opcodes::DIV => encode_x86_div(inst),
        x86_opcodes::IDIV => encode_x86_idiv(inst),
        x86_opcodes::CDQ => encode_x86_cdq(inst),
        x86_opcodes::CQO => encode_x86_cqo(inst),
        x86_opcodes::MOVSX => encode_x86_movsx(inst),
        x86_opcodes::MOVSXD => encode_x86_movsxd(inst),
        x86_opcodes::MOVZX => encode_x86_movzx(inst),
        x86_opcodes::SETO => encode_x86_setcc(inst, 0x90),
        x86_opcodes::SETNO => encode_x86_setcc(inst, 0x91),
        x86_opcodes::SETB => encode_x86_setcc(inst, 0x92),
        x86_opcodes::SETAE => encode_x86_setcc(inst, 0x93),
        x86_opcodes::SETE => encode_x86_setcc(inst, 0x94),
        x86_opcodes::SETNE => encode_x86_setcc(inst, 0x95),
        x86_opcodes::SETBE => encode_x86_setcc(inst, 0x96),
        x86_opcodes::SETA => encode_x86_setcc(inst, 0x97),
        x86_opcodes::SETS => encode_x86_setcc(inst, 0x98),
        x86_opcodes::SETNS => encode_x86_setcc(inst, 0x99),
        x86_opcodes::SETP => encode_x86_setcc(inst, 0x9A),
        x86_opcodes::SETNP => encode_x86_setcc(inst, 0x9B),
        x86_opcodes::SETL => encode_x86_setcc(inst, 0x9C),
        x86_opcodes::SETGE => encode_x86_setcc(inst, 0x9D),
        x86_opcodes::SETLE => encode_x86_setcc(inst, 0x9E),
        x86_opcodes::SETG => encode_x86_setcc(inst, 0x9F),
        x86_opcodes::CMOVE => encode_x86_cmovcc(inst, 0x44),
        x86_opcodes::CMOVNE => encode_x86_cmovcc(inst, 0x45),
        x86_opcodes::CMOVB => encode_x86_cmovcc(inst, 0x42),
        x86_opcodes::CMOVAE => encode_x86_cmovcc(inst, 0x43),
        x86_opcodes::CMOVBE => encode_x86_cmovcc(inst, 0x46),
        x86_opcodes::CMOVA => encode_x86_cmovcc(inst, 0x47),
        x86_opcodes::CMOVL => encode_x86_cmovcc(inst, 0x4C),
        x86_opcodes::CMOVGE => encode_x86_cmovcc(inst, 0x4D),
        x86_opcodes::CMOVLE => encode_x86_cmovcc(inst, 0x4E),
        x86_opcodes::CMOVG => encode_x86_cmovcc(inst, 0x4F),
        x86_opcodes::LOAD => encode_x86_load(inst),
        x86_opcodes::STORE => encode_x86_store(inst),
        // SSE/SSE2 scalar FP
        x86_opcodes::ADDSS => encode_x86_sse_binary(inst, 0x58, 0xF3),
        x86_opcodes::ADDSD => encode_x86_sse_binary(inst, 0x58, 0xF2),
        x86_opcodes::SUBSS => encode_x86_sse_binary(inst, 0x5C, 0xF3),
        x86_opcodes::SUBSD => encode_x86_sse_binary(inst, 0x5C, 0xF2),
        x86_opcodes::MULSS => encode_x86_sse_binary(inst, 0x59, 0xF3),
        x86_opcodes::MULSD => encode_x86_sse_binary(inst, 0x59, 0xF2),
        x86_opcodes::DIVSS => encode_x86_sse_binary(inst, 0x5E, 0xF3),
        x86_opcodes::DIVSD => encode_x86_sse_binary(inst, 0x5E, 0xF2),
        x86_opcodes::UCOMISS => encode_x86_sse_binary(inst, 0x2E, 0x00),
        x86_opcodes::UCOMISD => encode_x86_sse_binary(inst, 0x2E, 0x66),
        x86_opcodes::MOVSS => encode_x86_sse_binary(inst, 0x10, 0xF3),
        x86_opcodes::MOVSD => encode_x86_sse_binary(inst, 0x10, 0xF2),
        x86_opcodes::XORPS => encode_x86_sse_binary(inst, 0x57, 0x00),
        x86_opcodes::XORPD => encode_x86_sse_binary(inst, 0x57, 0x66),
        x86_opcodes::CVTSI2SS => encode_x86_sse_cvt_i2f(inst, 0x2A, true),
        x86_opcodes::CVTSI2SD => encode_x86_sse_cvt_i2f(inst, 0x2A, false),
        x86_opcodes::CVTTSS2SI => encode_x86_sse_cvt_f2i(inst, 0x2C, true),
        x86_opcodes::CVTTSD2SI => encode_x86_sse_cvt_f2i(inst, 0x2C, false),
        x86_opcodes::MOVD => encode_x86_movd(inst, false, false),
        x86_opcodes::MOVQ => encode_x86_movd(inst, true, false),
        x86_opcodes::MOVD_FROM_XMM => encode_x86_movd(inst, false, true),
        x86_opcodes::MOVQ_FROM_XMM => encode_x86_movd(inst, true, true),
        x86_opcodes::MOVSS_LOAD => encode_x86_sse_mem(inst, 0x10, 0xF3, false),
        x86_opcodes::MOVSD_LOAD => encode_x86_sse_mem(inst, 0x10, 0xF2, false),
        x86_opcodes::MOVSS_STORE => encode_x86_sse_mem(inst, 0x11, 0xF3, true),
        x86_opcodes::MOVSD_STORE => encode_x86_sse_mem(inst, 0x11, 0xF2, true),
        _ => None,
    }
}

// --- Individual instruction encoders ---

/// nop: 0x90
fn encode_x86_nop(_inst: &MCInst) -> Option<Vec<u8>> {
    Some(vec![0x90])
}

/// ret: C3 (near return, no operand)
/// ret imm16: C2 iw
fn encode_x86_ret(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.is_empty() {
        Some(vec![0xC3])
    } else if let Some(MCOperand::Imm(imm)) = inst.operands.first() {
        let mut out = Vec::with_capacity(3);
        out.push(0xC2);
        let imm16 = *imm as u16;
        out.extend_from_slice(&imm16.to_le_bytes());
        Some(out)
    } else {
        None
    }
}

/// push r64: 50+rd
/// push r64 (extended): 41 50+rd (when reg ≥ 8)
fn encode_x86_push(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    if let Some(reg) = inst.operands[0].get_reg() {
        let mut out = Vec::with_capacity(2);
        if reg >= 8 {
            out.push(0x41); // REX.B (no W for push)
        }
        // For push, r/m field in opcode byte encodes the register
        out.push(0x50 + (reg % 8) as u8);
        Some(out)
    } else {
        None
    }
}

/// pop r64: 58+rd
/// pop r64 (extended): 41 58+rd
fn encode_x86_pop(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    if let Some(reg) = inst.operands[0].get_reg() {
        let mut out = Vec::with_capacity(2);
        if reg >= 8 {
            out.push(0x41); // REX.B
        }
        out.push(0x58 + (reg % 8) as u8);
        Some(out)
    } else {
        None
    }
}

/// mov r64, r64: REX.W + 89 /r  (mod=11, reg=src, rm=dst)
/// mov r64, imm64: REX.W + B8+rd with imm64
/// mov r32, r32: 89 /r (no REX if regs < 8)
/// mov r32, imm32: B8+rd with imm32
fn encode_x86_mov(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }

    let dst_is_reg = inst.operands[0].is_reg();
    let src_is_reg = inst.operands[1].is_reg();
    let src_is_imm = inst.operands[1].is_imm();

    // mov r, r
    if dst_is_reg && src_is_reg {
        let dst = inst.operands[0].get_reg().unwrap();
        let src = inst.operands[1].get_reg().unwrap();

        // Determine if 64-bit or 32-bit based on instruction size
        let is64 = inst_is_64bit(inst);

        let mut out = Vec::with_capacity(3);
        // 0x89 MOV r/m64, r64: reg field = source, r/m field = dest
        // REX.R extends reg field (source), REX.B extends r/m field (dest)
        let w = is64;
        let rx_r = x86_reg_needs_rex_r(src);
        let rx_b = x86_reg_needs_rex_b(dst);
        let need_rex = w || rx_r || rx_b;
        if need_rex {
            let rex = make_rex(w, rx_r, false, rx_b);
            out.push(rex);
        }
        out.push(0x89);
        // 89 /r: mod=11 (register), reg=src, rm=dst
        out.push(make_modrm(0x03, x86_reg_field(src), x86_reg_field(dst)));
        Some(out)
    }
    // mov r, imm
    else if dst_is_reg && src_is_imm {
        let dst = inst.operands[0].get_reg().unwrap();
        let imm = inst.operands[1].get_imm().unwrap();
        let is64 = inst_is_64bit(inst);

        if is64 {
            // REX.W + B8+rd + imm64
            let mut out = Vec::with_capacity(10);
            let rex = make_rex(true, false, false, x86_reg_needs_rex_b(dst));
            out.push(rex);
            out.push(0xB8 + x86_reg_field(dst));
            push_i64_le(&mut out, imm);
            Some(out)
        } else {
            // B8+rd + imm32 (32-bit reg encoding uses same B8+rd but 32-bit imm)
            let mut out = Vec::with_capacity(6);
            if x86_reg_needs_rex_b(dst) {
                out.push(0x41); // REX.B only (no W)
            }
            out.push(0xB8 + x86_reg_field(dst));
            push_i32_le(&mut out, imm as i32);
            Some(out)
        }
    }
    // mov r, [mem] — not yet supported
    else {
        None
    }
}

/// load r64, [r64] or loadzx r32, byte [r64]: 8B or 0F B6
/// Load value from memory at address in src register into dst.
/// size==1: MOVZX r32, byte [mem] (zero-extend byte to 32-bit)
/// size==4: MOV r32, [mem] (32-bit load)
/// size==0: MOV r64, [mem] (64-bit load)
fn encode_x86_load(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;

    let is64 = inst_is_64bit(inst);
    let is_byte = inst.size == 1;

    let mut out = Vec::with_capacity(4);

    if is_byte {
        // MOVZX r32, byte [r64]: 0F B6 /r
        // Zero-extends an 8-bit memory value into a 32-bit register.
        // On x86-64, a 32-bit destination register zero-extends to 64-bit.
        // REX.W is NOT needed; just REX.R/B if the register is extended (8-15).
        let rx_r = x86_reg_needs_rex_r(dst);
        let rx_b = x86_reg_needs_rex_b(src);
        if rx_r || rx_b {
            out.push(make_rex(false, rx_r, false, rx_b));
        }
        out.extend_from_slice(&[0x0F, 0xB6]);
        let rm_field = x86_reg_field(src);
        out.push(make_modrm(0x00, x86_reg_field(dst), rm_field));
        if rm_field == 4 {
            out.push(0x24);
        }
        return Some(out);
    }

    // 0x8B — mov r, r/m (32-bit or 64-bit depending on REX.W)
    let w = is64;
    let rx_r = x86_reg_needs_rex_r(dst);
    let rx_b = x86_reg_needs_rex_b(src);
    let need_rex = w || rx_r || rx_b;
    if need_rex {
        let rex = make_rex(w, rx_r, false, rx_b);
        out.push(rex);
    }
    out.push(0x8B);
    // ModRM: mod=00 (memory [reg]), reg=dst, r/m=src
    let rm_field = x86_reg_field(src);
    out.push(make_modrm(0x00, x86_reg_field(dst), rm_field));
    // When mod=00 and r/m=4, emit SIB byte (base register encoding 4 = rsp/r12).
    if rm_field == 4 {
        out.push(0x24); // SIB: scale=00, index=4(no index), base=4
    }
    Some(out)
}

/// store [r64], r64 or store byte [r64], r8: 89 or 88
/// Store value in val register into memory at address in ptr register.
/// size==1: MOV [mem], r8 (byte store, uses low-byte reg encoding)
/// size==4: MOV [mem], r32 (32-bit store)
/// size==0: MOV [mem], r64 (64-bit store)
fn encode_x86_store(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let ptr = inst.operands[0].get_reg()?;
    let val = inst.operands[1].get_reg()?;

    let is64 = inst_is_64bit(inst);
    let is_byte = inst.size == 1;

    let mut out = Vec::with_capacity(3);

    if is_byte {
        // MOV byte [r64], r8: 88 /r  (mod=00, reg=val, r/m=ptr)
        // Stores the low byte of the source register.
        // For byte stores, the reg field encodes a low-byte register
        // (al=0, cl=1, dl=2, bl=3, spl=4, bpl=5, sil=6, dil=7).
        // Registers 0-3 (al,cl,dl,bl) do not need REX.
        // Registers 4-7 (spl,bpl,sil,dil) need the REX prefix *present*
        // (to distinguish from ah,ch,dh,bh) but DO NOT set REX.R=1 — the
        // low-byte of rdi (dil) is still ModRM.reg=7 with REX.R=0.
        // Registers 8-15 (r8b..r15b) need REX with R=1 to extend the
        // reg field from register N to register N+8.
        // The ModRM encoding for 0x88 is: reg field = val (source),
        // r/m field = ptr (destination). So REX.R extends the val
        // reg field and REX.B extends the ptr r/m field.
        let val_needs_rex_present = val >= 4; // enable low-byte encoding
        let rx_r = val >= 8; // extend reg field for registers 8-15
        let rx_b = x86_reg_needs_rex_b(ptr); // ptr reg in r/m field
        let need_rex = val_needs_rex_present || rx_b;
        if need_rex {
            out.push(make_rex(false, rx_r, false, rx_b));
        }
        out.push(0x88);
        let rm_field = x86_reg_field(ptr);
        out.push(make_modrm(0x00, x86_reg_field(val), rm_field));
        if rm_field == 4 {
            out.push(0x24);
        }
        return Some(out);
    }

    // 0x89 — mov r/m, r (32-bit or 64-bit depending on REX.W)
    let w = is64;
    let rx_r = x86_reg_needs_rex_r(val);
    let rx_b = x86_reg_needs_rex_b(ptr);
    let need_rex = w || rx_r || rx_b;
    if need_rex {
        let rex = make_rex(w, rx_r, false, rx_b);
        out.push(rex);
    }
    out.push(0x89);
    // ModRM: mod=00 (memory [ptr]), reg=val, r/m=ptr
    let rm_field = x86_reg_field(ptr);
    out.push(make_modrm(0x00, x86_reg_field(val), rm_field));
    // When mod=00 and r/m=4, a SIB byte is required (otherwise r/m=4 means rsp).
    if rm_field == 4 {
        out.push(0x24);
    }
    Some(out)
}

/// add r64, r64: REX.W + 01 /r  (mod=11, reg=dst, rm=src, opcode=01 handles "r,r")
/// add r64, imm32: REX.W + 81 /0 id  (mod=11, reg/opcode=0, rm=dst)
/// add r32, imm8: 83 /0 ib
fn encode_x86_add(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }

    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm();
    let src = inst.operands[1].get_reg();
    let is64 = inst_is_64bit(inst);

    if let Some(src_reg) = src {
        // add r, r
        let mut out = Vec::with_capacity(3);
        let w = is64;
        let rx_r = x86_reg_needs_rex_r(dst);
        let rx_b = x86_reg_needs_rex_b(src_reg);
        let need_rex = w || rx_r || rx_b;
        if need_rex {
            let rex = make_rex(w, rx_r, false, rx_b);
            out.push(rex);
        }
        out.push(0x01); // ADD r/m, r (32-bit or 64-bit depending on REX.W)
        out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src_reg)));
        Some(out)
    } else if let Some(imm_val) = imm {
        // add r, imm
        encode_alu_imm(x86_reg_field(dst), dst, imm_val, 0x81, 0x83, 0, is64)
    } else {
        None
    }
}

/// sub r64, r64: REX.W + 29 /r
/// sub r64, imm32: REX.W + 81 /5 id
/// sub r32, imm8: 83 /5 ib
fn encode_x86_sub(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }

    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm();
    let src = inst.operands[1].get_reg();
    let is64 = inst_is_64bit(inst);

    if let Some(src_reg) = src {
        // sub r, r
        let mut out = Vec::with_capacity(3);
        let w = is64;
        let rx_r = x86_reg_needs_rex_r(dst);
        let rx_b = x86_reg_needs_rex_b(src_reg);
        let need_rex = w || rx_r || rx_b;
        if need_rex {
            let rex = make_rex(w, rx_r, false, rx_b);
            out.push(rex);
        }
        out.push(0x29); // SUB r/m, r (32-bit or 64-bit depending on REX.W)
        out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src_reg)));
        Some(out)
    } else if let Some(imm_val) = imm {
        encode_alu_imm(x86_reg_field(dst), dst, imm_val, 0x81, 0x83, 5, is64)
    } else {
        None
    }
}

/// imul r32, r/m32: 0F AF /r   (two-operand form)
fn encode_x86_imul(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(4);
    // IMUL r64, r/m64: REX.W + 0F AF /r
    // reg = dst (operand[0]), r/m = src (operand[1]), result in dst
    let need_rex = is64 || x86_reg_needs_rex_r(dst) || x86_reg_needs_rex_b(src);
    if need_rex {
        out.push(make_rex(
            is64,
            x86_reg_needs_rex_r(dst),
            false,
            x86_reg_needs_rex_b(src),
        ));
    }
    out.push(0x0F);
    out.push(0xAF);
    out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src)));
    Some(out)
}

/// mul r64: REX.W + F7 /4  (mod=11, reg/opcode=4, rm=reg)
fn encode_x86_mul(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xF7);
    out.push(make_modrm(0x03, 4, x86_reg_field(reg)));
    Some(out)
}

/// and r64, r64: REX.W + 21 /r
/// and r64, imm32: REX.W + 81 /4 id
fn encode_x86_and(inst: &MCInst) -> Option<Vec<u8>> {
    encode_binary_reg_imm(inst, 0x21, 4)
}

/// or r64, r64: REX.W + 09 /r
/// or r64, imm32: REX.W + 81 /1 id
fn encode_x86_or(inst: &MCInst) -> Option<Vec<u8>> {
    encode_binary_reg_imm(inst, 0x09, 1)
}

/// xor r64, r64: REX.W + 31 /r
/// xor r64, imm32: REX.W + 81 /6 id
fn encode_x86_xor(inst: &MCInst) -> Option<Vec<u8>> {
    encode_binary_reg_imm(inst, 0x31, 6)
}

/// cmp r, r: REX.W + 39 /r
/// cmp r, imm8: 83 /7 ib
fn encode_x86_cmp(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    // CMP operands: MCInst has [lhs, rhs] — same as Intel CMP r/m, r
    // InstFormat: CMP r/m64, r64 → modRM(reg=r64(second), r/m=r/m64(first))
    // reg field = source (rhs), r/m field = destination (lhs)
    let lhs = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm();
    let rhs = inst.operands[1].get_reg();

    if let Some(rhs_reg) = rhs {
        let is64 = inst_is_64bit(inst);
        let mut out = Vec::with_capacity(3);
        let w = is64;
        // For CMP r/m, r: REX.R extends reg field (rhs), REX.B extends r/m field (lhs)
        let rx_r = x86_reg_needs_rex_r(rhs_reg);
        let rx_b = x86_reg_needs_rex_b(lhs);
        let need_rex = w || rx_r || rx_b;
        if need_rex {
            let rex = make_rex(w, rx_r, false, rx_b);
            out.push(rex);
        }
        out.push(0x39); // CMP r/m, r (reg=rhs, rm=lhs)
        out.push(make_modrm(0x03, x86_reg_field(rhs_reg), x86_reg_field(lhs)));
        Some(out)
    } else if let Some(imm_val) = imm {
        encode_alu_imm(
            x86_reg_field(lhs),
            lhs,
            imm_val,
            0x81,
            0x83,
            7,
            inst_is_64bit(inst),
        )
    } else {
        None
    }
}

/// jmp rel32: E9 cd
/// jmp label: E9 with 0 displacement (placeholder, needs fixup)
fn encode_x86_jmp(inst: &MCInst) -> Option<Vec<u8>> {
    let mut out = Vec::with_capacity(5);
    out.push(0xE9);
    // Compute relative offset if immediate given, otherwise 0 (placeholder)
    if let Some(MCOperand::Imm(offset)) = inst.operands.first() {
        push_i32_le(&mut out, *offset as i32);
    } else {
        push_i32_le(&mut out, 0);
    }
    Some(out)
}

/// call rel32: E8 cd
fn encode_x86_call(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.operands.first() {
        Some(MCOperand::Imm(offset)) => {
            // Direct call: E8 rel32
            let mut out = Vec::with_capacity(5);
            out.push(0xE8);
            push_i32_le(&mut out, *offset as i32);
            Some(out)
        }
        Some(MCOperand::Reg(reg)) => {
            // Indirect call through register: FF /2 reg
            // FF /2 = opcode FF, ModRM(mod=3, reg/opcode=2, rm=reg_field)
            // ModRM = 0b11_010_rmm = 0xD0 | (reg & 7)
            let rm = *reg & 7;
            let modrm = (0xD0u32 | rm) as u8;
            let mut out = Vec::with_capacity(3);
            if *reg >= 8 {
                out.push(0x41); // REX.B prefix
            }
            out.push(0xFF);
            out.push(modrm);
            Some(out)
        }
        _ => {
            // Fallback: E8 00000000
            let mut out = Vec::with_capacity(5);
            out.push(0xE8);
            push_i32_le(&mut out, 0);
            Some(out)
        }
    }
}

/// Jcc rel32: 0F 8x cd (where x encodes the condition)
/// JE: 0F 84, JNE: 0F 85
fn encode_x86_jcc(inst: &MCInst, cond_byte: u8) -> Option<Vec<u8>> {
    let mut out = Vec::with_capacity(6);
    out.push(0x0F);
    out.push(cond_byte);
    if let Some(MCOperand::Imm(offset)) = inst.operands.first() {
        push_i32_le(&mut out, *offset as i32);
    } else {
        push_i32_le(&mut out, 0);
    }
    Some(out)
}

/// inc r64: REX.W + FF /0  (mod=11, reg/opcode=0, rm=reg)
fn encode_x86_inc(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xFF);
    out.push(make_modrm(0x03, 0, x86_reg_field(reg)));
    Some(out)
}

/// dec r64: REX.W + FF /1  (mod=11, reg/opcode=1, rm=reg)
fn encode_x86_dec(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xFF);
    out.push(make_modrm(0x03, 1, x86_reg_field(reg)));
    Some(out)
}

/// lea r64, [mem]: REX.W + 8D /r (placeholder, memory operand not yet supported)
fn encode_x86_lea(inst: &MCInst) -> Option<Vec<u8>> {
    // LEA dst, src
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    if inst.operands[1].is_reg() {
        eprintln!(
            "LEA_REG: ops[0]={:?} ops[1]={:?}",
            inst.operands[0], inst.operands[1]
        );
    }

    if let Some(base_reg) = inst.operands[1].get_reg() {
        // lea r64, [base_reg]
        // Encoding: REX.W + 8D /r  (mod=00, reg=dst, rm=base)
        let mut out = Vec::with_capacity(3);
        let need_rex = is64 || x86_reg_needs_rex_r(dst) || x86_reg_needs_rex_b(base_reg);
        if need_rex {
            out.push(make_rex(
                is64,
                x86_reg_needs_rex_r(dst),
                false,
                x86_reg_needs_rex_b(base_reg),
            ));
        }
        out.push(0x8D);
        out.push(make_modrm(
            0x00,
            x86_reg_field(dst),
            x86_reg_field(base_reg),
        ));
        Some(out)
    } else if inst.operands[1].is_expr() {
        // lea r64, [rip + symbol]
        // Encoding: REX.W + 8D + ModRM(00, dst, 101) + disp32(0 placeholder)
        // rm=101 with mod=00 means RIP-relative addressing.
        let mut out = Vec::with_capacity(7);
        let need_rex = is64 || x86_reg_needs_rex_r(dst);
        if need_rex {
            out.push(make_rex(is64, x86_reg_needs_rex_r(dst), false, false));
        }
        out.push(0x8D);
        // mod=00, reg=dst, rm=101 (RIP-relative)
        out.push(make_modrm(0x00, x86_reg_field(dst), 5));
        // disp32 placeholder (will be patched by relocation)
        out.extend_from_slice(&[0u8; 4]);
        Some(out)
    } else {
        None
    }
}

/// not r64: REX.W + F7 /2
fn encode_x86_not(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xF7);
    out.push(make_modrm(0x03, 2, x86_reg_field(reg)));
    Some(out)
}

/// neg r64: REX.W + F7 /3
fn encode_x86_neg(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xF7);
    out.push(make_modrm(0x03, 3, x86_reg_field(reg)));
    Some(out)
}

/// cmovcc r64, r64: REX.W + 0F 4x + modrm
fn encode_x86_cmovcc(inst: &MCInst, cc_byte: u8) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    // CMOVcc dst, src: 0F 4x /r
    // Intel SDM Vol 2A: CMOVcc r64, r/m64
    //   Op/En: RM  →  Operand 1 (dst): ModRM:r/m (r,w), Operand 2 (src): ModRM:reg (r)
    //   reg field = source, r/m field = destination
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(4);
    let need_rex = is64 || x86_reg_needs_rex_r(src) || x86_reg_needs_rex_b(dst);
    if need_rex {
        out.push(make_rex(
            is64,
            x86_reg_needs_rex_r(src),
            false,
            x86_reg_needs_rex_b(dst),
        ));
    }
    out.push(0x0F);
    out.push(cc_byte);
    // modrm: mod=11, reg=src (read), r/m=dst (read-write)
    out.push(make_modrm(0x03, x86_reg_field(src), x86_reg_field(dst)));
    Some(out)
}

/// shl/shr r64, cl: REX.W + D3 /4 or /5
/// shl/shr r64, imm8: REX.W + C1 /4 or /5 ib
fn encode_x86_shift(inst: &MCInst, reg_opcode_field: u8) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    // Determine shift width from operand size. 32-bit shift: size == 4.
    // 64-bit shift: size >= 8 (REX.W). Use inst_is_64bit() to handle
    // size == 0 consistently with MOV and ALU encoders (they treat
    // size == 0 as 64-bit via the same function).  The instruction
    // selector must set size = 4 for 32-bit shifts and size = 8 for
    // 64-bit shifts.
    let is64 = inst_is_64bit(inst);
    let is_cl = inst.operands[1].get_reg() == Some(1); // RCX=1 is CL

    let mut out = Vec::with_capacity(4);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }

    if is_cl {
        // Shift by CL
        out.push(0xD3);
        out.push(make_modrm(0x03, reg_opcode_field, x86_reg_field(reg)));
    } else if let Some(imm_val) = inst.operands[1].get_imm() {
        // Shift by immediate
        if imm_val == 1 {
            // Shift by 1: D1 /4 or /5
            out.push(0xD1);
        } else {
            // Shift by imm8: C1 /4 or /5
            out.push(0xC1);
        }
        out.push(make_modrm(0x03, reg_opcode_field, x86_reg_field(reg)));
        if imm_val != 1 {
            out.push(imm_val as u8);
        }
    } else {
        return None;
    }
    Some(out)
}

/// div r64: REX.W + F7 /6 (mod=11, reg/opcode=6, rm=reg)
fn encode_x86_div(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xF7);
    out.push(make_modrm(0x03, 6, x86_reg_field(reg)));
    Some(out)
}

fn encode_x86_idiv(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let reg = inst.operands[0].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(3);
    let need_rex = is64 || x86_reg_needs_rex_b(reg);
    if need_rex {
        out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(reg)));
    }
    out.push(0xF7);
    out.push(make_modrm(0x03, 7, x86_reg_field(reg)));
    Some(out)
}

fn encode_x86_cdq(_inst: &MCInst) -> Option<Vec<u8>> {
    // CDQ: 99 (sign-extend eax into edx:eax, 32-bit)
    Some(vec![0x99])
}

fn encode_x86_cqo(_inst: &MCInst) -> Option<Vec<u8>> {
    // CQO: 48 99 (REX.W + 99, sign-extend rax into rdx:rax, 64-bit)
    Some(vec![0x48, 0x99])
}

// --- Helper encoders ---

/// Encode ALU instruction with immediate: op r/m, imm
///
/// Uses 0x81 opcode for imm32 and 0x83 for imm8 when possible.
/// reg_opcode_field is the /digit encoding (0=ADD, 5=SUB, 7=CMP, etc.)
fn encode_alu_imm(
    rm_field: u8,
    rm_reg_id: u32,
    imm: i64,
    op_imm32: u8,
    op_imm8: u8,
    reg_opcode_field: u8,
    is64: bool,
) -> Option<Vec<u8>> {
    // Use imm8 encoding if value fits in signed byte
    if (-128..=127).contains(&imm) {
        let mut out = Vec::with_capacity(4);
        let need_rex = is64 || x86_reg_needs_rex_b(rm_reg_id);
        if need_rex {
            out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(rm_reg_id)));
        }
        out.push(op_imm8);
        out.push(make_modrm(0x03, reg_opcode_field, rm_field));
        out.push(imm as u8);
        Some(out)
    } else {
        let mut out = Vec::with_capacity(7);
        let need_rex = is64 || x86_reg_needs_rex_b(rm_reg_id);
        if need_rex {
            out.push(make_rex(is64, false, false, x86_reg_needs_rex_b(rm_reg_id)));
        }
        out.push(op_imm32);
        out.push(make_modrm(0x03, reg_opcode_field, rm_field));
        push_i32_le(&mut out, imm as i32);
        Some(out)
    }
}

/// Generic binary op: reg, reg or reg, imm
fn encode_binary_reg_imm(inst: &MCInst, op_reg_reg: u8, reg_opcode_field: u8) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm();
    let src = inst.operands[1].get_reg();

    if let Some(src_reg) = src {
        // reg, reg
        let is64 = inst_is_64bit(inst);
        let mut out = Vec::with_capacity(3);
        let w = is64;
        let rx_r = x86_reg_needs_rex_r(dst);
        let rx_b = x86_reg_needs_rex_b(src_reg);
        let need_rex = w || rx_r || rx_b;
        if need_rex {
            let rex = make_rex(w, rx_r, false, rx_b);
            out.push(rex);
        }
        out.push(op_reg_reg);
        out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src_reg)));
        Some(out)
    } else if let Some(imm_val) = imm {
        encode_alu_imm(
            x86_reg_field(dst),
            dst,
            imm_val,
            0x81,
            0x83,
            reg_opcode_field,
            inst_is_64bit(inst),
        )
    } else {
        None
    }
}

/// movsxd r64, r32: REX.W + 63 /r
///   Sign-extends a 32-bit register to 64 bits.
fn encode_x86_movsxd(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;

    // MOVSXD r64, r/m32: REX.W + 63 /r
    // mod=11 (register), reg=dst, rm=src
    let mut out = Vec::with_capacity(3);
    let rex = make_rex(
        true, // W=1 (64-bit operand size)
        x86_reg_needs_rex_r(dst),
        false,
        x86_reg_needs_rex_b(src),
    );
    out.push(rex);
    out.push(0x63);
    out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src)));
    Some(out)
}

/// movsx r32/r64, r8: 0F BE /r
///   Sign-extends an 8-bit register to 32 or 64 bits.
///   size==4: MOVSX r32, r8 (no REX.W; 32-bit result zero-extends to 64-bit on x86-64)
///   size==0: MOVSX r64, r8 (REX.W for 64-bit destination)
fn encode_x86_movsx(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;
    let is64 = inst_is_64bit(inst);
    let mut out = Vec::with_capacity(4);
    // MOVSX r32/r64, r8: 0F BE /r
    // mod=11 (register), reg=dst, rm=src
    // For 64-bit destination, add REX.W.
    // Registers 4-7 (SPL/BPL/SIL/DIL) need REX prefix present (without W).
    let src_needs_rex_low = src >= 4 && src < 8; // SPL/BPL/SIL/DIL
    let rex_r = x86_reg_needs_rex_r(dst);
    let rex_b = x86_reg_needs_rex_b(src);
    let need_rex = is64 || src_needs_rex_low || rex_r || rex_b;
    if need_rex {
        out.push(make_rex(is64, rex_r, false, rex_b));
    }
    out.extend_from_slice(&[0x0F, 0xBE]);
    out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src)));
    Some(out)
}

/// movzx r32, r8: 0F B6 /r
///   Zero-extends an 8-bit register to 32 bits.
fn encode_x86_movzx(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;

    let mut out = Vec::with_capacity(4);

    // MOVZX r32, r8 uses 0x0F 0xB6 with ModRM:
    // mod=11 (register), reg=dst, rm=src
    // No REX.W needed — writing to 32-bit reg zero-extends to 64-bit in x86-64.
    //
    // NOTE: In 64-bit mode, registers 4-7 (rsp/rbp/rsi/rdi) require a REX prefix
    // to access their low 8-bit form (SPL/BPL/SIL/DIL). Without REX, the encoding
    // maps to AH/CH/DH/BH instead.
    let rex_r = x86_reg_needs_rex_r(dst);
    let rex_b = x86_reg_needs_rex_b(src);
    // Also need REX for regs 4-7 to get low-byte encoding (SPL/BPL/SIL/DIL)
    // instead of high-byte (AH/CH/DH/BH).
    let needs_rex_for_low_byte = (src >= 4 && src < 8) || (dst >= 4 && dst < 8);
    let needs_rex = rex_r || rex_b || needs_rex_for_low_byte;
    if needs_rex {
        out.push(make_rex(false, rex_r, false, rex_b));
    }
    out.extend_from_slice(&[0x0F, 0xB6]);
    out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src)));
    Some(out)
}

/// setcc r8: 0F 0x9<cc> /0  (mod=11, rm=dst)
///   Sets the 8-bit register to 1 if the condition is true, 0 otherwise.
fn encode_x86_setcc(inst: &MCInst, opcode2: u8) -> Option<Vec<u8>> {
    if inst.operands.len() != 1 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;

    let mut out = Vec::with_capacity(3);

    // In 64-bit mode, registers 4-7 (rsp/rbp/rsi/rdi) require a REX prefix
    // to access their low 8-bit form (SPL/BPL/SIL/DIL). Without REX, the encoding
    // maps to AH/CH/DH/BH instead.
    // For regs 8+, we also need REX.B.
    if x86_reg_needs_rex_b(dst) {
        out.push(0x41); // REX.B
    } else if dst >= 4 && dst < 8 {
        out.push(0x40); // REX (no bits set, but enables low 8-bit encoding)
    }
    out.extend_from_slice(&[0x0F, opcode2]);
    out.push(make_modrm(0x03, 0, x86_reg_field(dst)));
    Some(out)
}

// ============================================================================
// SSE/SSE2 Scalar FP Instruction Encoders
// ============================================================================

/// Encode an SSE binary operation with a mandatory prefix and 0x0F escape.
/// prefix: 0xF3 (SSE scalar single), 0xF2 (SSE scalar double),
///         0x66 (SSE2 packed double), 0x00 (no prefix, e.g. UCOMISS, XORPS)
/// opcode2: the 0F-prefixed opcode byte (e.g. 0x58 for ADDSS/ADDSD)
///
/// Encode an SSE binary operation (ADDSS, ADDSD, SUBSS, SUBSD, MULSS, MULSD,
/// DIVSS, DIVSD, UCOMISS, UCOMISD, MOVSS, MOVSD, XORPS, XORPD).
///
/// ISel convention: operands[0] = source, operands[1] = dest
/// Actual encoding (verified against objdump): ModRM.reg = dest, ModRM.r/m = src
///   i.e. the destination XMM goes in the reg field, source XMM in the r/m field
fn encode_x86_sse_binary(inst: &MCInst, opcode2: u8, prefix: u8) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let src = inst.operands[0].get_reg()?;
    let dst = inst.operands[1].get_reg()?;

    let mut out = Vec::with_capacity(4);
    if prefix != 0x00 {
        out.push(prefix);
    }
    let src_idx = src.wrapping_sub(64);
    let dst_idx = dst.wrapping_sub(64);
    // REX.R extends reg field (dest), REX.B extends r/m field (src)
    let need_rex_r = dst_idx >= 8;
    let need_rex_b = src_idx >= 8;
    if need_rex_r || need_rex_b {
        out.push(make_rex(false, need_rex_r, false, need_rex_b));
    }
    out.push(0x0F);
    out.push(opcode2);
    // Encoding: reg=dest, r/m=src (verified against objdump)
    let reg_field = (dst_idx & 0x07) as u8;
    let rm_field = (src_idx & 0x07) as u8;
    out.push(make_modrm(0x03, reg_field, rm_field));
    Some(out)
}

/// Encode CVTSI2SS/CVTSI2SD — convert integer register to XMM register.
/// opcode2: 0x2A for CVTSI2SS/CVTSI2SD
/// is_single: true for CVTSI2SS (prefix F3), false for CVTSI2SD (prefix F2)
/// Encoding: F3/F2 REX.W 0F 2A /r
///   ModRM: mod=11, reg=integer_src, rm=xmm_dst
fn encode_x86_sse_cvt_i2f(inst: &MCInst, opcode2: u8, is_single: bool) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let xmm_dst = inst.operands[0].get_reg()?;
    let int_src = inst.operands[1].get_reg()?;

    let mut out = Vec::with_capacity(5);
    // Mandatory prefix
    out.push(if is_single { 0xF3 } else { 0xF2 });
    // REX.W + REX.R (extends int reg) + REX.B (extends xmm reg)
    let need_w = true; // REX.W for 64-bit operand
    let need_rex_r = x86_reg_needs_rex_r(int_src);
    let dst_idx = xmm_dst.wrapping_sub(64);
    let need_rex_b = dst_idx >= 8;
    out.push(make_rex(need_w, need_rex_r, false, need_rex_b));
    out.push(0x0F);
    out.push(opcode2);
    // ModRM: mod=11, reg=int_src (low 3 bits), rm=xmm_dst (low 3 bits)
    let reg_field = x86_reg_field(int_src);
    let rm_field = (dst_idx & 0x07) as u8;
    out.push(make_modrm(0x03, reg_field, rm_field));
    Some(out)
}

/// Encode CVTTSS2SI/CVTTSD2SI — convert XMM register to integer register (truncate).
/// opcode2: 0x2C for CVTTSS2SI/CVTTSD2SI
/// is_single: true for CVTTSS2SI (prefix F3), false for CVTTSD2SI (prefix F2)
/// Encoding: F3/F2 REX.W 0F 2C /r
///   ModRM: mod=11, reg=xmm_src, rm=int_dst
fn encode_x86_sse_cvt_f2i(inst: &MCInst, opcode2: u8, is_single: bool) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let int_dst = inst.operands[0].get_reg()?;
    let xmm_src = inst.operands[1].get_reg()?;

    let mut out = Vec::with_capacity(5);
    // Mandatory prefix
    out.push(if is_single { 0xF3 } else { 0xF2 });
    // REX.W + REX.R (extends xmm reg) + REX.B (extends int reg)
    let need_w = true; // REX.W for 64-bit operand
    let src_idx = xmm_src.wrapping_sub(64);
    let need_rex_r = src_idx >= 8;
    let need_rex_b = x86_reg_needs_rex_b(int_dst);
    out.push(make_rex(need_w, need_rex_r, false, need_rex_b));
    out.push(0x0F);
    out.push(opcode2);
    // ModRM: mod=11, reg=xmm_src, rm=int_dst
    let reg_field = (src_idx & 0x07) as u8;
    let rm_field = x86_reg_field(int_dst);
    out.push(make_modrm(0x03, reg_field, rm_field));
    Some(out)
}

/// Encode MOVD/MOVQ — move between GPR and XMM register.
/// GPR→XMM direction (opcode 0x6E): operands[0]=GPR(src), operands[1]=XMM(dst)
///   reg=GPR, r/m=XMM
/// XMM→GPR direction (opcode 0x7E): operands[0]=XMM(src), operands[1]=GPR(dst)
///   reg=XMM, r/m=GPR
fn encode_x86_movd(inst: &MCInst, is_64bit: bool, from_xmm: bool) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let mut out = Vec::with_capacity(4);
    // 0x66 prefix (SSE2)
    out.push(0x66);
    if from_xmm {
        // XMM→GPR: opcode 0x7E, reg=XMM, r/m=GPR
        // operands[0]=XMM(src), operands[1]=GPR(dst)
        let xmm_src = inst.operands[0].get_reg()?;
        let gpr_dst = inst.operands[1].get_reg()?;
        let xmm_idx = xmm_src.wrapping_sub(64);
        let need_w = is_64bit;
        let need_rex_r = xmm_idx >= 8;
        let need_rex_b = x86_reg_needs_rex_b(gpr_dst);
        if need_w || need_rex_r || need_rex_b {
            out.push(make_rex(need_w, need_rex_r, false, need_rex_b));
        }
        out.extend_from_slice(&[0x0F, 0x7E]);
        out.push(make_modrm(
            0x03,
            (xmm_idx & 0x07) as u8,
            x86_reg_field(gpr_dst),
        ));
    } else {
        // GPR→XMM: opcode 0x6E, reg=XMM(dest), r/m=GPR(src)
        // Verified against objdump: `movd %r9d,%xmm7` → reg=7(xmm7), r/m=9(r9d)
        let gpr_reg = inst.operands[0].get_reg()?;
        let xmm_reg = inst.operands[1].get_reg()?;
        let xmm_idx = xmm_reg.wrapping_sub(64);
        let need_w = is_64bit;
        // REX.R extends reg field (XMM dest), REX.B extends r/m field (GPR src)
        let need_rex_r = xmm_idx >= 8;
        let need_rex_b = x86_reg_needs_rex_b(gpr_reg);
        if need_w || need_rex_r || need_rex_b {
            out.push(make_rex(need_w, need_rex_r, false, need_rex_b));
        }
        out.extend_from_slice(&[0x0F, 0x6E]);
        out.push(make_modrm(
            0x03,
            (xmm_idx & 0x07) as u8, // reg = XMM dest
            x86_reg_field(gpr_reg), // r/m = GPR src
        ));
    }
    Some(out)
}

/// Encode memory-addressed MOVSS/MOVSD (for float LOAD/STORE).
/// For LOAD (opcode2=0x10): operands[0]=XMM(dest), operands[1]=GPR(ptr)
///   F3/F2 0F 10 /r  mod=00, reg=XMM, r/m=ptr
/// For STORE (opcode2=0x11): operands[0]=XMM(src), operands[1]=GPR(ptr)
///   F3/F2 0F 11 /r  mod=00, reg=XMM, r/m=ptr
fn encode_x86_sse_mem(inst: &MCInst, opcode2: u8, prefix: u8, is_store: bool) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let xmm_reg = inst.operands[0].get_reg()?;
    let ptr_reg = inst.operands[1].get_reg()?;
    // ptr_reg must be a GPR (0-15), xmm_reg must be XMM (64-79)
    let xmm_idx = xmm_reg.wrapping_sub(64);

    let mut out = Vec::with_capacity(4);
    out.push(prefix); // F3 (float) or F2 (double)
                      // REX.R extends reg field (XMM), REX.B extends r/m field (GPR ptr)
    let need_rex_r = xmm_idx >= 8;
    let need_rex_b = x86_reg_needs_rex_b(ptr_reg);
    if need_rex_r || need_rex_b {
        out.push(make_rex(false, need_rex_r, false, need_rex_b));
    }
    out.extend_from_slice(&[0x0F, opcode2]);
    // mod=00 (memory [ptr]), reg=XMM, r/m=ptr
    out.push(make_modrm(
        0x00,
        (xmm_idx & 0x07) as u8,
        x86_reg_field(ptr_reg),
    ));
    Some(out)
}

// ============================================================================
// ARM/AArch64 Instruction Encoder
// ============================================================================

/// Encode an AArch64 instruction from an MCInst.
///
/// AArch64 uses fixed 32-bit instructions. Key formats:
///   add/sub (immediate): 1|0|0|01011|sh|imm12|Rn|Rd
///   add/sub (register):  1|0|0|01011|shift|0|Rm|6|Rn|Rd
pub fn encode_aarch64(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.opcode {
        1 => encode_aarch64_mov(inst),    // MOV
        2 => encode_aarch64_add(inst),    // ADD
        3 => encode_aarch64_sub(inst),    // SUB
        4 => encode_aarch64_mul(inst),    // MUL (actually MADD with zero accumulator)
        5 => encode_aarch64_and(inst),    // AND
        6 => encode_aarch64_orr(inst),    // ORR
        7 => encode_aarch64_eor(inst),    // EOR
        0 => Some(encode_aarch64_nop()),  // NOP
        17 => Some(encode_aarch64_ret()), // RET
        15 => encode_aarch64_b(inst),     // B
        16 => encode_aarch64_bl(inst),    // BL
        _ => None,
    }
}

fn encode_aarch64_nop() -> Vec<u8> {
    0xD503201Fu32.to_le_bytes().to_vec() // NOP = HINT #0
}

fn encode_aarch64_ret() -> Vec<u8> {
    0xD65F03C0u32.to_le_bytes().to_vec() // RET X30
}

/// MOVZ: 1|10|100101|00|imm16|Rd
fn encode_aarch64_mov(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm().unwrap_or(0);

    let mut insn: u32 = 0xD2800000; // MOVZ base
    insn |= dst & 0x1F;
    insn |= ((imm as u32) & 0xFFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

/// ADD (immediate): 1|0|0|10001|0|shift|imm12|Rn|Rd
fn encode_aarch64_add(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;
    let imm = inst.operands[2].get_imm().unwrap_or(0);

    let mut insn: u32 = 0x91000000; // ADD (immediate) base
    insn |= dst & 0x1F;
    insn |= (src & 0x1F) << 5;
    insn |= ((imm as u32) & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

/// SUB (immediate): 1|1|0|10001|0|shift|imm12|Rn|Rd
fn encode_aarch64_sub(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;
    let imm = inst.operands[2].get_imm().unwrap_or(0);

    let mut insn: u32 = 0xD1000000; // SUB (immediate) base
    insn |= dst & 0x1F;
    insn |= (src & 0x1F) << 5;
    insn |= ((imm as u32) & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

/// MUL: MADD Xd, Xn, Xm, XZR  → 10011011|000|Rm|0|00000|Rn|Rd
fn encode_aarch64_mul(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn: u32 = 0x9B007C00; // MADD with XZR as accumulator
    insn |= dst & 0x1F;
    insn |= (src1 & 0x1F) << 5;
    insn |= (src2 & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

/// AND: 1|00|01010|00|Rm|6|Rn|Rd
fn encode_aarch64_and(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn: u32 = 0x8A000000; // AND (shifted register) base
    insn |= dst & 0x1F;
    insn |= (src1 & 0x1F) << 5;
    insn |= (src2 & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

/// ORR: 1|01|01010|00|Rm|6|Rn|Rd
fn encode_aarch64_orr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn: u32 = 0xAA000000; // ORR (shifted register) base
    insn |= dst & 0x1F;
    insn |= (src1 & 0x1F) << 5;
    insn |= (src2 & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

/// EOR: 1|10|01010|00|Rm|6|Rn|Rd
fn encode_aarch64_eor(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn: u32 = 0xCA000000; // EOR (shifted register) base
    insn |= dst & 0x1F;
    insn |= (src1 & 0x1F) << 5;
    insn |= (src2 & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

/// B (unconditional branch): 0|00101|imm26
fn encode_aarch64_b(inst: &MCInst) -> Option<Vec<u8>> {
    let offset = inst.operands.first().and_then(|o| o.get_imm()).unwrap_or(0);
    let imm26 = (offset as u32) & 0x03FFFFFF;
    let insn: u32 = 0x14000000 | imm26;
    Some(insn.to_le_bytes().to_vec())
}

/// BL (branch with link): 1|00101|imm26
fn encode_aarch64_bl(inst: &MCInst) -> Option<Vec<u8>> {
    let offset = inst.operands.first().and_then(|o| o.get_imm()).unwrap_or(0);
    let imm26 = (offset as u32) & 0x03FFFFFF;
    let insn: u32 = 0x94000000 | imm26;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// ARM32 (A32) Instruction Encoder
// ============================================================================

/// Encode an ARM32 instruction from an MCInst.
/// ARM32 uses fixed 32-bit instructions with conditional execution.
pub fn encode_arm32(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.opcode {
        0 => encode_arm32_nop(inst),  // NOP
        1 => encode_arm32_mov(inst),  // MOV
        2 => encode_arm32_movw(inst), // MOVW
        3 => encode_arm32_movt(inst), // MOVT
        4 => encode_arm32_add(inst),  // ADD
        5 => encode_arm32_sub(inst),  // SUB
        6 => encode_arm32_mul(inst),  // MUL
        7 => encode_arm32_and(inst),  // AND
        8 => encode_arm32_orr(inst),  // ORR
        9 => encode_arm32_eor(inst),  // EOR
        _ => None,
    }
}

/// ARM NOP: 0xE320F000 (MOV r0, r0 with AL condition)
fn encode_arm32_nop(_inst: &MCInst) -> Option<Vec<u8>> {
    Some(0xE320F000u32.to_le_bytes().to_vec())
}

/// ARM MOV (register): cond|00|0|1101|0|0000|Rd|0000|0000|Rm
/// Always unconditional (AL=1110)
fn encode_arm32_mov(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src = inst.operands[1].get_reg()?;

    // MOV Rd, Rm  →  E1A00000 + (Rd<<12) + Rm
    let mut insn: u32 = 0xE1A00000;
    insn |= (dst & 0xF) << 12;
    insn |= src & 0xF;
    Some(insn.to_le_bytes().to_vec())
}

/// ARM MOVW: cond|0011|0000|imm4|Rd|imm12
fn encode_arm32_movw(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xE3000000; // MOVW base
    insn |= (dst & 0xF) << 12;
    insn |= ((imm >> 12) & 0xF) << 16; // imm4 (bits 19:16)
    insn |= imm & 0xFFF; // imm12
    Some(insn.to_le_bytes().to_vec())
}

/// ARM MOVT: cond|0011|0100|imm4|Rd|imm12
fn encode_arm32_movt(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let imm = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xE3400000; // MOVT base
    insn |= (dst & 0xF) << 12;
    insn |= ((imm >> 12) & 0xF) << 16;
    insn |= imm & 0xFFF;
    Some(insn.to_le_bytes().to_vec())
}

/// ARM ADD: cond|00|0|0100|1|Rn|Rd|0000|0000|Rm
fn encode_arm32_add(inst: &MCInst) -> Option<Vec<u8>> {
    encode_arm32_alu_reg(inst, 0xE0800000)
}

/// ARM SUB: cond|00|0|0010|1|Rn|Rd|0000|0000|Rm
fn encode_arm32_sub(inst: &MCInst) -> Option<Vec<u8>> {
    encode_arm32_alu_reg(inst, 0xE0400000)
}

/// ARM MUL: cond|0000|0001|S|Rd|0000|0001|Rm
fn encode_arm32_mul(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn: u32 = 0xE0000090; // MUL base
    insn |= (dst & 0xF) << 16;
    insn |= (src1 & 0xF) << 8;
    insn |= src2 & 0xF;
    Some(insn.to_le_bytes().to_vec())
}

/// ARM AND: cond|00|0|0000|1|Rn|Rd|0000|0000|Rm
fn encode_arm32_and(inst: &MCInst) -> Option<Vec<u8>> {
    encode_arm32_alu_reg(inst, 0xE0000000)
}

/// ARM ORR: cond|00|0|1100|1|Rn|Rd|0000|0000|Rm
fn encode_arm32_orr(inst: &MCInst) -> Option<Vec<u8>> {
    encode_arm32_alu_reg(inst, 0xE1800000)
}

/// ARM EOR: cond|00|0|0001|1|Rn|Rd|0000|0000|Rm
fn encode_arm32_eor(inst: &MCInst) -> Option<Vec<u8>> {
    encode_arm32_alu_reg(inst, 0xE0200000)
}

/// ARM ALU register operation helper.
fn encode_arm32_alu_reg(inst: &MCInst, base_insn: u32) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let dst = inst.operands[0].get_reg()?;
    let src1 = inst.operands[1].get_reg()?;
    let src2 = inst.operands[2].get_reg()?;

    let mut insn = base_insn;
    insn |= (dst & 0xF) << 12;
    insn |= (src1 & 0xF) << 16;
    insn |= src2 & 0xF;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// MCAssembler — Section-based Assembly Framework
// ============================================================================

/// A fixup records a relocation that must be applied to a fragment.
#[derive(Debug, Clone)]
pub struct MCFixup {
    /// Offset within the fragment where the fixup applies
    pub offset: usize,
    /// The kind of fixup (target-specific)
    pub kind: FixupKind,
    /// Symbol or label reference
    pub symbol: Option<String>,
    /// Optional addend
    pub value: i64,
}

/// Kinds of fixups.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum FixupKind {
    /// PC-relative 32-bit
    Rel32,
    /// PC-relative 8-bit (short jump)
    Rel8,
    /// Absolute 64-bit
    Abs64,
    /// Absolute 32-bit
    Abs32,
}

/// A fragment of assembled bytes within a section.
#[derive(Debug, Clone)]
pub struct MCFragment {
    /// The raw bytes of this fragment (may contain placeholder zeros for fixups)
    pub data: Vec<u8>,
    /// Whether this fragment is an instruction
    pub is_instruction: bool,
    /// Pending fixups for this fragment
    pub fixups: Vec<MCFixup>,
    /// Alignment requirement (power of 2)
    pub alignment: u8,
}

impl MCFragment {
    pub fn new_instruction(data: Vec<u8>) -> Self {
        Self {
            data,
            is_instruction: true,
            fixups: Vec::new(),
            alignment: 1,
        }
    }

    pub fn new_data(data: Vec<u8>) -> Self {
        Self {
            data,
            is_instruction: false,
            fixups: Vec::new(),
            alignment: 1,
        }
    }

    pub fn add_fixup(&mut self, fixup: MCFixup) {
        self.fixups.push(fixup);
    }
}

/// A section in the assembler output.
#[derive(Debug, Clone)]
pub struct MCSection {
    pub name: String,
    pub fragments: Vec<MCFragment>,
    /// Section type (text, data, etc.)
    pub section_type: SectionType,
}

#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SectionType {
    Text,
    Data,
    Rodata,
    Bss,
}

impl MCSection {
    pub fn new(name: &str, sec_type: SectionType) -> Self {
        Self {
            name: name.to_string(),
            fragments: Vec::new(),
            section_type: sec_type,
        }
    }

    pub fn add_fragment(&mut self, frag: MCFragment) {
        self.fragments.push(frag);
    }
}

/// The MC Assembler manages sections, fragments, and fixups.
pub struct MCAssembler {
    pub sections: Vec<MCSection>,
    pub target_triple: String,
    /// Symbol table: label name → (section_index, fragment_index, offset)
    pub symbols: Vec<(String, usize, usize, usize)>,
}

impl MCAssembler {
    pub fn new(triple: &str) -> Self {
        Self {
            sections: Vec::new(),
            target_triple: triple.to_string(),
            symbols: Vec::new(),
        }
    }

    /// Add a section if not already present.
    pub fn get_or_create_section(&mut self, name: &str, sec_type: SectionType) -> usize {
        if let Some(idx) = self.sections.iter().position(|s| s.name == name) {
            return idx;
        }
        self.sections.push(MCSection::new(name, sec_type));
        self.sections.len() - 1
    }

    /// Emit an encoded instruction into the current text section.
    pub fn emit_instruction(&mut self, bytes: Vec<u8>) {
        let sec_idx = self.get_or_create_section(".text", SectionType::Text);
        self.sections[sec_idx].add_fragment(MCFragment::new_instruction(bytes));
    }

    /// Emit raw data bytes.
    pub fn emit_data(&mut self, bytes: Vec<u8>, section: &str) {
        let sec_idx = self.get_or_create_section(section, SectionType::Data);
        self.sections[sec_idx].add_fragment(MCFragment::new_data(bytes));
    }

    /// Define a symbol/label at the current position.
    pub fn define_symbol(&mut self, name: &str, sec_idx: usize, frag_idx: usize, offset: usize) {
        self.symbols
            .push((name.to_string(), sec_idx, frag_idx, offset));
    }

    /// Compute the total size of all fragments in a section.
    pub fn section_size(&self, sec_idx: usize) -> usize {
        self.sections[sec_idx]
            .fragments
            .iter()
            .map(|f| f.data.len())
            .sum()
    }

    /// Flatten a section into a contiguous byte vector.
    pub fn flatten_section(&self, sec_idx: usize) -> Vec<u8> {
        let mut out = Vec::new();
        for frag in &self.sections[sec_idx].fragments {
            out.extend_from_slice(&frag.data);
        }
        out
    }

    /// Flatten all sections into a contiguous byte vector.
    /// Returns (total_bytes, section_offsets) where offsets maps section name → byte offset.
    pub fn flatten_all(&self) -> (Vec<u8>, Vec<(String, usize, usize)>) {
        let mut out = Vec::new();
        let mut offsets = Vec::new();
        for sec in &self.sections {
            let start = out.len();
            for frag in &sec.fragments {
                out.extend_from_slice(&frag.data);
            }
            let end = out.len();
            offsets.push((sec.name.clone(), start, end - start));
        }
        (out, offsets)
    }
}

impl Default for MCAssembler {
    fn default() -> Self {
        Self::new("x86_64-unknown-linux-gnu")
    }
}

// ============================================================================
// AArch64 Encoding Helpers
// ============================================================================

/// Encode an AArch64 register to its 5-bit encoding field.
fn encode_a64_reg(reg: u32) -> u32 {
    reg & 0x1F
}

/// Encode a signed immediate with range checking for the given bit width.
fn encode_a64_imm_signed(value: i64, bits: u32) -> Option<u32> {
    let min = -(1i64 << (bits - 1));
    let max = (1i64 << (bits - 1)) - 1;
    if value < min || value > max {
        return None;
    }
    let mask = (1u64 << bits) - 1;
    Some((value as u64 & mask) as u32)
}

/// Encode an unsigned immediate with range checking.
fn encode_a64_imm_unsigned(value: u64, bits: u32) -> Option<u32> {
    let max = (1u64 << bits) - 1;
    if value > max {
        return None;
    }
    Some(value as u32)
}

/// Check if a 64-bit value can be encoded as an AArch64 logical immediate.
/// Returns (N, immr, imms) or None.
fn encode_a64_logical_imm(value: u64, size: u32) -> Option<(u32, u32, u32)> {
    if value == 0 {
        return Some((0, 0, 0));
    }
    if value == u64::MAX {
        if size == 64 {
            return Some((1, 0, 63));
        } else {
            return Some((0, 0, 31));
        }
    }
    let effective_value = if size == 32 {
        value & 0xFFFFFFFF
    } else {
        value
    };
    let trailing_ones = effective_value.trailing_zeros();
    let total_ones = effective_value.count_ones();
    if total_ones == 0 {
        return Some((0, 0, 0));
    }
    let rotated = if trailing_ones > 0 {
        (effective_value >> trailing_ones) | (effective_value << (64 - trailing_ones))
    } else {
        effective_value
    };
    let ones_end = match size {
        32 => 32u32.saturating_sub(rotated.trailing_zeros()),
        _ => 64u32.saturating_sub(rotated.trailing_zeros()),
    };
    let immr = trailing_ones as u32;
    let imms = (ones_end - 1) as u32;
    let n = if size == 64 { 1 } else { 0 };
    Some((n, immr, imms))
}

/// Decode a 13-bit AArch64 immediate (1 + 12-bit shifted) for ADD/SUB.
fn encode_a64_addsub_imm(value: u64) -> Option<(u32, u32)> {
    if value <= 0xFFF {
        return Some((0, value as u32)); // no shift
    }
    if value & 0xFFF == 0 && (value >> 12) <= 0xFFF {
        return Some((1, (value >> 12) as u32)); // LSL #12
    }
    None
}

// ============================================================================
// AArch64 Load/Store Instructions
// ============================================================================

fn encode_aarch64_ldr(inst: &MCInst, size: u32) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = match size {
        0 => 0xB9400000, // LDR Wt, [Xn, #pimm]
        1 => 0xF9400000, // LDR Xt, [Xn, #pimm]
        2 => 0x3D400000, // LDR Qt, [Xn, #pimm] (SIMD 128-bit)
        _ => 0xF9400000,
    };
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    let scaled_offset = match size {
        0 => (offset / 4) & 0xFFF,
        2 => (offset / 16) & 0xFFF,
        _ => (offset / 8) & 0xFFF,
    };
    insn |= scaled_offset << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_str(inst: &MCInst, size: u32) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = match size {
        0 => 0xB9000000, // STR Wt, [Xn, #pimm]
        1 => 0xF9000000, // STR Xt, [Xn, #pimm]
        2 => 0x3D000000, // STR Qt, [Xn, #pimm] (SIMD 128-bit)
        _ => 0xF9000000,
    };
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    let scaled_offset = match size {
        0 => (offset / 4) & 0xFFF,
        2 => (offset / 16) & 0xFFF,
        _ => (offset / 8) & 0xFFF,
    };
    insn |= scaled_offset << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ldp(inst: &MCInst, size: u32) -> Option<Vec<u8>> {
    if inst.operands.len() < 4 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rt2 = encode_a64_reg(inst.operands[1].get_reg()?);
    let rn = encode_a64_reg(inst.operands[2].get_reg()?);
    let offset = inst.operands[3].get_imm().unwrap_or(0) as i32;

    let mut insn: u32 = match size {
        0 => 0x29400000, // LDP Wt1, Wt2, [Xn, #imm7]
        1 => 0xA9400000, // LDP Xt1, Xt2, [Xn, #imm7]
        2 => 0x2D400000, // LDP St1, St2, [Xn, #imm7] (SIMD 32-bit)
        3 => 0x6D400000, // LDP Dt1, Dt2, [Xn, #imm7] (SIMD 64-bit)
        _ => 0xA9400000,
    };
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rt2 & 0x1F) << 10;
    let scaled_offset = match size {
        0 => (offset / 4) as u32 & 0x7F,
        2 => (offset / 4) as u32 & 0x7F,
        3 => (offset / 8) as u32 & 0x7F,
        _ => (offset / 8) as u32 & 0x7F,
    };
    insn |= scaled_offset << 15;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_stp(inst: &MCInst, size: u32) -> Option<Vec<u8>> {
    if inst.operands.len() < 4 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rt2 = encode_a64_reg(inst.operands[1].get_reg()?);
    let rn = encode_a64_reg(inst.operands[2].get_reg()?);
    let offset = inst.operands[3].get_imm().unwrap_or(0) as i32;

    let mut insn: u32 = match size {
        0 => 0x29000000, // STP Wt1, Wt2, [Xn, #imm7]
        1 => 0xA9000000, // STP Xt1, Xt2, [Xn, #imm7]
        2 => 0x2D000000, // STP St1, St2, [Xn, #imm7]
        3 => 0x6D000000, // STP Dt1, Dt2, [Xn, #imm7]
        _ => 0xA9000000,
    };
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rt2 & 0x1F) << 10;
    let scaled_offset = match size {
        0 => (offset / 4) as u32 & 0x7F,
        2 => (offset / 4) as u32 & 0x7F,
        3 => (offset / 8) as u32 & 0x7F,
        _ => (offset / 8) as u32 & 0x7F,
    };
    insn |= scaled_offset << 15;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ldrb(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x39400000; // LDRB Wt, [Xn, #pimm]
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (offset & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_strb(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x39000000; // STRB Wt, [Xn, #pimm]
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (offset & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ldrh(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x79400000; // LDRH Wt, [Xn, #pimm]
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= ((offset / 2) & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_strh(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x79000000; // STRH Wt, [Xn, #pimm]
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= ((offset / 2) & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ldrsw(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xB9800000;
    insn |= rt & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= ((offset / 4) & 0xFFF) << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ldr_literal(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let offset = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x58000000; // LDR Xt, #imm (literal)
    insn |= rt & 0x1F;
    insn |= (offset & 0x7FFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// AArch64 ALU Instructions
// ============================================================================

fn encode_aarch64_cmp(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rn = encode_a64_reg(inst.operands[0].get_reg()?);
    let op2 = &inst.operands[1];

    if let Some(rm) = op2.get_reg() {
        let rm_enc = encode_a64_reg(rm);
        let mut insn: u32 = 0xEB00001F; // SUBS XZR, Xn, Xm
        insn |= (rn & 0x1F) << 5;
        insn |= (rm_enc & 0x1F) << 16;
        Some(insn.to_le_bytes().to_vec())
    } else if let Some(imm) = op2.get_imm() {
        let imm_val = imm as u32;
        let mut insn: u32 = 0xF100001F; // SUBS XZR, Xn, #imm
        insn |= (rn & 0x1F) << 5;
        if let Some((shift, encoded)) = encode_a64_addsub_imm(imm_val as u64) {
            insn |= (shift & 0x1) << 22;
            insn |= (encoded & 0xFFF) << 10;
            return Some(insn.to_le_bytes().to_vec());
        }
        None
    } else {
        None
    }
}

fn encode_aarch64_tst(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rn = encode_a64_reg(inst.operands[0].get_reg()?);

    if let Some(rm) = inst.operands[1].get_reg() {
        let rm_enc = encode_a64_reg(rm);
        let mut insn: u32 = 0xEA00001F; // ANDS XZR, Xn, Xm
        insn |= (rn & 0x1F) << 5;
        insn |= (rm_enc & 0x1F) << 16;
        Some(insn.to_le_bytes().to_vec())
    } else if let Some(imm) = inst.operands[1].get_imm() {
        if let Some((n, immr, imms)) = encode_a64_logical_imm(imm as u64, 64) {
            let mut insn: u32 = 0xF240001F; // ANDS XZR, Xn, #imm
            insn |= (rn & 0x1F) << 5;
            insn |= (n & 0x1) << 22;
            insn |= (immr & 0x3F) << 16;
            insn |= (imms & 0x3F) << 10;
            Some(insn.to_le_bytes().to_vec())
        } else {
            None
        }
    } else {
        None
    }
}

fn encode_aarch64_lsl(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let shift = inst.operands[2].get_imm().unwrap_or(0) as u32;
    if shift > 63 {
        return None;
    }
    let imms: u32 = 63;
    let immr: u32 = ((64 - shift) % 64) & 0x3F;
    let mut insn: u32 = 0xD3400000; // UBFM base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (immr & 0x3F) << 16;
    insn |= (imms & 0x3F) << 10;
    insn |= 1 << 22;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_lsr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let shift = inst.operands[2].get_imm().unwrap_or(0) as u32;
    if shift > 63 {
        return None;
    }
    let imms: u32 = 63;
    let immr: u32 = shift & 0x3F;
    let mut insn: u32 = 0xD3400000;
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (immr & 0x3F) << 16;
    insn |= (imms & 0x3F) << 10;
    insn |= 1 << 22;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_asr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let shift = inst.operands[2].get_imm().unwrap_or(0) as u32;
    if shift > 63 {
        return None;
    }
    let imms: u32 = 63;
    let immr: u32 = shift & 0x3F;
    let mut insn: u32 = 0x9340FC00; // SBFM base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (immr & 0x3F) << 16;
    insn |= (imms & 0x3F) << 10;
    insn |= 1 << 22;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_sdiv(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x9AC00C00; // SDIV base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_udiv(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x9AC00800; // UDIV base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_csel(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 4 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);
    let cond = inst.operands[3].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x9A800000; // CSEL base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (cond & 0xF) << 12;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_adrp(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let imm = inst.operands[1].get_imm().unwrap_or(0) as i64;
    let imm_val = imm as u64;
    let immlo = (imm_val >> 29) & 0x3;
    let immhi = (imm_val >> 5) & 0x7FFFF;
    let mut insn: u32 = 0x90000000; // ADRP base
    insn |= rd & 0x1F;
    insn |= (immhi as u32 & 0x7FFFF) << 5;
    insn |= (immlo as u32 & 0x3) << 29;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_adr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let imm = inst.operands[1].get_imm().unwrap_or(0) as i64;
    let imm_val = imm as u64;
    let immlo = (imm_val >> 29) & 0x3;
    let immhi = (imm_val >> 5) & 0x7FFFF;
    let mut insn: u32 = 0x10000000; // ADR base
    insn |= rd & 0x1F;
    insn |= (immhi as u32 & 0x7FFFF) << 5;
    insn |= (immlo as u32 & 0x3) << 29;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_add_extended(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);
    let extend = inst.operands.get(3).and_then(|o| o.get_imm()).unwrap_or(3) as u32;

    let mut insn: u32 = 0x8B200000; // ADD (extended register) base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    insn |= (extend & 0x7) << 13;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_movk(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let imm = inst.operands[1].get_imm().unwrap_or(0) as u32;
    let hw = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xF2800000; // MOVK base
    insn |= rd & 0x1F;
    insn |= (imm & 0xFFFF) << 5;
    insn |= ((hw / 16) & 0x3) << 21;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_movn(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let imm = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x92800000; // MOVN base
    insn |= rd & 0x1F;
    insn |= (imm & 0xFFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_neg(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rm = encode_a64_reg(inst.operands[1].get_reg()?);

    let mut insn: u32 = 0xCB0003E0; // SUB Xd, XZR, Xm
    insn |= rd & 0x1F;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_mvn(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rm = encode_a64_reg(inst.operands[1].get_reg()?);

    let mut insn: u32 = 0xAA2003E0; // ORN Xd, XZR, Xm
    insn |= rd & 0x1F;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_madd(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 4 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);
    let ra = encode_a64_reg(inst.operands[3].get_reg()?);

    let mut insn: u32 = 0x9B000000; // MADD base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (ra & 0x1F) << 10;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_clz(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);

    let mut insn: u32 = 0xDAC01000; // CLZ base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_rev(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);

    let mut insn: u32 = 0xDAC00C00; // REV (64-bit) base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= 1 << 10;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_extr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 4 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);
    let lsb = inst.operands[3].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x93C00000; // EXTR base
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    insn |= (lsb & 0x3F) << 10;
    insn |= 1 << 22;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// AArch64 Branch & System Instructions
// ============================================================================

fn encode_aarch64_bcond(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let offset = inst.operands[0].get_imm().unwrap_or(0) as u32;
    let cond = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x54000000; // B.cond base
    insn |= cond & 0xF;
    insn |= (offset & 0x7FFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_cbz(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let offset = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xB4000000; // CBZ (64-bit) base
    insn |= rt & 0x1F;
    insn |= (offset & 0x7FFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_cbnz(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let offset = inst.operands[1].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0xB5000000; // CBNZ (64-bit) base
    insn |= rt & 0x1F;
    insn |= (offset & 0x7FFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_tbz(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let bit = inst.operands[1].get_imm().unwrap_or(0) as u32;
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x36000000; // TBZ base
    insn |= rt & 0x1F;
    insn |= (bit & 0x1F) << 19;
    insn |= ((bit >> 5) & 0x1) << 31;
    insn |= (offset & 0x3FFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_tbnz(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rt = encode_a64_reg(inst.operands[0].get_reg()?);
    let bit = inst.operands[1].get_imm().unwrap_or(0) as u32;
    let offset = inst.operands[2].get_imm().unwrap_or(0) as u32;

    let mut insn: u32 = 0x37000000; // TBNZ base
    insn |= rt & 0x1F;
    insn |= (bit & 0x1F) << 19;
    insn |= ((bit >> 5) & 0x1) << 31;
    insn |= (offset & 0x3FFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_ret_reg(inst: &MCInst) -> Option<Vec<u8>> {
    let rn = if let Some(op) = inst.operands.first() {
        encode_a64_reg(op.get_reg()?)
    } else {
        30
    };

    let mut insn: u32 = 0xD65F0000; // RET base
    insn |= (rn & 0x1F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_br(inst: &MCInst) -> Option<Vec<u8>> {
    let rn = encode_a64_reg(inst.operands.first()?.get_reg()?);

    let mut insn: u32 = 0xD61F0000; // BR base
    insn |= (rn & 0x1F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_blr(inst: &MCInst) -> Option<Vec<u8>> {
    let rn = encode_a64_reg(inst.operands.first()?.get_reg()?);

    let mut insn: u32 = 0xD63F0000; // BLR base
    insn |= (rn & 0x1F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_svc(inst: &MCInst) -> Option<Vec<u8>> {
    let imm = inst.operands.first().and_then(|o| o.get_imm()).unwrap_or(0) as u32;

    let mut insn: u32 = 0xD4000001; // SVC #0
    insn |= (imm & 0xFFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_brk(inst: &MCInst) -> Option<Vec<u8>> {
    let imm = inst.operands.first().and_then(|o| o.get_imm()).unwrap_or(0) as u32;

    let mut insn: u32 = 0xD4200000; // BRK #0
    insn |= (imm & 0xFFFF) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_hint(inst: &MCInst) -> Option<Vec<u8>> {
    let imm = inst.operands.first().and_then(|o| o.get_imm()).unwrap_or(0) as u32;

    let mut insn: u32 = 0xD503201F; // HINT #0 = NOP
    insn |= (imm & 0x7F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_isb() -> Vec<u8> {
    0xD5033FDFu32.to_le_bytes().to_vec()
}

fn encode_aarch64_dsb() -> Vec<u8> {
    0xD5033F9Fu32.to_le_bytes().to_vec()
}

fn encode_aarch64_dmb() -> Vec<u8> {
    0xD5033BBFu32.to_le_bytes().to_vec()
}

fn encode_aarch64_msr(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let xt = encode_a64_reg(inst.operands[1].get_reg()?);
    let mut insn: u32 = 0xD500401F; // MSR (register, NZCV condition flags)
    insn |= xt & 0x1F;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_mrs(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let xt = encode_a64_reg(inst.operands[0].get_reg()?);
    let mut insn: u32 = 0xD5304000; // MRS Xt, NZCV
    insn |= xt & 0x1F;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// AArch64 Floating-Point & SIMD Stubs
// ============================================================================

fn encode_aarch64_fadd(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x1E202800; // FADD Sd, Sn, Sm (single-precision)
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_fsub(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x1E203800; // FSUB Sd, Sn, Sm
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_fmul(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x1E200800; // FMUL Sd, Sn, Sm
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_fdiv(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 3 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);
    let rm = encode_a64_reg(inst.operands[2].get_reg()?);

    let mut insn: u32 = 0x1E201800; // FDIV Sd, Sn, Sm
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_fcmp(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rn = encode_a64_reg(inst.operands[0].get_reg()?);
    let rm = encode_a64_reg(inst.operands[1].get_reg()?);

    let mut insn: u32 = 0x1E202000; // FCMP Sn, Sm
    insn |= (rn & 0x1F) << 5;
    insn |= (rm & 0x1F) << 16;
    Some(insn.to_le_bytes().to_vec())
}

fn encode_aarch64_fmov(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);

    if let Some(rm) = inst.operands[1].get_reg() {
        let rm_enc = encode_a64_reg(rm);
        let mut insn: u32 = 0x1E204000; // FMOV Sd, Sm
        insn |= rd & 0x1F;
        insn |= (rm_enc & 0x1F) << 16;
        Some(insn.to_le_bytes().to_vec())
    } else if let Some(imm) = inst.operands[1].get_fpimm() {
        let bits = imm.to_bits() as u32;
        let mut insn: u32 = 0x1E201000; // FMOV Sd, #0.0 base
        insn |= rd & 0x1F;
        insn |= (bits & 0xFF) << 13; // imm8
        Some(insn.to_le_bytes().to_vec())
    } else {
        None
    }
}

fn encode_aarch64_fcvt(inst: &MCInst) -> Option<Vec<u8>> {
    if inst.operands.len() < 2 {
        return None;
    }
    let rd = encode_a64_reg(inst.operands[0].get_reg()?);
    let rn = encode_a64_reg(inst.operands[1].get_reg()?);

    // Default: FCVT Sd, Dn (single to double)
    let mut insn: u32 = 0x1E22C000; // FCVT Sd, Dn
    insn |= rd & 0x1F;
    insn |= (rn & 0x1F) << 5;
    Some(insn.to_le_bytes().to_vec())
}

// ============================================================================
// Enhanced AArch64 Dispatch Table
// ============================================================================

pub fn encode_aarch64_full(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.opcode {
        // Existing core opcodes
        0 => Some(encode_aarch64_nop()),
        1 => encode_aarch64_mov(inst),
        2 => encode_aarch64_add(inst),
        3 => encode_aarch64_sub(inst),
        4 => encode_aarch64_mul(inst),
        5 => encode_aarch64_and(inst),
        6 => encode_aarch64_orr(inst),
        7 => encode_aarch64_eor(inst),
        15 => encode_aarch64_b(inst),
        16 => encode_aarch64_bl(inst),
        17 => Some(encode_aarch64_ret()),

        // Load/store
        18 => encode_aarch64_ldr(inst, 1),
        19 => encode_aarch64_ldr(inst, 0),
        20 => encode_aarch64_str(inst, 1),
        21 => encode_aarch64_str(inst, 0),
        22 => encode_aarch64_ldp(inst, 1),
        23 => encode_aarch64_ldp(inst, 0),
        24 => encode_aarch64_stp(inst, 1),
        25 => encode_aarch64_stp(inst, 0),
        26 => encode_aarch64_cmp(inst),
        27 => encode_aarch64_tst(inst),
        28 => encode_aarch64_lsl(inst),
        29 => encode_aarch64_lsr(inst),
        30 => encode_aarch64_asr(inst),
        31 => encode_aarch64_sdiv(inst),
        32 => encode_aarch64_udiv(inst),
        33 => encode_aarch64_csel(inst),
        34 => encode_aarch64_adrp(inst),
        35 => encode_aarch64_adr(inst),
        36 => encode_aarch64_add_extended(inst),
        37 => encode_aarch64_movk(inst),
        38 => encode_aarch64_movn(inst),
        39 => encode_aarch64_neg(inst),
        40 => encode_aarch64_mvn(inst),
        41 => encode_aarch64_ldrb(inst),
        42 => encode_aarch64_strb(inst),
        43 => encode_aarch64_ldrh(inst),
        44 => encode_aarch64_strh(inst),
        45 => encode_aarch64_ldrsw(inst),
        46 => encode_aarch64_ldr_literal(inst),
        47 => encode_aarch64_madd(inst),
        48 => encode_aarch64_msr(inst),
        49 => encode_aarch64_mrs(inst),
        50 => encode_aarch64_bcond(inst),
        51 => encode_aarch64_cbz(inst),
        52 => encode_aarch64_cbnz(inst),
        53 => encode_aarch64_tbz(inst),
        54 => encode_aarch64_tbnz(inst),
        55 => encode_aarch64_ret_reg(inst),
        56 => encode_aarch64_br(inst),
        57 => encode_aarch64_blr(inst),
        58 => encode_aarch64_clz(inst),
        59 => encode_aarch64_rev(inst),
        60 => encode_aarch64_extr(inst),
        61 => encode_aarch64_svc(inst),
        62 => encode_aarch64_brk(inst),
        63 => encode_aarch64_hint(inst),
        64 => Some(encode_aarch64_isb()),
        65 => Some(encode_aarch64_dsb()),
        66 => Some(encode_aarch64_dmb()),

        // Floating-point
        80 => encode_aarch64_fadd(inst),
        81 => encode_aarch64_fsub(inst),
        82 => encode_aarch64_fmul(inst),
        83 => encode_aarch64_fdiv(inst),
        84 => encode_aarch64_fcmp(inst),
        85 => encode_aarch64_fmov(inst),
        86 => encode_aarch64_fcvt(inst),

        // SIMD load/store
        90 => encode_aarch64_ldr(inst, 2),
        91 => encode_aarch64_str(inst, 2),
        92 => encode_aarch64_ldp(inst, 2),
        93 => encode_aarch64_stp(inst, 2),
        94 => encode_aarch64_ldp(inst, 3),
        95 => encode_aarch64_stp(inst, 3),

        _ => None,
    }
}

// ============================================================================
// RISC-V Instruction Encoder — RV32I/RV64I + Extensions
// ============================================================================

fn rv_push_u32_le(insn: u32) -> Vec<u8> {
    insn.to_le_bytes().to_vec()
}

fn encode_riscv_r(opcode: u32, rd: u32, funct3: u32, rs1: u32, rs2: u32, funct7: u32) -> u32 {
    (funct7 & 0x7F) << 25
        | (rs2 & 0x1F) << 20
        | (rs1 & 0x1F) << 15
        | (funct3 & 0x7) << 12
        | (rd & 0x1F) << 7
        | (opcode & 0x7F)
}

fn encode_riscv_i(opcode: u32, rd: u32, funct3: u32, rs1: u32, imm: i32) -> u32 {
    ((imm as u32) & 0xFFF) << 20
        | (rs1 & 0x1F) << 15
        | (funct3 & 0x7) << 12
        | (rd & 0x1F) << 7
        | (opcode & 0x7F)
}

fn encode_riscv_s(opcode: u32, funct3: u32, rs1: u32, rs2: u32, imm: i32) -> u32 {
    let imm_u = imm as u32;
    ((imm_u >> 5) & 0x7F) << 25
        | (rs2 & 0x1F) << 20
        | (rs1 & 0x1F) << 15
        | (funct3 & 0x7) << 12
        | (imm_u & 0x1F) << 7
        | (opcode & 0x7F)
}

fn encode_riscv_b(opcode: u32, funct3: u32, rs1: u32, rs2: u32, imm: i32) -> u32 {
    let imm_u = imm as u32;
    ((imm_u >> 12) & 0x1) << 31
        | ((imm_u >> 5) & 0x3F) << 25
        | (rs2 & 0x1F) << 20
        | (rs1 & 0x1F) << 15
        | (funct3 & 0x7) << 12
        | ((imm_u >> 1) & 0xF) << 8
        | ((imm_u >> 11) & 0x1) << 7
        | (opcode & 0x7F)
}

fn encode_riscv_u(opcode: u32, rd: u32, imm: i32) -> u32 {
    ((imm as u32) & 0xFFFFF000) | (rd & 0x1F) << 7 | (opcode & 0x7F)
}

fn encode_riscv_j(opcode: u32, rd: u32, imm: i32) -> u32 {
    let imm_u = imm as u32;
    ((imm_u >> 20) & 0x1) << 31
        | ((imm_u >> 1) & 0x3FF) << 21
        | ((imm_u >> 11) & 0x1) << 20
        | ((imm_u >> 12) & 0xFF) << 12
        | (rd & 0x1F) << 7
        | (opcode & 0x7F)
}

const RV_OP_LUI: u32 = 0b0110111;
const RV_OP_AUIPC: u32 = 0b0010111;
const RV_OP_JAL: u32 = 0b1101111;
const RV_OP_JALR: u32 = 0b1100111;
const RV_OP_BRANCH: u32 = 0b1100011;
const RV_OP_LOAD: u32 = 0b0000011;
const RV_OP_STORE: u32 = 0b0100011;
const RV_OP_IMM: u32 = 0b0010011;
const RV_OP_OP: u32 = 0b0110011;
const RV_OP_SYSTEM: u32 = 0b1110011;
const RV_OP_MISC: u32 = 0b0001111;
const RV_OP_IMM32: u32 = 0b0011011;
const RV_OP_OP32: u32 = 0b0111011;

fn encode_rv_reg(reg: u32) -> u32 {
    reg & 0x1F
}

fn rv_get_imm(inst: &MCInst, idx: usize) -> i64 {
    inst.operands
        .get(idx)
        .and_then(|o| o.get_imm())
        .unwrap_or(0)
}

fn rv_get_reg(inst: &MCInst, idx: usize) -> u32 {
    inst.operands
        .get(idx)
        .and_then(|o| o.get_reg())
        .unwrap_or(0)
}

pub fn encode_riscv(inst: &MCInst) -> Option<Vec<u8>> {
    match inst.opcode {
        // === RV32I Integer (R-type) ===
        1 => {
            // ADD
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b000, rs1, rs2, 0b0000000,
            )))
        }
        2 => {
            // SUB
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b000, rs1, rs2, 0b0100000,
            )))
        }
        3 => {
            // SLL
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b001, rs1, rs2, 0b0000000,
            )))
        }
        4 => {
            // SLT
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b010, rs1, rs2, 0b0000000,
            )))
        }
        5 => {
            // SLTU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b011, rs1, rs2, 0b0000000,
            )))
        }
        6 => {
            // XOR
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b100, rs1, rs2, 0b0000000,
            )))
        }
        7 => {
            // SRL
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b101, rs1, rs2, 0b0000000,
            )))
        }
        8 => {
            // SRA
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b101, rs1, rs2, 0b0100000,
            )))
        }
        9 => {
            // OR
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b110, rs1, rs2, 0b0000000,
            )))
        }
        10 => {
            // AND
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b111, rs1, rs2, 0b0000000,
            )))
        }

        // === RV64I (OP-32) ===
        11 => {
            // ADDW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b000, rs1, rs2, 0b0000000,
            )))
        }
        12 => {
            // SUBW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b000, rs1, rs2, 0b0100000,
            )))
        }
        13 => {
            // SLLW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b001, rs1, rs2, 0b0000000,
            )))
        }
        14 => {
            // SRLW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b101, rs1, rs2, 0b0000000,
            )))
        }
        15 => {
            // SRAW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b101, rs1, rs2, 0b0100000,
            )))
        }

        // === I-type (OP-IMM) ===
        20 => {
            // ADDI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b000, rs1, imm,
            )))
        }
        21 => {
            // SLTI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b010, rs1, imm,
            )))
        }
        22 => {
            // SLTIU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b011, rs1, imm,
            )))
        }
        23 => {
            // XORI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b100, rs1, imm,
            )))
        }
        24 => {
            // ORI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b110, rs1, imm,
            )))
        }
        25 => {
            // ANDI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_IMM, rd, 0b111, rs1, imm,
            )))
        }

        // === I-type shifts ===
        30 => {
            // SLLI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x3F) as u32) | 0x000;
            let insn = (imm << 20) | (rs1 << 15) | (0b001 << 12) | (rd << 7) | RV_OP_IMM;
            Some(rv_push_u32_le(insn))
        }
        31 => {
            // SRLI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x3F) as u32) | 0x000;
            let insn = (imm << 20) | (rs1 << 15) | (0b101 << 12) | (rd << 7) | RV_OP_IMM;
            Some(rv_push_u32_le(insn))
        }
        32 => {
            // SRAI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x3F) as u32) | 0x400;
            let insn = (imm << 20) | (rs1 << 15) | (0b101 << 12) | (rd << 7) | RV_OP_IMM;
            Some(rv_push_u32_le(insn))
        }
        33 => {
            // SLLIW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x1F) as u32) | 0x000;
            let insn = (imm << 20) | (rs1 << 15) | (0b001 << 12) | (rd << 7) | RV_OP_IMM32;
            Some(rv_push_u32_le(insn))
        }
        34 => {
            // SRLIW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x1F) as u32) | 0x000;
            let insn = (imm << 20) | (rs1 << 15) | (0b101 << 12) | (rd << 7) | RV_OP_IMM32;
            Some(rv_push_u32_le(insn))
        }
        35 => {
            // SRAIW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let shamt = rv_get_imm(inst, 2) as u32;
            let imm = ((shamt & 0x1F) as u32) | 0x400;
            let insn = (imm << 20) | (rs1 << 15) | (0b101 << 12) | (rd << 7) | RV_OP_IMM32;
            Some(rv_push_u32_le(insn))
        }

        // === LOAD instructions ===
        40 => {
            // LB
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b000, rs1, imm,
            )))
        }
        41 => {
            // LH
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b001, rs1, imm,
            )))
        }
        42 => {
            // LW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b010, rs1, imm,
            )))
        }
        43 => {
            // LBU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b100, rs1, imm,
            )))
        }
        44 => {
            // LHU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b101, rs1, imm,
            )))
        }
        45 => {
            // LD
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b011, rs1, imm,
            )))
        }
        46 => {
            // LWU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_LOAD, rd, 0b110, rs1, imm,
            )))
        }

        // === STORE instructions ===
        50 => {
            // SB
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_s(
                RV_OP_STORE,
                0b000,
                rs1,
                rs2,
                imm,
            )))
        }
        51 => {
            // SH
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_s(
                RV_OP_STORE,
                0b001,
                rs1,
                rs2,
                imm,
            )))
        }
        52 => {
            // SW
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_s(
                RV_OP_STORE,
                0b010,
                rs1,
                rs2,
                imm,
            )))
        }
        53 => {
            // SD
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_s(
                RV_OP_STORE,
                0b011,
                rs1,
                rs2,
                imm,
            )))
        }

        // === BRANCH instructions ===
        60 => {
            // BEQ
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b000,
                rs1,
                rs2,
                imm,
            )))
        }
        61 => {
            // BNE
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b001,
                rs1,
                rs2,
                imm,
            )))
        }
        62 => {
            // BLT
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b100,
                rs1,
                rs2,
                imm,
            )))
        }
        63 => {
            // BGE
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b101,
                rs1,
                rs2,
                imm,
            )))
        }
        64 => {
            // BLTU
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b110,
                rs1,
                rs2,
                imm,
            )))
        }
        65 => {
            // BGEU
            let rs1 = encode_rv_reg(rv_get_reg(inst, 0));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_b(
                RV_OP_BRANCH,
                0b111,
                rs1,
                rs2,
                imm,
            )))
        }

        // === JAL/JALR ===
        70 => {
            // JAL
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as i32;
            Some(rv_push_u32_le(encode_riscv_j(RV_OP_JAL, rd, imm)))
        }
        71 => {
            // JALR
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let imm = rv_get_imm(inst, 2) as i32;
            Some(rv_push_u32_le(encode_riscv_i(
                RV_OP_JALR, rd, 0b000, rs1, imm,
            )))
        }

        // === LUI/AUIPC ===
        80 => {
            // LUI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as i32;
            Some(rv_push_u32_le(encode_riscv_u(RV_OP_LUI, rd, imm)))
        }
        81 => {
            // AUIPC
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as i32;
            Some(rv_push_u32_le(encode_riscv_u(RV_OP_AUIPC, rd, imm)))
        }

        // === SYSTEM ===
        90 => Some(rv_push_u32_le(0x00000073)), // ECALL
        91 => Some(rv_push_u32_le(0x00100073)), // EBREAK
        92 => {
            // FENCE
            let pred = rv_get_imm(inst, 0) as u32 & 0xF;
            let succ = rv_get_imm(inst, 1) as u32 & 0xF;
            let insn = (0b0000 << 28)
                | (pred << 24)
                | (succ << 20)
                | (0b00000 << 15)
                | (0b000 << 12)
                | (0b00000 << 7)
                | RV_OP_MISC;
            Some(rv_push_u32_le(insn))
        }
        93 => Some(rv_push_u32_le(0x0000100F)), // FENCE.I

        // === RV32M/RV64M Multiply ===
        100 => {
            // MUL
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b000, rs1, rs2, 0b0000001,
            )))
        }
        101 => {
            // MULH
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b001, rs1, rs2, 0b0000001,
            )))
        }
        102 => {
            // MULHSU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b010, rs1, rs2, 0b0000001,
            )))
        }
        103 => {
            // MULHU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b011, rs1, rs2, 0b0000001,
            )))
        }
        104 => {
            // DIV
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b100, rs1, rs2, 0b0000001,
            )))
        }
        105 => {
            // DIVU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b101, rs1, rs2, 0b0000001,
            )))
        }
        106 => {
            // REM
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b110, rs1, rs2, 0b0000001,
            )))
        }
        107 => {
            // REMU
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP, rd, 0b111, rs1, rs2, 0b0000001,
            )))
        }
        108 => {
            // MULW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b000, rs1, rs2, 0b0000001,
            )))
        }
        109 => {
            // DIVW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b100, rs1, rs2, 0b0000001,
            )))
        }
        110 => {
            // DIVUW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b101, rs1, rs2, 0b0000001,
            )))
        }
        111 => {
            // REMW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b110, rs1, rs2, 0b0000001,
            )))
        }
        112 => {
            // REMUW
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let rs1 = encode_rv_reg(rv_get_reg(inst, 1));
            let rs2 = encode_rv_reg(rv_get_reg(inst, 2));
            Some(rv_push_u32_le(encode_riscv_r(
                RV_OP_OP32, rd, 0b111, rs1, rs2, 0b0000001,
            )))
        }

        // === RVC Compressed Stubs ===
        500 => Some(vec![0x01, 0x00]), // C.NOP (16-bit)
        501 => {
            // C.ADDI4SPN
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as u32;
            let insn: u16 = ((0x0000u32 | ((rd & 0x7) << 2) | ((imm & 0x3F) << 5) | 0b00) as u16);
            Some(insn.to_le_bytes().to_vec())
        }
        502 => {
            // C.ADDI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as i8;
            let i = imm as u8;
            let insn: u16 = ((0x0001u32
                | ((rd & 0x1F) << 7)
                | ((((i >> 5) & 0x1) as u32) << 12)
                | (((i & 0x1F) as u32) << 2)) as u16);
            Some(insn.to_le_bytes().to_vec())
        }
        503 => {
            // C.LI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as i8;
            let i = imm as u8;
            let insn: u16 = ((0x4001u32
                | ((rd & 0x1F) << 7)
                | ((((i >> 5) & 0x1) as u32) << 12)
                | (((i & 0x1F) as u32) << 2)) as u16);
            Some(insn.to_le_bytes().to_vec())
        }
        504 => {
            // C.LUI
            let rd = encode_rv_reg(rv_get_reg(inst, 0));
            let imm = rv_get_imm(inst, 1) as u32;
            let insn: u16 = ((0x6001u32
                | ((rd & 0x1F) << 7)
                | (((imm >> 17) & 0x1) << 12)
                | (((imm >> 12) & 0x1F) << 2)) as u16);
            Some(insn.to_le_bytes().to_vec())
        }
        505 => {
            // C.J
            let imm = rv_get_imm(inst, 0) as i16;
            let i = imm as u16;
            let insn: u16 = ((0xA001u32
                | (((i as u32 >> 11) & 0x1) << 12)
                | (((i as u32 >> 4) & 0x1) << 11)
                | (((i as u32 >> 9) & 0x3) << 9)
                | (((i as u32 >> 8) & 0x1) << 8)
                | (((i as u32 >> 10) & 0x1) << 7)
                | (((i as u32 >> 6) & 0x1) << 6)
                | (((i as u32 >> 7) & 0x1) << 5)
                | (((i as u32 >> 3) & 0x3) << 3)
                | (((i as u32 >> 1) & 0x3) << 1)) as u16);
            Some(insn.to_le_bytes().to_vec())
        }

        _ => None,
    }
}

// ============================================================================
// M68k Encoder Stubs
// ============================================================================

pub fn encode_m68k(_inst: &MCInst) -> Option<Vec<u8>> {
    None
}

fn encode_m68k_nop() -> Vec<u8> {
    vec![0x4E, 0x71]
}

fn encode_m68k_rts() -> Vec<u8> {
    vec![0x4E, 0x75]
}

fn encode_m68k_rte() -> Vec<u8> {
    vec![0x4E, 0x73]
}

fn encode_m68k_trap(vector: u8) -> Vec<u8> {
    vec![0x4E, 0x40 | (vector & 0xF)]
}

fn encode_m68k_move_w(dst: u8, src: u8) -> Vec<u8> {
    let word: u16 = 0x3000 | ((dst as u16 & 0x7) << 9) | (src as u16 & 0x7);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_move_l(dst: u8, src: u8) -> Vec<u8> {
    let word: u16 = 0x2000 | ((dst as u16 & 0x7) << 9) | (src as u16 & 0x7);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_add_l(dst: u8, src: u8) -> Vec<u8> {
    let word: u16 = 0xD080 | ((dst as u16 & 0x7) << 9) | (src as u16 & 0x7);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_sub_l(dst: u8, src: u8) -> Vec<u8> {
    let word: u16 = 0x9080 | ((dst as u16 & 0x7) << 9) | (src as u16 & 0x7);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_cmp_l(dst: u8, src: u8) -> Vec<u8> {
    let word: u16 = 0xB080 | ((src as u16 & 0x7) << 9) | (dst as u16 & 0x7);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_bra(disp: i8) -> Vec<u8> {
    let word: u16 = 0x6000 | (disp as u8 as u16);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_bsr(disp: i8) -> Vec<u8> {
    let word: u16 = 0x6100 | (disp as u8 as u16);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_jmp_an(reg: u8) -> Vec<u8> {
    let word: u16 = 0x4ED0 | ((reg as u16 & 0x7) << 9);
    word.to_be_bytes().to_vec()
}

fn encode_m68k_jsr_an(reg: u8) -> Vec<u8> {
    let word: u16 = 0x4E90 | ((reg as u16 & 0x7) << 9);
    word.to_be_bytes().to_vec()
}

// ============================================================================
// Encoding Helpers — Cross-Target Utilities
// ============================================================================

pub fn encode_immediate(value: i64, bits: u32, signed: bool) -> Option<u64> {
    if signed {
        let min = -(1i64 << (bits - 1));
        let max = (1i64 << (bits - 1)) - 1;
        if value < min || value > max {
            return None;
        }
        let mask = (1u64 << bits) - 1;
        Some((value as u64) & mask)
    } else {
        if value < 0 {
            return None;
        }
        let max = (1u64 << bits) - 1;
        if (value as u64) > max {
            return None;
        }
        Some(value as u64)
    }
}

pub fn encode_register(reg: u32, target: &str) -> u32 {
    match target {
        "x86_64" => reg & 0xF,
        "aarch64" => reg & 0x1F,
        "arm32" => reg & 0xF,
        "riscv" => reg & 0x1F,
        _ => 0,
    }
}

#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum A64Condition {
    EQ = 0b0000,
    NE = 0b0001,
    CS = 0b0010,
    CC = 0b0011,
    MI = 0b0100,
    PL = 0b0101,
    VS = 0b0110,
    VC = 0b0111,
    HI = 0b1000,
    LS = 0b1001,
    GE = 0b1010,
    LT = 0b1011,
    GT = 0b1100,
    LE = 0b1101,
    AL = 0b1110,
    NV = 0b1111,
}

impl A64Condition {
    pub fn from_name(name: &str) -> Option<Self> {
        match name.to_uppercase().as_str() {
            "EQ" => Some(Self::EQ),
            "NE" => Some(Self::NE),
            "CS" | "HS" => Some(Self::CS),
            "CC" | "LO" => Some(Self::CC),
            "MI" => Some(Self::MI),
            "PL" => Some(Self::PL),
            "VS" => Some(Self::VS),
            "VC" => Some(Self::VC),
            "HI" => Some(Self::HI),
            "LS" => Some(Self::LS),
            "GE" => Some(Self::GE),
            "LT" => Some(Self::LT),
            "GT" => Some(Self::GT),
            "LE" => Some(Self::LE),
            "AL" => Some(Self::AL),
            "NV" => Some(Self::NV),
            _ => None,
        }
    }

    pub fn bits(self) -> u32 {
        self as u32
    }
}

#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum A64Shift {
    LSL = 0b00,
    LSR = 0b01,
    ASR = 0b10,
    ROR = 0b11,
}

impl A64Shift {
    pub fn from_name(name: &str) -> Option<Self> {
        match name.to_uppercase().as_str() {
            "LSL" => Some(Self::LSL),
            "LSR" => Some(Self::LSR),
            "ASR" => Some(Self::ASR),
            "ROR" => Some(Self::ROR),
            _ => None,
        }
    }

    pub fn bits(self) -> u32 {
        self as u32
    }
}

pub fn encode_condition(cond: &str, target: &str) -> Option<u32> {
    match target {
        "aarch64" => A64Condition::from_name(cond).map(|c| c.bits()),
        "arm32" => {
            if let Some(c) = A64Condition::from_name(cond) {
                Some((c.bits() & 0xF) << 28)
            } else {
                cond.parse::<u32>().ok().map(|v| (v & 0xF) << 28)
            }
        }
        _ => Some(0),
    }
}

pub fn encode_aarch64_shift(shift_type: &str, amount: u32) -> Option<(u32, u32)> {
    let st = A64Shift::from_name(shift_type)?;
    if amount > 63 {
        return None;
    }
    Some((st.bits(), amount & 0x3F))
}

// ============================================================================
// Relocation Processing
// ============================================================================

#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum RelocationKind {
    Abs32,
    Abs64,
    PcRel32,
    GotPcRel,
    Plt32,
    Copy,
    GlobDat,
    JumpSlot,
    Relative,
    TlsGd,
    TlsLd,
    TlsIe,
    TlsLe,
}

#[derive(Debug, Clone)]
pub struct RelocationResult {
    pub value: u64,
    pub size: u8,
    pub is_pc_relative: bool,
}

pub fn apply_relocation(
    kind: RelocationKind,
    S: u64,
    A: u64,
    P: u64,
    G: u64,
    L: u64,
    B: u64,
) -> RelocationResult {
    match kind {
        RelocationKind::Abs32 => RelocationResult {
            value: S.wrapping_add(A) as u32 as u64,
            size: 4,
            is_pc_relative: false,
        },
        RelocationKind::Abs64 => RelocationResult {
            value: S.wrapping_add(A),
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::PcRel32 => {
            let val = S.wrapping_add(A).wrapping_sub(P) as i64;
            RelocationResult {
                value: val as u32 as u64,
                size: 4,
                is_pc_relative: true,
            }
        }
        RelocationKind::GotPcRel => {
            let val = G.wrapping_add(A).wrapping_sub(P) as i64;
            RelocationResult {
                value: val as u32 as u64,
                size: 4,
                is_pc_relative: true,
            }
        }
        RelocationKind::Plt32 => {
            let val = L.wrapping_add(A).wrapping_sub(P) as i64;
            RelocationResult {
                value: val as u32 as u64,
                size: 4,
                is_pc_relative: true,
            }
        }
        RelocationKind::Copy => RelocationResult {
            value: S,
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::GlobDat => RelocationResult {
            value: S.wrapping_add(A),
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::JumpSlot => RelocationResult {
            value: S,
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::Relative => RelocationResult {
            value: B.wrapping_add(A),
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::TlsGd => RelocationResult {
            value: 0,
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::TlsLd => RelocationResult {
            value: 0,
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::TlsIe => RelocationResult {
            value: 0,
            size: 8,
            is_pc_relative: false,
        },
        RelocationKind::TlsLe => RelocationResult {
            value: 0,
            size: 8,
            is_pc_relative: false,
        },
    }
}

pub fn elf_relocation_kind(elf_type: u32) -> Option<RelocationKind> {
    match elf_type {
        1 => Some(RelocationKind::Abs32),
        2 => Some(RelocationKind::Copy),
        3 => Some(RelocationKind::GlobDat),
        4 => Some(RelocationKind::JumpSlot),
        5 => Some(RelocationKind::Relative),
        6 => Some(RelocationKind::GotPcRel),
        7 => Some(RelocationKind::Plt32),
        8 => Some(RelocationKind::Abs64),
        _ => None,
    }
}

pub fn x86_64_relocation_kind(elf_type: u32) -> Option<RelocationKind> {
    match elf_type {
        1 => Some(RelocationKind::Abs64),
        2 => Some(RelocationKind::PcRel32),
        3 => Some(RelocationKind::GotPcRel),
        4 => Some(RelocationKind::Plt32),
        5 => Some(RelocationKind::Copy),
        6 => Some(RelocationKind::GlobDat),
        7 => Some(RelocationKind::JumpSlot),
        8 => Some(RelocationKind::Relative),
        10 => Some(RelocationKind::Abs32),
        16 => Some(RelocationKind::TlsGd),
        17 => Some(RelocationKind::TlsLd),
        18 => Some(RelocationKind::TlsIe),
        19 => Some(RelocationKind::TlsLe),
        _ => None,
    }
}

pub fn write_relocation_value(buf: &mut [u8], offset: usize, reloc: &RelocationResult) {
    if offset + reloc.size as usize > buf.len() {
        return;
    }
    match reloc.size {
        4 => {
            let val = reloc.value as u32;
            buf[offset..offset + 4].copy_from_slice(&val.to_le_bytes());
        }
        8 => {
            buf[offset..offset + 8].copy_from_slice(&reloc.value.to_le_bytes());
        }
        _ => {}
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
#[allow(unused_imports)]
mod tests {
    use super::*;
    use crate::mc_inst::{MCInst, MCOperand};
    use crate::mc_streamer::x86_opcodes;

    // === X86-64 Encoding Tests ===

    #[test]
    fn test_encode_nop() {
        let inst = MCInst::new(x86_opcodes::NOP);
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x90]);
    }

    #[test]
    fn test_encode_ret() {
        let inst = MCInst::new(x86_opcodes::RET);
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0xC3]);
    }

    #[test]
    fn test_encode_ret_imm16() {
        let mut inst = MCInst::new(x86_opcodes::RET);
        inst.add_operand(MCOperand::imm(8));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0xC2, 0x08, 0x00]);
    }

    #[test]
    fn test_encode_push_r64() {
        // push rax = 0x50
        let mut inst = MCInst::new(x86_opcodes::PUSH);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x50]);

        // push rcx = 0x51
        let mut inst = MCInst::new(x86_opcodes::PUSH);
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x51]);

        // push r8 = 41 50
        let mut inst = MCInst::new(x86_opcodes::PUSH);
        inst.add_operand(MCOperand::reg(8)); // r8
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x41, 0x50]);
    }

    #[test]
    fn test_encode_pop_r64() {
        // pop rax = 0x58
        let mut inst = MCInst::new(x86_opcodes::POP);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x58]);

        // pop rdi = 0x5F
        let mut inst = MCInst::new(x86_opcodes::POP);
        inst.add_operand(MCOperand::reg(7)); // rdi
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x5F]);
    }

    #[test]
    fn test_encode_mov_r64_r64() {
        // mov rax, rcx: REX.W 89 C8 (mod=11, reg=rcx=1, rm=rax=0)
        let mut inst = MCInst::new(x86_opcodes::MOV);
        inst.add_operand(MCOperand::reg(0)); // dst = rax
        inst.add_operand(MCOperand::reg(1)); // src = rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0x89, 0xC8]);
    }

    #[test]
    fn test_encode_mov_r64_imm64() {
        // mov rax, 42: REX.W B8 2A00000000000000
        let mut inst = MCInst::new(x86_opcodes::MOV);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::imm(42));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded.len(), 10);
        assert_eq!(encoded[0], 0x48); // REX.W
        assert_eq!(encoded[1], 0xB8); // B8+0=rax
                                      // Check imm64
        let imm = i64::from_le_bytes(encoded[2..10].try_into().unwrap());
        assert_eq!(imm, 42);
    }

    #[test]
    fn test_encode_add_r64_r64() {
        // add rax, rcx: REX.W 01 C8 (mod=11, reg=rax=0, rm=rcx=1)
        // Wait - 01 /r means: 01 modRM(reg, rm) where reg is the r64 source
        // Actually for ADD r/m64, r64: 01 /r
        // modRM.reg = src (the r64), modRM.rm = dst (the r/m64)
        let mut inst = MCInst::new(x86_opcodes::ADD);
        inst.add_operand(MCOperand::reg(0)); // dst = rax
        inst.add_operand(MCOperand::reg(1)); // src = rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded.len(), 3);
        assert_eq!(encoded[0], 0x48); // REX.W
        assert_eq!(encoded[1], 0x01); // ADD r/m64, r64
                                      // mod=11, reg=rax_field=0, rm=rcx_field=1 → 0xC8
                                      // Wait: reg field is DST (rax=0), rm is SRC (rcx=1)
                                      // modRM = (3<<6) | (0<<3) | 1 = 0xC0 | 0x01 = 0xC1
                                      // Hmm, let me reconsider. In our encoder, for add r,r:
                                      // out.push(make_modrm(0x03, x86_reg_field(dst), x86_reg_field(src)));
                                      // = (3<<6) | (0<<3) | 1 = 0xC1
        assert_eq!(encoded[2], 0xC1);
    }

    #[test]
    fn test_encode_sub_r64_r64() {
        // sub rax, rcx: REX.W 29 C1 (mod=11, reg=dst=rax=0, rm=src=rcx=1)
        // Actually: 29 /r, modRM.reg = src (the r64), modRM.rm = dst (the r/m64)
        // We have modRM = (3<<6) | reg_field(dst) | reg_field(src)
        // = 0xC0 | 0 | 1 = 0xC1
        let mut inst = MCInst::new(x86_opcodes::SUB);
        inst.add_operand(MCOperand::reg(0)); // dst = rax
        inst.add_operand(MCOperand::reg(1)); // src = rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded.len(), 3);
        assert_eq!(encoded[0], 0x48); // REX.W
        assert_eq!(encoded[1], 0x29); // SUB r/m64, r64
        assert_eq!(encoded[2], 0xC1);
    }

    #[test]
    fn test_encode_add_r32_imm8() {
        // add eax, 1 (using 32-bit reg eax=16): 83 C0 01
        // 83 /0 ib: opcode=0x83, modRM(mod=11, reg/opcode=0, rm=eax=0)
        // eax=16, field=(16-16)%8=0
        let mut inst = MCInst::new(x86_opcodes::ADD);
        inst.size = 4;
        inst.add_operand(MCOperand::reg(16)); // eax
        inst.add_operand(MCOperand::imm(1));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded[0], 0x83);
        // modRM: mod=3, reg/opcode=0 (ADD), rm=0 → 0xC0
        assert_eq!(encoded[1], 0xC0);
        assert_eq!(encoded[2], 0x01);
    }

    #[test]
    fn test_encode_sub_r32_imm8() {
        // sub eax, 1: 83 E8 01 (reg/opcode=5 for SUB)
        let mut inst = MCInst::new(x86_opcodes::SUB);
        inst.size = 4;
        inst.add_operand(MCOperand::reg(16)); // eax
        inst.add_operand(MCOperand::imm(1));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded[0], 0x83);
        assert_eq!(encoded[1], 0xE8); // mod=3, reg/opcode=5, rm=0
        assert_eq!(encoded[2], 0x01);
    }

    #[test]
    fn test_encode_add_r64_imm32() {
        // add rax, 1000: REX.W 81 C0 E8030000
        let mut inst = MCInst::new(x86_opcodes::ADD);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::imm(1000));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded[0], 0x48); // REX.W
        assert_eq!(encoded[1], 0x81); // ADD r/m64, imm32
        assert_eq!(encoded[2], 0xC0); // mod=3, reg/opcode=0, rm=0
        let imm = i32::from_le_bytes(encoded[3..7].try_into().unwrap());
        assert_eq!(imm, 1000);
    }

    #[test]
    fn test_encode_jmp_rel32() {
        // jmp +42: E9 2A 00 00 00
        let mut inst = MCInst::new(x86_opcodes::JMP);
        inst.add_operand(MCOperand::imm(42));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0xE9, 0x2A, 0x00, 0x00, 0x00]);
    }

    #[test]
    fn test_encode_call_rel32() {
        // call +100: E8 64 00 00 00
        let mut inst = MCInst::new(x86_opcodes::CALL);
        inst.add_operand(MCOperand::imm(100));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0xE8, 0x64, 0x00, 0x00, 0x00]);
    }

    #[test]
    fn test_encode_cmp_r64_r64() {
        // cmp rax, rcx: REX.W 39 C1
        let mut inst = MCInst::new(x86_opcodes::CMP);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded.len(), 3);
        assert_eq!(encoded[0], 0x48);
        assert_eq!(encoded[1], 0x39);
        assert_eq!(encoded[2], 0xC1);
    }

    #[test]
    fn test_encode_push_r12() {
        // push r12: 41 54 (REX.B + 50+(12%8=4))
        let mut inst = MCInst::new(x86_opcodes::PUSH);
        inst.add_operand(MCOperand::reg(12)); // r12
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x41, 0x54]);
    }

    #[test]
    fn test_encode_xor_r64_r64() {
        // xor rax, rax: REX.W 31 C0
        let mut inst = MCInst::new(x86_opcodes::XOR);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0x31, 0xC0]);
    }

    #[test]
    fn test_encode_and_r64_r64() {
        // and rax, rcx: REX.W 21 C1
        let mut inst = MCInst::new(x86_opcodes::AND);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0x21, 0xC1]);
    }

    #[test]
    fn test_encode_or_r64_r64() {
        // or rax, rcx: REX.W 09 C1
        let mut inst = MCInst::new(x86_opcodes::OR);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0x09, 0xC1]);
    }

    #[test]
    fn test_encode_mul_r64() {
        // mul rcx: REX.W F7 E1 (mod=11, reg/opcode=4, rm=rcx=1)
        let mut inst = MCInst::new(x86_opcodes::MUL);
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xF7, 0xE1]);
    }

    #[test]
    fn test_encode_inc_r64() {
        // inc rax: REX.W FF C0 (mod=11, reg/opcode=0, rm=rax=0)
        let mut inst = MCInst::new(x86_opcodes::INC);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xFF, 0xC0]);
    }

    #[test]
    fn test_encode_dec_r64() {
        // dec rax: REX.W FF C8 (mod=11, reg/opcode=1, rm=rax=0)
        let mut inst = MCInst::new(x86_opcodes::DEC);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xFF, 0xC8]);
    }

    #[test]
    fn test_encode_not_r64() {
        // not rax: REX.W F7 D0 (mod=11, reg/opcode=2, rm=0)
        let mut inst = MCInst::new(x86_opcodes::NOT);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xF7, 0xD0]);
    }

    #[test]
    fn test_encode_neg_r64() {
        // neg rax: REX.W F7 D8 (mod=11, reg/opcode=3, rm=0)
        let mut inst = MCInst::new(x86_opcodes::NEG);
        inst.add_operand(MCOperand::reg(0)); // rax
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xF7, 0xD8]);
    }

    #[test]
    fn test_encode_shl_r64_cl() {
        // shl rax, cl: REX.W D3 E0 (mod=11, reg/opcode=4, rm=rax=0)
        let mut inst = MCInst::new(x86_opcodes::SHL);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // cl = rcx=1
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xD3, 0xE0]);
    }

    #[test]
    fn test_encode_shl_r64_imm8() {
        // shl rax, 3: REX.W C1 E0 03
        let mut inst = MCInst::new(x86_opcodes::SHL);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::imm(3));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xC1, 0xE0, 0x03]);
    }

    #[test]
    fn test_encode_shr_r64_imm8() {
        // shr rax, 2: REX.W C1 E8 02
        let mut inst = MCInst::new(x86_opcodes::SHR);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::imm(2));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xC1, 0xE8, 0x02]);
    }

    #[test]
    fn test_encode_div_r64() {
        // div rcx: REX.W F7 F1 (mod=11, reg/opcode=6, rm=rcx=1)
        let mut inst = MCInst::new(x86_opcodes::DIV);
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x48, 0xF7, 0xF1]);
    }

    #[test]
    fn test_encode_je_rel32() {
        // je +42: 0F 84 2A 00 00 00
        let mut inst = MCInst::new(x86_opcodes::JE);
        inst.add_operand(MCOperand::imm(42));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x0F, 0x84, 0x2A, 0x00, 0x00, 0x00]);
    }

    #[test]
    fn test_encode_jne_rel32() {
        // jne +42: 0F 85 2A 00 00 00
        let mut inst = MCInst::new(x86_opcodes::JNE);
        inst.add_operand(MCOperand::imm(42));
        let encoded = encode_x86_64(&inst).unwrap();
        assert_eq!(encoded, vec![0x0F, 0x85, 0x2A, 0x00, 0x00, 0x00]);
    }

    // === AArch64 Encoding Tests ===

    #[test]
    fn test_encode_aarch64_nop() {
        let inst = MCInst::new(0); // NOP = opcode 0
        let encoded = encode_aarch64(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_aarch64_ret() {
        let inst = MCInst::new(17); // RET = opcode 17
        let encoded = encode_aarch64(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_aarch64_mov() {
        // mov x0, 42
        let mut inst = MCInst::new(1); // MOV
        inst.add_operand(MCOperand::reg(0)); // x0
        inst.add_operand(MCOperand::imm(42));
        let encoded = encode_aarch64(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_aarch64_add() {
        // add x0, x1, 5
        let mut inst = MCInst::new(2); // ADD
        inst.add_operand(MCOperand::reg(0)); // x0
        inst.add_operand(MCOperand::reg(1)); // x1
        inst.add_operand(MCOperand::imm(5));
        let encoded = encode_aarch64(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_aarch64_sub() {
        // sub x0, x1, 3
        let mut inst = MCInst::new(3); // SUB
        inst.add_operand(MCOperand::reg(0)); // x0
        inst.add_operand(MCOperand::reg(1)); // x1
        inst.add_operand(MCOperand::imm(3));
        let encoded = encode_aarch64(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    // === ARM32 Encoding Tests ===

    #[test]
    fn test_encode_arm32_nop() {
        let inst = MCInst::new(0); // NOP
        let encoded = encode_arm32(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_arm32_mov() {
        // mov r0, r1
        let mut inst = MCInst::new(1); // MOV
        inst.add_operand(MCOperand::reg(0)); // r0
        inst.add_operand(MCOperand::reg(1)); // r1
        let encoded = encode_arm32(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    #[test]
    fn test_encode_arm32_add() {
        // add r0, r1, r2
        let mut inst = MCInst::new(4); // ADD
        inst.add_operand(MCOperand::reg(0)); // r0
        inst.add_operand(MCOperand::reg(1)); // r1
        inst.add_operand(MCOperand::reg(2)); // r2
        let encoded = encode_arm32(&inst).unwrap();
        assert_eq!(encoded.len(), 4);
    }

    // === MCAssembler Tests ===

    #[test]
    fn test_assembler_section_management() {
        let mut asm = MCAssembler::new("x86_64-unknown-linux-gnu");
        let text_idx = asm.get_or_create_section(".text", SectionType::Text);
        let data_idx = asm.get_or_create_section(".data", SectionType::Data);
        assert_ne!(text_idx, data_idx);

        // Repeat creation should return same index
        assert_eq!(
            asm.get_or_create_section(".text", SectionType::Text),
            text_idx
        );
    }

    #[test]
    fn test_assembler_emit_instruction() {
        let mut asm = MCAssembler::new("x86_64-unknown-linux-gnu");
        asm.emit_instruction(vec![0x90]); // nop
        asm.emit_instruction(vec![0xC3]); // ret
        let flat = asm.flatten_section(0);
        assert_eq!(flat, vec![0x90, 0xC3]);
    }

    #[test]
    fn test_assembler_flatten_all() {
        let mut asm = MCAssembler::new("x86_64-unknown-linux-gnu");
        asm.emit_instruction(vec![0x90, 0xC3]); // nop; ret
        asm.emit_data(vec![0xDE, 0xAD, 0xBE, 0xEF], ".rodata");
        let (total, offsets) = asm.flatten_all();
        assert_eq!(total.len(), 6);
        assert_eq!(offsets.len(), 2);
    }

    #[test]
    fn test_assembler_symbol_definition() {
        let mut asm = MCAssembler::new("x86_64-unknown-linux-gnu");
        asm.emit_instruction(vec![0x90]);
        let sec = asm.get_or_create_section(".text", SectionType::Text);
        asm.define_symbol("main", sec, 0, 0);
        assert_eq!(asm.symbols.len(), 1);
        assert_eq!(asm.symbols[0].0, "main");
    }

    // === Roundtrip: Encode then Decode ===

    #[test]
    fn test_roundtrip_x86_nop() {
        let inst = MCInst::new(x86_opcodes::NOP);
        let encoded = encode_x86_64(&inst).unwrap();

        let disasm = crate::mc_disassembler::X86Disassembler::new();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::NOP);
        assert_eq!(decoded.size, 1);
    }

    #[test]
    fn test_roundtrip_x86_ret() {
        let inst = MCInst::new(x86_opcodes::RET);
        let encoded = encode_x86_64(&inst).unwrap();

        let disasm = crate::mc_disassembler::X86Disassembler::new();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::RET);
        assert_eq!(decoded.size, 1);
    }

    #[test]
    fn test_roundtrip_x86_push_r64() {
        for reg in 0..8u32 {
            let mut inst = MCInst::new(x86_opcodes::PUSH);
            inst.add_operand(MCOperand::reg(reg));
            let encoded = encode_x86_64(&inst).unwrap();

            let disasm = crate::mc_disassembler::X86Disassembler::new();
            let decoded = disasm.decode_one(&encoded, 0).unwrap();
            assert_eq!(decoded.inst.opcode, x86_opcodes::PUSH);
            assert_eq!(
                decoded.inst.operands[0].get_reg().unwrap(),
                reg,
                "push r{} roundtrip failed",
                reg
            );
        }
    }

    #[test]
    fn test_roundtrip_x86_pop_r64() {
        for reg in 0..8u32 {
            let mut inst = MCInst::new(x86_opcodes::POP);
            inst.add_operand(MCOperand::reg(reg));
            let encoded = encode_x86_64(&inst).unwrap();

            let disasm = crate::mc_disassembler::X86Disassembler::new();
            let decoded = disasm.decode_one(&encoded, 0).unwrap();
            assert_eq!(decoded.inst.opcode, x86_opcodes::POP);
            assert_eq!(
                decoded.inst.operands[0].get_reg().unwrap(),
                reg,
                "pop r{} roundtrip failed",
                reg
            );
        }
    }

    #[test]
    fn test_roundtrip_x86_mov_r64_r64() {
        // mov rax, rcx
        let mut inst = MCInst::new(x86_opcodes::MOV);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();

        let disasm = crate::mc_disassembler::X86Disassembler::new();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::MOV);
        // Disassembler returns (dst, src) = (reg field from modRM)
        assert_eq!(decoded.inst.operands.len(), 2);
    }

    #[test]
    fn test_roundtrip_x86_add_sub_r64_r64() {
        // add rax, rcx
        let mut inst = MCInst::new(x86_opcodes::ADD);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::reg(1)); // rcx
        let encoded = encode_x86_64(&inst).unwrap();

        let disasm = crate::mc_disassembler::X86Disassembler::new();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::ADD);

        // sub rax, rcx
        let mut inst = MCInst::new(x86_opcodes::SUB);
        inst.add_operand(MCOperand::reg(0));
        inst.add_operand(MCOperand::reg(1));
        let encoded = encode_x86_64(&inst).unwrap();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::SUB);
    }

    #[test]
    fn test_roundtrip_x86_mov_r64_imm64() {
        let mut inst = MCInst::new(x86_opcodes::MOV);
        inst.add_operand(MCOperand::reg(0)); // rax
        inst.add_operand(MCOperand::imm(0xDEADBEEF));
        let encoded = encode_x86_64(&inst).unwrap();

        let disasm = crate::mc_disassembler::X86Disassembler::new();
        let decoded = disasm.decode_one(&encoded, 0).unwrap();
        assert_eq!(decoded.inst.opcode, x86_opcodes::MOV);
        assert_eq!(decoded.inst.operands[0].get_reg().unwrap(), 0); // rax
        assert_eq!(decoded.inst.operands[1].get_imm().unwrap(), 0xDEADBEEF);
    }
}