llvm-native-core 0.1.16

//! X86 Full Disassembler — complete instruction decoder and printer supporting
//! all instruction sets from 8086 through AVX-512, AMX, APX, and beyond.
//!
//! ## Architecture
//!
//! The disassembler is structured as a pipeline:
//! 1. **Prefix Decoding** — legacy prefixes (LOCK, REP, segment overrides,
//!    operand-size, address-size), REX, VEX (2/3 byte), EVEX (4 byte), REX2
//! 2. **Opcode Decoding** — primary map (00-FF), two-byte escape (0F xx),
//!    three-byte escapes (0F 38 xx, 0F 3A xx), VEX/EVEX maps
//! 3. **ModR/M Decoding** — mod, reg/opcode, rm fields
//! 4. **SIB Decoding** — scale, index, base fields (when modrm.rm == 0b100)
//! 5. **Displacement Decoding** — 1, 2, or 4-byte signed displacement
//! 6. **Immediate Decoding** — 1, 2, 4, or 8-byte immediate values
//! 7. **Instruction Formatting** — AT&T and Intel syntax output
//!
//! ## Instruction Set Coverage
//!
//! - 8086/8088, 80186, 80286, 80386, 80486, Pentium, P6
//! - MMX, 3DNow!, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2
//! - AVX, AVX2, FMA, BMI, BMI2, ADX
//! - AVX-512 (F, CD, ER, PF, BW, DQ, VL, IFMA, VBMI, VBMI2, VNNI, BITALG, VPOPCNTDQ, GFNI,
//!   VAES, VPCLMULQDQ, BF16, FP16)
//! - AMX (TILE, TMUL)
//! - APX (Advanced Performance Extensions)
//! - CET, SHA, SGX, SMX, VMX, SVM, TSX, XSAVE
//! - AES, CLMUL, RDRAND, RDSEED, SHA, MPX
//! - UINTR, FRED, LKGS, CMPccXADD
//!
//! Clean-room behavioral reconstruction from:
//! - Intel® 64 and IA-32 Architectures Software Developer's Manual
//! - AMD64 Architecture Programmer's Manual
//! - Published opcode maps and encoding specifications
//! - Black-box oracle interrogation

use crate::mc_disassembler as mc;
use crate::x86::*;

// ============================================================================
// Core Types
// ============================================================================

/// Instruction syntax output format.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DisassemblerSyntax {
    /// AT&T syntax: `movl %eax, (%ebx)`
    Att,
    /// Intel syntax: `mov eax, [ebx]`
    Intel,
    /// Annotated with byte offsets: `0x0: mov eax, ebx`
    Annotated,
}

/// X86 processor mode.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86ProcessorMode {
    /// 16-bit real/protected mode (8086 through 80286)
    Mode16,
    /// 32-bit protected mode (80386 through x86)
    Mode32,
    /// 64-bit long mode (x86-64)
    Mode64,
}

impl X86ProcessorMode {
    pub fn default_operand_size(&self) -> u8 {
        match self {
            X86ProcessorMode::Mode16 => 16,
            X86ProcessorMode::Mode32 => 32,
            X86ProcessorMode::Mode64 => 32,
        }
    }

    pub fn default_address_size(&self) -> u8 {
        match self {
            X86ProcessorMode::Mode16 => 16,
            X86ProcessorMode::Mode32 => 32,
            X86ProcessorMode::Mode64 => 64,
        }
    }

    pub fn is_64bit(&self) -> bool {
        matches!(self, X86ProcessorMode::Mode64)
    }
}

// ============================================================================
// Prefix Decoding Structures
// ============================================================================

/// Legacy prefix information decoded from the instruction byte stream.
#[derive(Debug, Clone, Default)]
pub struct LegacyPrefixInfo {
    /// LOCK prefix (0xF0) present.
    pub has_lock: bool,
    /// REPNE/REPNZ prefix (0xF2) present.
    pub has_repne: bool,
    /// REP/REPZ prefix (0xF3) present.
    pub has_rep: bool,
    /// CS segment override (0x2E) present.
    pub cs_override: bool,
    /// DS segment override (0x3E) present.
    pub ds_override: bool,
    /// SS segment override (0x36) present.
    pub ss_override: bool,
    /// ES segment override (0x26) present.
    pub es_override: bool,
    /// FS segment override (0x64) present.
    pub fs_override: bool,
    /// GS segment override (0x65) present.
    pub gs_override: bool,
    /// Operand-size override (0x66) present.
    pub has_operand_size_override: bool,
    /// Address-size override (0x67) present.
    pub has_address_size_override: bool,
    /// The last active segment override prefix.
    pub active_segment_override: Option<SegmentOverride>,
    /// Effective operand size after all overrides (8, 16, 32, or 64).
    pub effective_operand_size: u8,
    /// Effective address size after all overrides (16, 32, or 64).
    pub effective_address_size: u8,
}

/// Segment override register.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SegmentOverride {
    CS,
    DS,
    SS,
    ES,
    FS,
    GS,
}

impl SegmentOverride {
    pub fn name(&self) -> &'static str {
        match self {
            SegmentOverride::CS => "cs",
            SegmentOverride::DS => "ds",
            SegmentOverride::SS => "ss",
            SegmentOverride::ES => "es",
            SegmentOverride::FS => "fs",
            SegmentOverride::GS => "gs",
        }
    }
}

/// REX prefix decoded fields (for 64-bit mode).
#[derive(Debug, Clone, Copy, Default)]
pub struct RexInfo {
    pub present: bool,
    /// W bit: 64-bit operand size.
    pub w: bool,
    /// R bit: extends ModR/M reg field.
    pub r: bool,
    /// X bit: extends SIB index field.
    pub x: bool,
    /// B bit: extends ModR/M rm field, SIB base, or opcode reg.
    pub b: bool,
}

/// VEX prefix decoded fields (2-byte or 3-byte).
#[derive(Debug, Clone, Copy, Default)]
pub struct VexDecodedInfo {
    pub present: bool,
    /// True for 3-byte VEX (C4), false for 2-byte VEX (C5).
    pub is_3byte: bool,
    /// Inverted R bit from REX: ~R.
    pub r: bool,
    /// Inverted X bit from REX: ~X.
    pub x: bool,
    /// Inverted B bit from REX: ~B.
    pub b: bool,
    /// W bit: 64-bit operand size / opcode extension.
    pub w: bool,
    /// Implied 4-bit register operand (inverted: ~vvvv).
    pub vvvv: u8,
    /// Vector length: 0=128-bit, 1=256-bit (L bit).
    pub l: bool,
    /// Implied mandatory prefix (pp): 0=none, 1=66, 2=F3, 3=F2.
    pub pp: u8,
    /// Map select (mmmmm): 1=0F, 2=0F 38, 3=0F 3A.
    pub mmmmm: u8,
}

/// EVEX prefix decoded fields (4-byte).
#[derive(Debug, Clone, Copy, Default)]
pub struct EvexDecodedInfo {
    pub present: bool,
    /// R' bit (EVEX.R'): extends ModR/M reg (inverted).
    pub r_prime: bool,
    /// X' bit (EVEX.X'): extends SIB index (inverted, alias for B' in some contexts).
    pub x_prime: bool,
    /// B' bit (EVEX.B'): extends ModR/M rm / base (inverted).
    pub b_prime: bool,
    /// R bit (EVEX.R): extends ModR/M reg (inverted).
    pub r: bool,
    /// X bit (EVEX.X): extends SIB index (inverted).
    pub x: bool,
    /// B bit (EVEX.B): extends ModR/M rm / base (inverted).
    pub b: bool,
    /// V' bit: extends vvvv (inverted).
    pub v_prime: bool,
    /// W bit: 64-bit operand size / opcode extension.
    pub w: bool,
    /// Zeroing mask bit.
    pub z: bool,
    /// Embedded opmask register (aaa field, 3 bits).
    pub aaa: u8,
    /// Vector length (L' bit, combined with L for 0, 128, 256, 512).
    pub ll: u8,
    /// Embedded broadcast / rounding control.
    pub b_bit: bool,
    /// Implied mandatory prefix (pp).
    pub pp: u8,
    /// Map select (mm, 5 bits).
    pub mm: u8,
    /// The inverted vvvv register.
    pub vvvv: u8,
}

// ============================================================================
// ModR/M and SIB Decoding
// ============================================================================

/// ModR/M byte decoded fields.
#[derive(Debug, Clone, Copy, Default)]
pub struct ModRMDecoded {
    /// The raw ModR/M byte.
    pub raw: u8,
    /// Mod field (bits 7:6): 0=no displacement, 1=disp8, 2=disp32, 3=register.
    pub mod_field: u8,
    /// Reg/opcode field (bits 5:3).
    pub reg_field: u8,
    /// R/M field (bits 2:0).
    pub rm_field: u8,
}

/// SIB byte decoded fields.
#[derive(Debug, Clone, Copy, Default)]
pub struct SIBDecoded {
    /// The raw SIB byte.
    pub raw: u8,
    /// Scale factor (bits 7:6): 1, 2, 4, or 8.
    pub scale: u8,
    /// Index register field (bits 5:3).
    pub index_field: u8,
    /// Base register field (bits 2:0).
    pub base_field: u8,
}

// ============================================================================
// Addressing Modes
// ============================================================================

/// 16-bit addressing mode encodings.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum AddressMode16 {
    BxSi,
    BxDi,
    BpSi,
    BpDi,
    Si,
    Di,
    Bp,
    Bx,
    Direct(u16),
}

/// 32-bit addressing mode encodings.
#[derive(Debug, Clone, PartialEq, Eq)]
pub enum AddressMode32 {
    /// EAX + Index*Scale + Displacement
    Indexed {
        base: X86RegName,
        index: Option<(X86RegName, u8)>,
        displacement: i32,
    },
    /// SIB with no base (Mod=00, base=101) — disp32 only.
    NoBase {
        index: Option<(X86RegName, u8)>,
        displacement: i32,
    },
    /// Direct register (Mod=11).
    Direct(X86RegName),
    /// EBP-based (Mod=01 or Mod=10 with base=101 but no SIB escape in 32-bit).
    EBPBased { displacement: i32 },
}

/// 64-bit addressing mode encodings.
#[derive(Debug, Clone, PartialEq, Eq)]
pub enum AddressMode64 {
    /// RIP-relative addressing.
    RipRelative(i32),
    /// SIB-based with optional base, index, scale.
    Indexed {
        base: Option<X86RegName>,
        index: Option<(X86RegName, u8)>,
        displacement: i32,
    },
    /// Direct register (Mod=11).
    Direct(X86RegName),
    /// Simple [base + disp] without SIB.
    BaseDisp { base: X86RegName, displacement: i32 },
}

/// X86 register name enumeration.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum X86RegName {
    // 8-bit
    AL,
    CL,
    DL,
    BL,
    AH,
    CH,
    DH,
    BH,
    SPL,
    BPL,
    SIL,
    DIL,
    R8B,
    R9B,
    R10B,
    R11B,
    R12B,
    R13B,
    R14B,
    R15B,
    R16B,
    R17B,
    R18B,
    R19B,
    R20B,
    R21B,
    R22B,
    R23B,
    R24B,
    R25B,
    R26B,
    R27B,
    R28B,
    R29B,
    R30B,
    R31B,
    // 16-bit
    AX,
    CX,
    DX,
    BX,
    SP,
    BP,
    SI,
    DI,
    R8W,
    R9W,
    R10W,
    R11W,
    R12W,
    R13W,
    R14W,
    R15W,
    R16W,
    R17W,
    R18W,
    R19W,
    R20W,
    R21W,
    R22W,
    R23W,
    R24W,
    R25W,
    R26W,
    R27W,
    R28W,
    R29W,
    R30W,
    R31W,
    // 32-bit
    EAX,
    ECX,
    EDX,
    EBX,
    ESP,
    EBP,
    ESI,
    EDI,
    R8D,
    R9D,
    R10D,
    R11D,
    R12D,
    R13D,
    R14D,
    R15D,
    R16D,
    R17D,
    R18D,
    R19D,
    R20D,
    R21D,
    R22D,
    R23D,
    R24D,
    R25D,
    R26D,
    R27D,
    R28D,
    R29D,
    R30D,
    R31D,
    // 64-bit
    RAX,
    RCX,
    RDX,
    RBX,
    RSP,
    RBP,
    RSI,
    RDI,
    R8,
    R9,
    R10,
    R11,
    R12,
    R13,
    R14,
    R15,
    R16,
    R17,
    R18,
    R19,
    R20,
    R21,
    R22,
    R23,
    R24,
    R25,
    R26,
    R27,
    R28,
    R29,
    R30,
    R31,
    // Segment
    ES,
    CS,
    SS,
    DS,
    FS,
    GS,
    // Control
    CR0,
    CR2,
    CR3,
    CR4,
    CR8,
    // Debug
    DR0,
    DR1,
    DR2,
    DR3,
    DR6,
    DR7,
    // MMX
    MM0,
    MM1,
    MM2,
    MM3,
    MM4,
    MM5,
    MM6,
    MM7,
    // XMM (128-bit SSE/AVX)
    XMM0,
    XMM1,
    XMM2,
    XMM3,
    XMM4,
    XMM5,
    XMM6,
    XMM7,
    XMM8,
    XMM9,
    XMM10,
    XMM11,
    XMM12,
    XMM13,
    XMM14,
    XMM15,
    XMM16,
    XMM17,
    XMM18,
    XMM19,
    XMM20,
    XMM21,
    XMM22,
    XMM23,
    XMM24,
    XMM25,
    XMM26,
    XMM27,
    XMM28,
    XMM29,
    XMM30,
    XMM31,
    // YMM (256-bit AVX)
    YMM0,
    YMM1,
    YMM2,
    YMM3,
    YMM4,
    YMM5,
    YMM6,
    YMM7,
    YMM8,
    YMM9,
    YMM10,
    YMM11,
    YMM12,
    YMM13,
    YMM14,
    YMM15,
    YMM16,
    YMM17,
    YMM18,
    YMM19,
    YMM20,
    YMM21,
    YMM22,
    YMM23,
    YMM24,
    YMM25,
    YMM26,
    YMM27,
    YMM28,
    YMM29,
    YMM30,
    YMM31,
    // ZMM (512-bit AVX-512)
    ZMM0,
    ZMM1,
    ZMM2,
    ZMM3,
    ZMM4,
    ZMM5,
    ZMM6,
    ZMM7,
    ZMM8,
    ZMM9,
    ZMM10,
    ZMM11,
    ZMM12,
    ZMM13,
    ZMM14,
    ZMM15,
    ZMM16,
    ZMM17,
    ZMM18,
    ZMM19,
    ZMM20,
    ZMM21,
    ZMM22,
    ZMM23,
    ZMM24,
    ZMM25,
    ZMM26,
    ZMM27,
    ZMM28,
    ZMM29,
    ZMM30,
    ZMM31,
    // Opmask
    K0,
    K1,
    K2,
    K3,
    K4,
    K5,
    K6,
    K7,
    // x87 FPU stack
    ST0,
    ST1,
    ST2,
    ST3,
    ST4,
    ST5,
    ST6,
    ST7,
    // TMM (AMX tile)
    TMM0,
    TMM1,
    TMM2,
    TMM3,
    TMM4,
    TMM5,
    TMM6,
    TMM7,
    // BND
    BND0,
    BND1,
    BND2,
    BND3,
}

impl X86RegName {
    /// Get the register class.
    pub fn class(&self) -> X86RegClass {
        match self {
            X86RegName::AL
            | X86RegName::CL
            | X86RegName::DL
            | X86RegName::BL
            | X86RegName::AH
            | X86RegName::CH
            | X86RegName::DH
            | X86RegName::BH
            | X86RegName::SPL
            | X86RegName::BPL
            | X86RegName::SIL
            | X86RegName::DIL
            | X86RegName::R8B
            | X86RegName::R9B
            | X86RegName::R10B
            | X86RegName::R11B
            | X86RegName::R12B
            | X86RegName::R13B
            | X86RegName::R14B
            | X86RegName::R15B
            | X86RegName::R16B
            | X86RegName::R17B
            | X86RegName::R18B
            | X86RegName::R19B
            | X86RegName::R20B
            | X86RegName::R21B
            | X86RegName::R22B
            | X86RegName::R23B
            | X86RegName::R24B
            | X86RegName::R25B
            | X86RegName::R26B
            | X86RegName::R27B
            | X86RegName::R28B
            | X86RegName::R29B
            | X86RegName::R30B
            | X86RegName::R31B => X86RegClass::GPR8,

            X86RegName::AX
            | X86RegName::CX
            | X86RegName::DX
            | X86RegName::BX
            | X86RegName::SP
            | X86RegName::BP
            | X86RegName::SI
            | X86RegName::DI
            | X86RegName::R8W
            | X86RegName::R9W
            | X86RegName::R10W
            | X86RegName::R11W
            | X86RegName::R12W
            | X86RegName::R13W
            | X86RegName::R14W
            | X86RegName::R15W
            | X86RegName::R16W
            | X86RegName::R17W
            | X86RegName::R18W
            | X86RegName::R19W
            | X86RegName::R20W
            | X86RegName::R21W
            | X86RegName::R22W
            | X86RegName::R23W
            | X86RegName::R24W
            | X86RegName::R25W
            | X86RegName::R26W
            | X86RegName::R27W
            | X86RegName::R28W
            | X86RegName::R29W
            | X86RegName::R30W
            | X86RegName::R31W => X86RegClass::GPR16,

            X86RegName::EAX
            | X86RegName::ECX
            | X86RegName::EDX
            | X86RegName::EBX
            | X86RegName::ESP
            | X86RegName::EBP
            | X86RegName::ESI
            | X86RegName::EDI
            | X86RegName::R8D
            | X86RegName::R9D
            | X86RegName::R10D
            | X86RegName::R11D
            | X86RegName::R12D
            | X86RegName::R13D
            | X86RegName::R14D
            | X86RegName::R15D
            | X86RegName::R16D
            | X86RegName::R17D
            | X86RegName::R18D
            | X86RegName::R19D
            | X86RegName::R20D
            | X86RegName::R21D
            | X86RegName::R22D
            | X86RegName::R23D
            | X86RegName::R24D
            | X86RegName::R25D
            | X86RegName::R26D
            | X86RegName::R27D
            | X86RegName::R28D
            | X86RegName::R29D
            | X86RegName::R30D
            | X86RegName::R31D => X86RegClass::GPR32,

            X86RegName::RAX
            | X86RegName::RCX
            | X86RegName::RDX
            | X86RegName::RBX
            | X86RegName::RSP
            | X86RegName::RBP
            | X86RegName::RSI
            | X86RegName::RDI
            | X86RegName::R8
            | X86RegName::R9
            | X86RegName::R10
            | X86RegName::R11
            | X86RegName::R12
            | X86RegName::R13
            | X86RegName::R14
            | X86RegName::R15
            | X86RegName::R16
            | X86RegName::R17
            | X86RegName::R18
            | X86RegName::R19
            | X86RegName::R20
            | X86RegName::R21
            | X86RegName::R22
            | X86RegName::R23
            | X86RegName::R24
            | X86RegName::R25
            | X86RegName::R26
            | X86RegName::R27
            | X86RegName::R28
            | X86RegName::R29
            | X86RegName::R30
            | X86RegName::R31 => X86RegClass::GPR64,

            X86RegName::ES
            | X86RegName::CS
            | X86RegName::SS
            | X86RegName::DS
            | X86RegName::FS
            | X86RegName::GS => X86RegClass::Segment,

            X86RegName::CR0
            | X86RegName::CR2
            | X86RegName::CR3
            | X86RegName::CR4
            | X86RegName::CR8 => X86RegClass::Control,

            X86RegName::DR0
            | X86RegName::DR1
            | X86RegName::DR2
            | X86RegName::DR3
            | X86RegName::DR6
            | X86RegName::DR7 => X86RegClass::Debug,

            X86RegName::MM0
            | X86RegName::MM1
            | X86RegName::MM2
            | X86RegName::MM3
            | X86RegName::MM4
            | X86RegName::MM5
            | X86RegName::MM6
            | X86RegName::MM7 => X86RegClass::MMX,

            X86RegName::XMM0
            | X86RegName::XMM1
            | X86RegName::XMM2
            | X86RegName::XMM3
            | X86RegName::XMM4
            | X86RegName::XMM5
            | X86RegName::XMM6
            | X86RegName::XMM7
            | X86RegName::XMM8
            | X86RegName::XMM9
            | X86RegName::XMM10
            | X86RegName::XMM11
            | X86RegName::XMM12
            | X86RegName::XMM13
            | X86RegName::XMM14
            | X86RegName::XMM15
            | X86RegName::XMM16
            | X86RegName::XMM17
            | X86RegName::XMM18
            | X86RegName::XMM19
            | X86RegName::XMM20
            | X86RegName::XMM21
            | X86RegName::XMM22
            | X86RegName::XMM23
            | X86RegName::XMM24
            | X86RegName::XMM25
            | X86RegName::XMM26
            | X86RegName::XMM27
            | X86RegName::XMM28
            | X86RegName::XMM29
            | X86RegName::XMM30
            | X86RegName::XMM31 => X86RegClass::XMM,

            X86RegName::YMM0
            | X86RegName::YMM1
            | X86RegName::YMM2
            | X86RegName::YMM3
            | X86RegName::YMM4
            | X86RegName::YMM5
            | X86RegName::YMM6
            | X86RegName::YMM7
            | X86RegName::YMM8
            | X86RegName::YMM9
            | X86RegName::YMM10
            | X86RegName::YMM11
            | X86RegName::YMM12
            | X86RegName::YMM13
            | X86RegName::YMM14
            | X86RegName::YMM15
            | X86RegName::YMM16
            | X86RegName::YMM17
            | X86RegName::YMM18
            | X86RegName::YMM19
            | X86RegName::YMM20
            | X86RegName::YMM21
            | X86RegName::YMM22
            | X86RegName::YMM23
            | X86RegName::YMM24
            | X86RegName::YMM25
            | X86RegName::YMM26
            | X86RegName::YMM27
            | X86RegName::YMM28
            | X86RegName::YMM29
            | X86RegName::YMM30
            | X86RegName::YMM31 => X86RegClass::YMM,

            X86RegName::ZMM0
            | X86RegName::ZMM1
            | X86RegName::ZMM2
            | X86RegName::ZMM3
            | X86RegName::ZMM4
            | X86RegName::ZMM5
            | X86RegName::ZMM6
            | X86RegName::ZMM7
            | X86RegName::ZMM8
            | X86RegName::ZMM9
            | X86RegName::ZMM10
            | X86RegName::ZMM11
            | X86RegName::ZMM12
            | X86RegName::ZMM13
            | X86RegName::ZMM14
            | X86RegName::ZMM15
            | X86RegName::ZMM16
            | X86RegName::ZMM17
            | X86RegName::ZMM18
            | X86RegName::ZMM19
            | X86RegName::ZMM20
            | X86RegName::ZMM21
            | X86RegName::ZMM22
            | X86RegName::ZMM23
            | X86RegName::ZMM24
            | X86RegName::ZMM25
            | X86RegName::ZMM26
            | X86RegName::ZMM27
            | X86RegName::ZMM28
            | X86RegName::ZMM29
            | X86RegName::ZMM30
            | X86RegName::ZMM31 => X86RegClass::ZMM,

            X86RegName::K0
            | X86RegName::K1
            | X86RegName::K2
            | X86RegName::K3
            | X86RegName::K4
            | X86RegName::K5
            | X86RegName::K6
            | X86RegName::K7 => X86RegClass::Opmask,

            X86RegName::ST0
            | X86RegName::ST1
            | X86RegName::ST2
            | X86RegName::ST3
            | X86RegName::ST4
            | X86RegName::ST5
            | X86RegName::ST6
            | X86RegName::ST7 => X86RegClass::FPU,

            X86RegName::TMM0
            | X86RegName::TMM1
            | X86RegName::TMM2
            | X86RegName::TMM3
            | X86RegName::TMM4
            | X86RegName::TMM5
            | X86RegName::TMM6
            | X86RegName::TMM7 => X86RegClass::TMM,

            X86RegName::BND0 | X86RegName::BND1 | X86RegName::BND2 | X86RegName::BND3 => {
                X86RegClass::BND
            }
        }
    }

    /// The register name string in lower case.
    pub fn name(&self) -> &'static str {
        match self {
            // 8-bit
            X86RegName::AL => "al",
            X86RegName::CL => "cl",
            X86RegName::DL => "dl",
            X86RegName::BL => "bl",
            X86RegName::AH => "ah",
            X86RegName::CH => "ch",
            X86RegName::DH => "dh",
            X86RegName::BH => "bh",
            X86RegName::SPL => "spl",
            X86RegName::BPL => "bpl",
            X86RegName::SIL => "sil",
            X86RegName::DIL => "dil",
            X86RegName::R8B => "r8b",
            X86RegName::R9B => "r9b",
            X86RegName::R10B => "r10b",
            X86RegName::R11B => "r11b",
            X86RegName::R12B => "r12b",
            X86RegName::R13B => "r13b",
            X86RegName::R14B => "r14b",
            X86RegName::R15B => "r15b",
            X86RegName::R16B => "r16b",
            X86RegName::R17B => "r17b",
            X86RegName::R18B => "r18b",
            X86RegName::R19B => "r19b",
            X86RegName::R20B => "r20b",
            X86RegName::R21B => "r21b",
            X86RegName::R22B => "r22b",
            X86RegName::R23B => "r23b",
            X86RegName::R24B => "r24b",
            X86RegName::R25B => "r25b",
            X86RegName::R26B => "r26b",
            X86RegName::R27B => "r27b",
            X86RegName::R28B => "r28b",
            X86RegName::R29B => "r29b",
            X86RegName::R30B => "r30b",
            X86RegName::R31B => "r31b",
            // 16-bit
            X86RegName::AX => "ax",
            X86RegName::CX => "cx",
            X86RegName::DX => "dx",
            X86RegName::BX => "bx",
            X86RegName::SP => "sp",
            X86RegName::BP => "bp",
            X86RegName::SI => "si",
            X86RegName::DI => "di",
            X86RegName::R8W => "r8w",
            X86RegName::R9W => "r9w",
            X86RegName::R10W => "r10w",
            X86RegName::R11W => "r11w",
            X86RegName::R12W => "r12w",
            X86RegName::R13W => "r13w",
            X86RegName::R14W => "r14w",
            X86RegName::R15W => "r15w",
            X86RegName::R16W => "r16w",
            X86RegName::R17W => "r17w",
            X86RegName::R18W => "r18w",
            X86RegName::R19W => "r19w",
            X86RegName::R20W => "r20w",
            X86RegName::R21W => "r21w",
            X86RegName::R22W => "r22w",
            X86RegName::R23W => "r23w",
            X86RegName::R24W => "r24w",
            X86RegName::R25W => "r25w",
            X86RegName::R26W => "r26w",
            X86RegName::R27W => "r27w",
            X86RegName::R28W => "r28w",
            X86RegName::R29W => "r29w",
            X86RegName::R30W => "r30w",
            X86RegName::R31W => "r31w",
            // 32-bit
            X86RegName::EAX => "eax",
            X86RegName::ECX => "ecx",
            X86RegName::EDX => "edx",
            X86RegName::EBX => "ebx",
            X86RegName::ESP => "esp",
            X86RegName::EBP => "ebp",
            X86RegName::ESI => "esi",
            X86RegName::EDI => "edi",
            X86RegName::R8D => "r8d",
            X86RegName::R9D => "r9d",
            X86RegName::R10D => "r10d",
            X86RegName::R11D => "r11d",
            X86RegName::R12D => "r12d",
            X86RegName::R13D => "r13d",
            X86RegName::R14D => "r14d",
            X86RegName::R15D => "r15d",
            X86RegName::R16D => "r16d",
            X86RegName::R17D => "r17d",
            X86RegName::R18D => "r18d",
            X86RegName::R19D => "r19d",
            X86RegName::R20D => "r20d",
            X86RegName::R21D => "r21d",
            X86RegName::R22D => "r22d",
            X86RegName::R23D => "r23d",
            X86RegName::R24D => "r24d",
            X86RegName::R25D => "r25d",
            X86RegName::R26D => "r26d",
            X86RegName::R27D => "r27d",
            X86RegName::R28D => "r28d",
            X86RegName::R29D => "r29d",
            X86RegName::R30D => "r30d",
            X86RegName::R31D => "r31d",
            // 64-bit
            X86RegName::RAX => "rax",
            X86RegName::RCX => "rcx",
            X86RegName::RDX => "rdx",
            X86RegName::RBX => "rbx",
            X86RegName::RSP => "rsp",
            X86RegName::RBP => "rbp",
            X86RegName::RSI => "rsi",
            X86RegName::RDI => "rdi",
            X86RegName::R8 => "r8",
            X86RegName::R9 => "r9",
            X86RegName::R10 => "r10",
            X86RegName::R11 => "r11",
            X86RegName::R12 => "r12",
            X86RegName::R13 => "r13",
            X86RegName::R14 => "r14",
            X86RegName::R15 => "r15",
            X86RegName::R16 => "r16",
            X86RegName::R17 => "r17",
            X86RegName::R18 => "r18",
            X86RegName::R19 => "r19",
            X86RegName::R20 => "r20",
            X86RegName::R21 => "r21",
            X86RegName::R22 => "r22",
            X86RegName::R23 => "r23",
            X86RegName::R24 => "r24",
            X86RegName::R25 => "r25",
            X86RegName::R26 => "r26",
            X86RegName::R27 => "r27",
            X86RegName::R28 => "r28",
            X86RegName::R29 => "r29",
            X86RegName::R30 => "r30",
            X86RegName::R31 => "r31",
            // Segment
            X86RegName::ES => "es",
            X86RegName::CS => "cs",
            X86RegName::SS => "ss",
            X86RegName::DS => "ds",
            X86RegName::FS => "fs",
            X86RegName::GS => "gs",
            // Control
            X86RegName::CR0 => "cr0",
            X86RegName::CR2 => "cr2",
            X86RegName::CR3 => "cr3",
            X86RegName::CR4 => "cr4",
            X86RegName::CR8 => "cr8",
            // Debug
            X86RegName::DR0 => "dr0",
            X86RegName::DR1 => "dr1",
            X86RegName::DR2 => "dr2",
            X86RegName::DR3 => "dr3",
            X86RegName::DR6 => "dr6",
            X86RegName::DR7 => "dr7",
            // MMX
            X86RegName::MM0 => "mm0",
            X86RegName::MM1 => "mm1",
            X86RegName::MM2 => "mm2",
            X86RegName::MM3 => "mm3",
            X86RegName::MM4 => "mm4",
            X86RegName::MM5 => "mm5",
            X86RegName::MM6 => "mm6",
            X86RegName::MM7 => "mm7",
            // XMM
            X86RegName::XMM0 => "xmm0",
            X86RegName::XMM1 => "xmm1",
            X86RegName::XMM2 => "xmm2",
            X86RegName::XMM3 => "xmm3",
            X86RegName::XMM4 => "xmm4",
            X86RegName::XMM5 => "xmm5",
            X86RegName::XMM6 => "xmm6",
            X86RegName::XMM7 => "xmm7",
            X86RegName::XMM8 => "xmm8",
            X86RegName::XMM9 => "xmm9",
            X86RegName::XMM10 => "xmm10",
            X86RegName::XMM11 => "xmm11",
            X86RegName::XMM12 => "xmm12",
            X86RegName::XMM13 => "xmm13",
            X86RegName::XMM14 => "xmm14",
            X86RegName::XMM15 => "xmm15",
            X86RegName::XMM16 => "xmm16",
            X86RegName::XMM17 => "xmm17",
            X86RegName::XMM18 => "xmm18",
            X86RegName::XMM19 => "xmm19",
            X86RegName::XMM20 => "xmm20",
            X86RegName::XMM21 => "xmm21",
            X86RegName::XMM22 => "xmm22",
            X86RegName::XMM23 => "xmm23",
            X86RegName::XMM24 => "xmm24",
            X86RegName::XMM25 => "xmm25",
            X86RegName::XMM26 => "xmm26",
            X86RegName::XMM27 => "xmm27",
            X86RegName::XMM28 => "xmm28",
            X86RegName::XMM29 => "xmm29",
            X86RegName::XMM30 => "xmm30",
            X86RegName::XMM31 => "xmm31",
            // YMM
            X86RegName::YMM0 => "ymm0",
            X86RegName::YMM1 => "ymm1",
            X86RegName::YMM2 => "ymm2",
            X86RegName::YMM3 => "ymm3",
            X86RegName::YMM4 => "ymm4",
            X86RegName::YMM5 => "ymm5",
            X86RegName::YMM6 => "ymm6",
            X86RegName::YMM7 => "ymm7",
            X86RegName::YMM8 => "ymm8",
            X86RegName::YMM9 => "ymm9",
            X86RegName::YMM10 => "ymm10",
            X86RegName::YMM11 => "ymm11",
            X86RegName::YMM12 => "ymm12",
            X86RegName::YMM13 => "ymm13",
            X86RegName::YMM14 => "ymm14",
            X86RegName::YMM15 => "ymm15",
            X86RegName::YMM16 => "ymm16",
            X86RegName::YMM17 => "ymm17",
            X86RegName::YMM18 => "ymm18",
            X86RegName::YMM19 => "ymm19",
            X86RegName::YMM20 => "ymm20",
            X86RegName::YMM21 => "ymm21",
            X86RegName::YMM22 => "ymm22",
            X86RegName::YMM23 => "ymm23",
            X86RegName::YMM24 => "ymm24",
            X86RegName::YMM25 => "ymm25",
            X86RegName::YMM26 => "ymm26",
            X86RegName::YMM27 => "ymm27",
            X86RegName::YMM28 => "ymm28",
            X86RegName::YMM29 => "ymm29",
            X86RegName::YMM30 => "ymm30",
            X86RegName::YMM31 => "ymm31",
            // ZMM
            X86RegName::ZMM0 => "zmm0",
            X86RegName::ZMM1 => "zmm1",
            X86RegName::ZMM2 => "zmm2",
            X86RegName::ZMM3 => "zmm3",
            X86RegName::ZMM4 => "zmm4",
            X86RegName::ZMM5 => "zmm5",
            X86RegName::ZMM6 => "zmm6",
            X86RegName::ZMM7 => "zmm7",
            X86RegName::ZMM8 => "zmm8",
            X86RegName::ZMM9 => "zmm9",
            X86RegName::ZMM10 => "zmm10",
            X86RegName::ZMM11 => "zmm11",
            X86RegName::ZMM12 => "zmm12",
            X86RegName::ZMM13 => "zmm13",
            X86RegName::ZMM14 => "zmm14",
            X86RegName::ZMM15 => "zmm15",
            X86RegName::ZMM16 => "zmm16",
            X86RegName::ZMM17 => "zmm17",
            X86RegName::ZMM18 => "zmm18",
            X86RegName::ZMM19 => "zmm19",
            X86RegName::ZMM20 => "zmm20",
            X86RegName::ZMM21 => "zmm21",
            X86RegName::ZMM22 => "zmm22",
            X86RegName::ZMM23 => "zmm23",
            X86RegName::ZMM24 => "zmm24",
            X86RegName::ZMM25 => "zmm25",
            X86RegName::ZMM26 => "zmm26",
            X86RegName::ZMM27 => "zmm27",
            X86RegName::ZMM28 => "zmm28",
            X86RegName::ZMM29 => "zmm29",
            X86RegName::ZMM30 => "zmm30",
            X86RegName::ZMM31 => "zmm31",
            // Opmask
            X86RegName::K0 => "k0",
            X86RegName::K1 => "k1",
            X86RegName::K2 => "k2",
            X86RegName::K3 => "k3",
            X86RegName::K4 => "k4",
            X86RegName::K5 => "k5",
            X86RegName::K6 => "k6",
            X86RegName::K7 => "k7",
            // FPU
            X86RegName::ST0 => "st(0)",
            X86RegName::ST1 => "st(1)",
            X86RegName::ST2 => "st(2)",
            X86RegName::ST3 => "st(3)",
            X86RegName::ST4 => "st(4)",
            X86RegName::ST5 => "st(5)",
            X86RegName::ST6 => "st(6)",
            X86RegName::ST7 => "st(7)",
            // TMM
            X86RegName::TMM0 => "tmm0",
            X86RegName::TMM1 => "tmm1",
            X86RegName::TMM2 => "tmm2",
            X86RegName::TMM3 => "tmm3",
            X86RegName::TMM4 => "tmm4",
            X86RegName::TMM5 => "tmm5",
            X86RegName::TMM6 => "tmm6",
            X86RegName::TMM7 => "tmm7",
            // BND
            X86RegName::BND0 => "bnd0",
            X86RegName::BND1 => "bnd1",
            X86RegName::BND2 => "bnd2",
            X86RegName::BND3 => "bnd3",
        }
    }

    /// The register name as used in AT&T syntax (with % prefix).
    pub fn att_name(&self) -> String {
        format!("%{}", self.name())
    }

    /// The AT&T size suffix for this register (l, w, b, q, etc.).
    pub fn size_suffix(&self) -> &'static str {
        match self.class() {
            X86RegClass::GPR8 => "b",
            X86RegClass::GPR16 => "w",
            X86RegClass::GPR32 => "l",
            X86RegClass::GPR64 => "q",
            X86RegClass::XMM => "x",
            X86RegClass::YMM => "y",
            X86RegClass::ZMM => "z",
            _ => "",
        }
    }
}

/// Register class categorization.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86RegClass {
    GPR8,
    GPR16,
    GPR32,
    GPR64,
    Segment,
    Control,
    Debug,
    MMX,
    XMM,
    YMM,
    ZMM,
    Opmask,
    FPU,
    TMM,
    BND,
}

// ============================================================================
// Decoded Instruction
// ============================================================================

/// A fully decoded X86 instruction with all operands resolved.
#[derive(Debug, Clone)]
pub struct X86DecodedInstruction {
    /// The mnemonic string (e.g., "mov", "add", "vaddps").
    pub mnemonic: String,
    /// The raw opcode byte (or first opcode byte for multi-byte encodings).
    pub opcode: u16,
    /// The instruction encoding map used.
    pub opcode_map: X86OpcodeMap,
    /// Resolved operands.
    pub operands: Vec<X86DecodedOperand>,
    /// Total instruction size in bytes.
    pub size: usize,
    /// Instruction address (for relative calculations).
    pub address: u64,
    /// Decoded prefix information.
    pub prefixes: LegacyPrefixInfo,
    /// REX prefix info (if applicable).
    pub rex: Option<RexInfo>,
    /// VEX prefix info (if applicable).
    pub vex: Option<VexDecodedInfo>,
    /// EVEX prefix info (if applicable).
    pub evex: Option<EvexDecodedInfo>,
    /// Whether the instruction implicitly operates on specific registers.
    pub implicit_operands: Vec<X86DecodedOperand>,
    /// Instruction attribute flags.
    pub attributes: InstructionAttributes,
    /// Opcode extension from ModR/M reg field (for group instructions).
    pub opcode_extension: Option<u8>,
    /// Effective operand size.
    pub operand_size: u8,
    /// Effective address size.
    pub address_size: u8,
    /// Vector length in bits (0 if not a vector instruction).
    pub vector_length: u16,
}

/// Instruction attribute flags.
#[derive(Debug, Clone, Copy, Default)]
pub struct InstructionAttributes {
    pub has_modrm: bool,
    pub has_sib: bool,
    pub has_displacement: bool,
    pub has_immediate: bool,
    pub is_branch: bool,
    pub is_call: bool,
    pub is_return: bool,
    pub is_conditional: bool,
    pub is_privileged: bool,
    pub is_sse: bool,
    pub is_avx: bool,
    pub is_avx512: bool,
    pub uses_vvvv: bool,
    pub uses_opmask: bool,
    pub uses_broadcast: bool,
    pub uses_zeroing: bool,
    pub uses_er: bool,
    pub uses_sae: bool,
    pub has_lock_prefix: bool,
    pub has_rep_prefix: bool,
    pub has_repne_prefix: bool,
    pub is_64bit_only: bool,
    pub is_32bit_only: bool,
    pub is_string_instruction: bool,
    pub is_group_instruction: bool,
    pub opcode_extension_from_3bits: bool,
}

/// A single decoded operand (register, memory, immediate, etc.).
#[derive(Debug, Clone, PartialEq, Eq)]
pub enum X86DecodedOperand {
    /// Register operand.
    Register {
        reg: X86RegName,
        /// Size suffix hint.
        size_hint: OperandSizeHint,
    },
    /// Memory operand.
    Memory {
        segment: Option<SegmentOverride>,
        base: Option<X86RegName>,
        index: Option<(X86RegName, u8)>,
        displacement: i64,
        size_hint: OperandSizeHint,
        rip_relative: bool,
    },
    /// Immediate value.
    Immediate { value: i64, size: u8 },
    /// PC-relative branch target.
    RelativeOffset { offset: i64, size: u8 },
    /// Implicit register (not encoded in ModR/M).
    ImplicitRegister { reg: X86RegName },
    /// Opmask register (AVX-512).
    OpmaskRegister { reg: X86RegName, zeroing: bool },
    /// X87 FPU stack register.
    FPURegister { index: u8 },
}

/// Size hint for operand formatting.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum OperandSizeHint {
    None,
    Byte,
    Word,
    Dword,
    Qword,
    Oword,  // 128-bit
    Yword,  // 256-bit
    Zword,  // 512-bit
    Single, // 32-bit float
    Double, // 64-bit float
    Fword,  // 48-bit far pointer
    Tbyte,  // 80-bit
}

impl OperandSizeHint {
    pub fn att_suffix(&self) -> &'static str {
        match self {
            OperandSizeHint::Byte => "b",
            OperandSizeHint::Word => "w",
            OperandSizeHint::Dword => "l",
            OperandSizeHint::Qword => "q",
            OperandSizeHint::Oword => "x",
            OperandSizeHint::Yword => "y",
            OperandSizeHint::Zword => "z",
            OperandSizeHint::Single => "s",
            OperandSizeHint::Double => "d",
            OperandSizeHint::Fword => "f",
            OperandSizeHint::Tbyte => "t",
            OperandSizeHint::None => "",
        }
    }

    pub fn intel_prefix(&self) -> &'static str {
        match self {
            OperandSizeHint::Byte => "byte ptr ",
            OperandSizeHint::Word => "word ptr ",
            OperandSizeHint::Dword => "dword ptr ",
            OperandSizeHint::Qword => "qword ptr ",
            OperandSizeHint::Oword => "xmmword ptr ",
            OperandSizeHint::Yword => "ymmword ptr ",
            OperandSizeHint::Zword => "zmmword ptr ",
            OperandSizeHint::Single => "dword ptr ",
            OperandSizeHint::Double => "qword ptr ",
            OperandSizeHint::Fword => "fword ptr ",
            OperandSizeHint::Tbyte => "tbyte ptr ",
            OperandSizeHint::None => "",
        }
    }
}

/// Which opcode map the instruction came from.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum X86OpcodeMap {
    Primary,   // 1-byte: 00-FF
    Map0F,     // 2-byte: 0F xx
    Map0F38,   // 3-byte: 0F 38 xx
    Map0F3A,   // 3-byte: 0F 3A xx
    VexMap1,   // VEX map 1 (0F)
    VexMap2,   // VEX map 2 (0F 38)
    VexMap3,   // VEX map 3 (0F 3A)
    EvexMap1,  // EVEX map 1 (0F)
    EvexMap2,  // EVEX map 2 (0F 38)
    EvexMap3,  // EVEX map 3 (0F 3A)
    EvexMap4,  // EVEX map 4
    EvexMap5,  // EVEX map 5
    EvexMap6,  // EVEX map 6
    XopMap8,   // XOP map 8
    XopMap9,   // XOP map 9
    XopMapA,   // XOP map A
    ThreeDNow, // 3DNow!
    Group,     // Group instruction (uses ModR/M reg field for opcode extension)
}

// ============================================================================
// Instruction Table Entry
// ============================================================================

/// A single entry in the instruction decode table.
#[derive(Debug, Clone)]
pub struct InstrTableEntry {
    pub opcode: u16,
    pub mnemonic: &'static str,
    pub encoding_form: InstrEncodingForm,
    pub has_modrm: bool,
    pub imm_size: u8,
    pub attributes: InstructionAttributes,
    /// For group instructions: which group number (1-17).
    pub group: Option<u8>,
    /// Size suffix hint for AT&T syntax.
    pub att_size_hint: OperandSizeHint,
}

/// How operands are encoded for this instruction.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum InstrEncodingForm {
    /// No operands encoded.
    Implicit,
    /// Register only.
    RegOnly,
    /// ModR/M: reg = register, rm = register.
    RegRM,
    /// ModR/M: reg = opcode extension, rm = register.
    OpcodeExtRM,
    /// ModR/M: reg = register, rm = register/memory.
    RmReg,
    /// ModR/M: rm = register.
    RmOnly,
    /// ModR/M: reg = register, rm ignored + immediate.
    RegImm,
    /// ModR/M: rm = register/memory + immediate.
    RmImm,
    /// ModR/M: reg = register, rm = register/memory + immediate.
    RmRegImm,
    /// ModR/M: reg = register, rm = register/memory + immediate in ModR/M.
    RmRegImmModRM,
    /// PC-relative branch.
    RelBranch,
    /// Accumulator + immediate (AL/AX/EAX/RAX).
    AccumImm,
    /// Accumulator + memory address.
    AccumMem,
    /// Memory address + accumulator.
    MemAccum,
    /// VEX/EVEX specific: reg, vvvv, rm.
    VexRegVvvvRm,
    /// VEX/EVEX: vvvv, rm, reg.
    VexVvvvRmReg,
    /// VEX/EVEX: vvvv, rm + immediate.
    VexVvvvRmImm,
    /// VEX/EVEX: rm, reg.
    VexRmReg,
    /// EVEX: reg{k}, rm (memory-only)
    EvexRegKRm,
    /// EVEX: vvvv{k}, rm, reg
    EvexVvvvKRmReg,
    /// EVEX: vvvv{k}, rm, reg + immediate
    EvexVvvvKRmRegImm,
    /// Group instruction — opcode extension from ModR/M reg.
    GroupOpcodeExt,
    /// Reg + RM + immediate (common encoding form).
    RegRMImm,
    /// Immediate8 only (no ModR/M).
    Immediate8,
    /// VEX/EVEX: reg, vvvv, rm + immediate.
    VexRegVvvvRmImm,
    /// Store instruction form (memory destination).
    Store,
}

// ============================================================================
// X86FullDisassembler — Main Disassembler Interface
// ============================================================================

/// Complete X86 disassembler supporting all instruction sets from 8086 through AVX-512 and AMX.
///
/// Can be used in three modes:
/// - 16-bit (real / protected mode)
/// - 32-bit (protected mode)
/// - 64-bit (long mode)
///
/// Output formats: AT&T syntax, Intel syntax, and annotated (byte offsets).
pub struct X86FullDisassembler {
    /// Processor operating mode.
    pub mode: X86ProcessorMode,
    /// Base address for PC-relative calculations.
    pub base_address: u64,
    /// Internal instruction decoder.
    decoder: X86InstructionDecoder,
    /// Instruction formatter.
    printer: X86InstructionPrinter,
    /// Output syntax style.
    pub syntax: DisassemblerSyntax,
    /// Whether to show instruction bytes in output.
    pub show_bytes: bool,
    /// Maximum number of bytes to decode per instruction (0 = unlimited).
    pub max_insn_size: usize,
    /// Whether to validate operand encodings.
    pub validate: bool,
}

impl X86FullDisassembler {
    pub fn new(mode: X86ProcessorMode) -> Self {
        X86FullDisassembler {
            mode,
            base_address: 0,
            decoder: X86InstructionDecoder::new(mode),
            printer: X86InstructionPrinter::new(DisassemblerSyntax::Intel),
            syntax: DisassemblerSyntax::Intel,
            show_bytes: false,
            max_insn_size: 15,
            validate: true,
        }
    }

    pub fn with_address(mut self, addr: u64) -> Self {
        self.base_address = addr;
        self.decoder.set_base_address(addr);
        self
    }

    pub fn with_syntax(mut self, syntax: DisassemblerSyntax) -> Self {
        self.syntax = syntax;
        self.printer.set_syntax(syntax);
        self
    }

    pub fn with_show_bytes(mut self, show: bool) -> Self {
        self.show_bytes = show;
        self
    }

    /// Decode and disassemble a single instruction from the byte slice.
    /// Returns `Some((decoded, formatted_string))` on success, `None` on failure.
    pub fn disassemble_one(&mut self, bytes: &[u8]) -> Option<(X86DecodedInstruction, String)> {
        let limit = if self.max_insn_size > 0 {
            bytes.len().min(self.max_insn_size)
        } else {
            bytes.len()
        };
        let slice = &bytes[..limit];
        let decoded = self.decoder.decode_one(slice)?;
        let formatted = self.printer.format(&decoded, self.show_bytes, bytes);
        Some((decoded, formatted))
    }

    /// Disassemble all instructions in the byte slice.
    /// Returns a vector of formatted instruction strings.
    pub fn disassemble_all(&mut self, bytes: &[u8]) -> Vec<String> {
        let mut results = Vec::new();
        let mut offset = 0usize;

        while offset < bytes.len() {
            let remaining = &bytes[offset..];
            if let Some((decoded, formatted)) = self.disassemble_one(remaining) {
                results.push(formatted);
                offset += decoded.size;
            } else {
                // Emit unknown byte as raw data
                if offset < bytes.len() {
                    results.push(format!("\t.byte 0x{:02x}", bytes[offset]));
                    offset += 1;
                }
            }
        }

        results
    }

    /// Decode a single instruction into its structured representation.
    pub fn decode_one(&mut self, bytes: &[u8]) -> Option<X86DecodedInstruction> {
        self.decoder.decode_one(bytes)
    }

    /// Change the processor mode.
    pub fn set_mode(&mut self, mode: X86ProcessorMode) {
        self.mode = mode;
        self.decoder.set_mode(mode);
    }

    /// Change the base address.
    pub fn set_base_address(&mut self, addr: u64) {
        self.base_address = addr;
        self.decoder.set_base_address(addr);
    }
}

// ============================================================================
// X86InstructionDecoder — Full Instruction Decoder
// ============================================================================

/// Low-level X86 instruction byte decoder.
///
/// Decodes the full instruction encoding pipeline:
/// 1. Legacy prefixes
/// 2. REX prefix
/// 3. VEX/EVEX/XOP prefixes
/// 4. Opcode byte(s)
/// 5. ModR/M byte
/// 6. SIB byte
/// 7. Displacement
/// 8. Immediate(s)
pub struct X86InstructionDecoder {
    pub mode: X86ProcessorMode,
    pub base_address: u64,
    /// Current position in the byte stream during decode.
    pos: usize,
    /// Current byte slice being decoded.
    bytes: Vec<u8>,
    /// Decoded legacy prefixes.
    prefixes: LegacyPrefixInfo,
    /// Decoded REX.
    rex: Option<RexInfo>,
    /// Decoded VEX.
    vex: Option<VexDecodedInfo>,
    /// Decoded EVEX.
    evex: Option<EvexDecodedInfo>,
    /// Decoded ModR/M.
    modrm: Option<ModRMDecoded>,
    /// Decoded SIB.
    sib: Option<SIBDecoded>,
    /// Displacement value.
    displacement: i64,
    /// Immediate values (ordered).
    immediates: Vec<i64>,
    /// First opcode byte after prefixes.
    opcode: u16,
    /// Full opcode including escape bytes.
    full_opcode: Vec<u8>,
    /// Which map the opcode came from.
    opcode_map: X86OpcodeMap,
}

impl X86InstructionDecoder {
    pub fn new(mode: X86ProcessorMode) -> Self {
        X86InstructionDecoder {
            mode,
            base_address: 0,
            pos: 0,
            bytes: Vec::new(),
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            modrm: None,
            sib: None,
            displacement: 0,
            immediates: Vec::new(),
            opcode: 0,
            full_opcode: Vec::new(),
            opcode_map: X86OpcodeMap::Primary,
        }
    }

    pub fn set_base_address(&mut self, addr: u64) {
        self.base_address = addr;
    }

    pub fn set_mode(&mut self, mode: X86ProcessorMode) {
        self.mode = mode;
    }

    /// Decode a single instruction from the byte slice.
    /// Returns `Some(X86DecodedInstruction)` on success, `None` on failure.
    pub fn decode_one(&mut self, bytes: &[u8]) -> Option<X86DecodedInstruction> {
        self.reset();
        self.bytes = bytes.to_vec();

        if bytes.is_empty() {
            return None;
        }

        // Step 1: Decode all prefixes (legacy, REX, VEX, EVEX)
        if !self.decode_prefixes() {
            return None;
        }

        // Step 2: Decode opcode
        if self.pos >= bytes.len() {
            return None;
        }

        let opcode_byte = self.read_byte()?;
        self.full_opcode.push(opcode_byte);

        // Determine opcode map
        let map = self.determine_map(opcode_byte);

        // Look up instruction in table
        let entry = match map {
            X86OpcodeMap::Primary => {
                self.opcode = opcode_byte as u16;
                self.lookup_primary(opcode_byte)?
            }
            X86OpcodeMap::Map0F => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                self.opcode = op2 as u16;
                self.lookup_0f(op2)?
            }
            X86OpcodeMap::Map0F38 => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                let op3 = self.read_byte()?;
                self.full_opcode.push(op3);
                self.opcode = op3 as u16;
                self.lookup_0f38(op3)?
            }
            X86OpcodeMap::Map0F3A => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                let op3 = self.read_byte()?;
                self.full_opcode.push(op3);
                self.opcode = op3 as u16;
                self.lookup_0f3a(op3)?
            }
            X86OpcodeMap::VexMap1 | X86OpcodeMap::VexMap2 | X86OpcodeMap::VexMap3 => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                self.opcode = op2 as u16;
                self.lookup_vex(op2, &map)?
            }
            X86OpcodeMap::EvexMap1
            | X86OpcodeMap::EvexMap2
            | X86OpcodeMap::EvexMap3
            | X86OpcodeMap::EvexMap4
            | X86OpcodeMap::EvexMap5
            | X86OpcodeMap::EvexMap6 => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                self.opcode = op2 as u16;
                self.lookup_evex(op2, &map)?
            }
            X86OpcodeMap::XopMap8 | X86OpcodeMap::XopMap9 | X86OpcodeMap::XopMapA => {
                let op2 = self.read_byte()?;
                self.full_opcode.push(op2);
                self.opcode = op2 as u16;
                self.lookup_xop(op2, &map)?
            }
            _ => return None,
        };

        // Step 3: Decode ModR/M if needed
        if entry.has_modrm {
            self.modrm = Some(self.decode_modrm()?);
        }

        // Step 4: Decode SIB if needed
        if self.has_sib() {
            self.sib = Some(self.decode_sib()?);
        }

        // Step 5: Decode displacement
        self.decode_displacement()?;

        // Step 6: Decode immediate
        self.decode_immediates(&entry);

        // Step 7: Build the decoded instruction
        let operands = self.build_operands(&entry);
        let size = self.pos;

        let vex_info = self.vex;
        let evex_info = self.evex;

        Some(X86DecodedInstruction {
            mnemonic: entry.mnemonic.to_string(),
            opcode: self.opcode,
            opcode_map: self.opcode_map,
            operands,
            size,
            address: self.base_address,
            prefixes: self.prefixes.clone(),
            rex: self.rex,
            vex: vex_info,
            evex: evex_info,
            implicit_operands: Vec::new(),
            attributes: entry.attributes,
            opcode_extension: self.modrm.map(|m| m.reg_field),
            operand_size: self.prefixes.effective_operand_size,
            address_size: self.prefixes.effective_address_size,
            vector_length: self.determine_vector_length(),
        })
    }

    fn reset(&mut self) {
        self.pos = 0;
        self.bytes.clear();
        self.prefixes = LegacyPrefixInfo::default();
        self.rex = None;
        self.vex = None;
        self.evex = None;
        self.modrm = None;
        self.sib = None;
        self.displacement = 0;
        self.immediates.clear();
        self.opcode = 0;
        self.full_opcode.clear();
        self.opcode_map = X86OpcodeMap::Primary;
    }

    fn read_byte(&mut self) -> Option<u8> {
        if self.pos < self.bytes.len() {
            let b = self.bytes[self.pos];
            self.pos += 1;
            Some(b)
        } else {
            None
        }
    }

    /// Peek at the next byte without consuming it.
    fn peek_byte(&self) -> Option<u8> {
        if self.pos < self.bytes.len() {
            Some(self.bytes[self.pos])
        } else {
            None
        }
    }

    // ---- Prefix Decoding ----

    fn decode_prefixes(&mut self) -> bool {
        let mut has_rex = false;
        let mut has_operand_size = false;
        let mut has_address_size = false;

        // Initialize effective sizes based on mode
        self.prefixes.effective_operand_size = self.mode.default_operand_size();
        self.prefixes.effective_address_size = self.mode.default_address_size();

        loop {
            let b = match self.peek_byte() {
                Some(b) => b,
                None => return false,
            };

            match b {
                // Legacy prefixes
                0xF0 => {
                    if !self.prefixes.has_lock {
                        self.prefixes.has_lock = true;
                        self.read_byte();
                        continue;
                    }
                    // LOCK appearing twice could be an opcode in some contexts
                    break;
                }
                0xF2 => {
                    if !self.prefixes.has_repne {
                        self.prefixes.has_repne = true;
                        self.read_byte();
                        continue;
                    }
                }
                0xF3 => {
                    if !self.prefixes.has_rep {
                        self.prefixes.has_rep = true;
                        self.read_byte();
                        continue;
                    }
                }
                0x2E => {
                    self.prefixes.cs_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::CS);
                    self.read_byte();
                    continue;
                }
                0x3E => {
                    self.prefixes.ds_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::DS);
                    self.read_byte();
                    continue;
                }
                0x36 => {
                    self.prefixes.ss_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::SS);
                    self.read_byte();
                    continue;
                }
                0x26 => {
                    self.prefixes.es_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::ES);
                    self.read_byte();
                    continue;
                }
                0x64 => {
                    self.prefixes.fs_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::FS);
                    self.read_byte();
                    continue;
                }
                0x65 => {
                    self.prefixes.gs_override = true;
                    self.prefixes.active_segment_override = Some(SegmentOverride::GS);
                    self.read_byte();
                    continue;
                }
                0x66 => {
                    if !has_operand_size {
                        has_operand_size = true;
                        self.prefixes.has_operand_size_override = true;
                        // Toggle operand size
                        self.prefixes.effective_operand_size = match self.mode {
                            X86ProcessorMode::Mode16 => 32,
                            X86ProcessorMode::Mode32 => 16,
                            X86ProcessorMode::Mode64 => 16,
                        };
                        self.read_byte();
                        continue;
                    }
                    break;
                }
                0x67 => {
                    if !has_address_size {
                        has_address_size = true;
                        self.prefixes.has_address_size_override = true;
                        // Toggle address size
                        self.prefixes.effective_address_size = match self.mode {
                            X86ProcessorMode::Mode16 => 32,
                            X86ProcessorMode::Mode32 => 16,
                            X86ProcessorMode::Mode64 => 32,
                        };
                        self.read_byte();
                        continue;
                    }
                    break;
                }
                // REX prefix (40-4F in 64-bit mode)
                0x40..=0x4F if self.mode == X86ProcessorMode::Mode64 => {
                    if !has_rex {
                        has_rex = true;
                        let rex_byte = self.read_byte().unwrap();
                        self.decode_rex(rex_byte);
                        self.prefixes.effective_operand_size = if rex_byte & 0x08 != 0 {
                            64
                        } else if has_operand_size {
                            16
                        } else {
                            32
                        };
                        continue;
                    }
                    break;
                }
                // VEX 2-byte prefix (C5 in 32/64-bit mode)
                0xC5 if self.mode != X86ProcessorMode::Mode16 => {
                    // Check next byte to distinguish from LDS
                    if self.pos + 2 < self.bytes.len() {
                        let b2 = self.bytes[self.pos + 1];
                        // VEX.~R = b2[7]; in 64-bit mode, VEX.~R must be 1 unless REX.R used
                        if self.mode == X86ProcessorMode::Mode64 || (b2 & 0x80) == 0x80 {
                            self.read_byte(); // consume C5
                            let vex2 = self.read_byte().unwrap();
                            self.decode_vex_2byte(vex2);
                            continue;
                        }
                    }
                    break;
                }
                // VEX 3-byte prefix (C4 in 32/64-bit mode)
                0xC4 if self.mode != X86ProcessorMode::Mode16 => {
                    // Check next byte to distinguish from LES
                    if self.pos + 2 < self.bytes.len() {
                        let b2 = self.bytes[self.pos + 1];
                        if self.mode == X86ProcessorMode::Mode64 || (b2 & 0x80) == 0x80 {
                            self.read_byte(); // consume C4
                            let vex2 = self.read_byte().unwrap();
                            let vex3 = self.read_byte().unwrap();
                            self.decode_vex_3byte(vex2, vex3);
                            continue;
                        }
                    }
                    break;
                }
                // EVEX prefix (62 in 32/64-bit mode)
                0x62 if self.mode != X86ProcessorMode::Mode16 => {
                    // Check that we have enough bytes and this is actually EVEX
                    if self.pos + 3 < self.bytes.len() {
                        let b2 = self.bytes[self.pos + 1];
                        // EVEX: bits[7:4] of byte 2 must be 0
                        if (b2 & 0xF0) == 0x00 || self.mode == X86ProcessorMode::Mode64 {
                            self.read_byte(); // consume 62
                            let evex2 = self.read_byte().unwrap();
                            let evex3 = self.read_byte().unwrap();
                            let evex4 = self.read_byte().unwrap();
                            self.decode_evex_full(evex2, evex3, evex4);
                            continue;
                        }
                    }
                    break;
                }
                _ => break,
            }
        }

        true
    }

    fn decode_rex(&mut self, rex_byte: u8) {
        let rex = RexInfo {
            present: true,
            w: (rex_byte & 0x08) != 0,
            r: (rex_byte & 0x04) != 0,
            x: (rex_byte & 0x02) != 0,
            b: (rex_byte & 0x01) != 0,
        };
        self.rex = Some(rex);
    }

    fn decode_vex_2byte(&mut self, vex2: u8) {
        // 2-byte VEX: [C5] [R vvvv L pp]
        // Byte 2: bits[7] = ~R, bits[6:3] = ~vvvv, bit[2] = L, bits[1:0] = pp
        let r = (vex2 & 0x80) == 0; // ~R (inverted)
        let vvvv = ((vex2 >> 3) & 0x0F) ^ 0x0F; // ~vvvv (inverted)
        let l = (vex2 & 0x04) != 0;
        let pp = vex2 & 0x03;

        let info = VexDecodedInfo {
            present: true,
            is_3byte: false,
            r,
            x: true,  // ~X = 1 for 2-byte VEX
            b: true,  // ~B = 1 for 2-byte VEX
            w: false, // W not present in 2-byte VEX
            vvvv,
            l,
            pp,
            mmmmm: 1, // Implied 0F map
        };
        self.vex = Some(info);
    }

    fn decode_vex_3byte(&mut self, vex2: u8, vex3: u8) {
        // 3-byte VEX: [C4] [~R ~X ~B mmmmm] [W ~vvvv L pp]
        // Byte 2: bits[7] = ~R, bits[6] = ~X, bits[5] = ~B, bits[4:0] = mmmmm
        // Byte 3: bits[7] = W, bits[6:3] = ~vvvv, bit[2] = L, bits[1:0] = pp
        let r = (vex2 & 0x80) == 0;
        let x = (vex2 & 0x40) == 0;
        let b = (vex2 & 0x20) == 0;
        let mmmmm = vex2 & 0x1F;
        let w = (vex3 & 0x80) != 0;
        let vvvv = ((vex3 >> 3) & 0x0F) ^ 0x0F;
        let l = (vex3 & 0x04) != 0;
        let pp = vex3 & 0x03;

        let info = VexDecodedInfo {
            present: true,
            is_3byte: true,
            r,
            x,
            b,
            w,
            vvvv,
            l,
            pp,
            mmmmm,
        };

        // Determine map from mmmmm
        match mmmmm {
            0x01 => self.opcode_map = X86OpcodeMap::VexMap1,
            0x02 => self.opcode_map = X86OpcodeMap::VexMap2,
            0x03 => self.opcode_map = X86OpcodeMap::VexMap3,
            0x08..=0x0A => {
                self.opcode_map = match mmmmm {
                    0x08 => X86OpcodeMap::XopMap8,
                    0x09 => X86OpcodeMap::XopMap9,
                    0x0A => X86OpcodeMap::XopMapA,
                    _ => X86OpcodeMap::Primary,
                };
            }
            _ => {
                // 2-byte VEX implies mmmmm = 00001
                self.opcode_map = X86OpcodeMap::VexMap1;
            }
        }

        self.vex = Some(info);
    }

    fn decode_evex_full(&mut self, evex2: u8, evex3: u8, evex4: u8) {
        // EVEX: [62] [P1 P0] [P2] [P3]
        // P1 (evex2): bits[7:4] = must be 0 (reserved), bits[3] = R', bit[2] = B', bit[1] = R, bit[0] = 00mm (top 2 bits of mm)
        // Actually P1: [7]=R', [6]=X', [5]=B', [4]=R', [3]=00/R', [2]=mm[4], [1]=mm[3], [0]=mm[2]
        // Let me use the standard Intel encoding:
        // Byte 2 (P0): [7] = R/X/B/R' or...
        // Let's use the standard layout:
        // Byte 1 (P0): 0xF0 mask check passed. bits[7:4]=~R,~X,~B,~R' | bits[3:0]=mmmm
        // Byte 2 (P1): bits[7]=W, bits[6]=~vvvv[3], bits[5:2]=~vvvv[2:0]?, bits[3:0]=pp
        // Byte 3 (P2): bits[7]=z, bits[6:5]=L', bits[4]=b, bits[3:1]=V', bits[0]=aaa[0]? no.

        // Using actual Intel EVEX encoding:
        // P0 (byte after 62): [7]=~R, [6]=~X, [5]=~B, [4]=~R', [3:0]=mmmm
        // P1 (next byte):    [7]=W, [6]=~vvvv[3], [5]=1's?, [4]=~vvvv[1]? no.
        // Actually:
        // P1: [7]=W, [6:3]=~vvvv, [2]=1/pp[1]? no.
        // Let me use the LLVM-style decoding:
        // EVEX.P0: bits[7:4] = ~R ~X ~B ~R'
        // EVEX.P0: bits[3:0] = mm[3:0]
        // EVEX.P1: bits[7] = W, bits[6:3] = ~vvvv, bit[2] = pp[1]? Actually pp is in bits[1:0] of P1.
        // EVEX.P1: bits[7]=W, bits[6:3]=~vvvv, bit[2]=pp[1]? Let me use:
        // P1: bits[7]=W, bits[6:3]=~vvvv, bits[2:0]=???
        // P1: [7]=W, [6]=~vvvv[3], [5]=~vvvv[2], [4]=~vvvv[1], [3]=~vvvv[0], [2]=1's, [1:0]=pp
        // P2: [7]=z, [6]=L', [5]=b, [4]=V', [3:0]=aaa
        // Wait, the EVEX encoding is actually:
        // Byte 0: 0x62
        // Byte 1 (P0): [7]=~R, [6]=~X, [5]=~B, [4]=~R', [3:0]=mmmm
        // Byte 2 (P1): [7]=W, [6:3]=~vvvv, [2]=1 (fixed), [1:0]=pp
        // Byte 3 (P2): [7]=z, [6:5]=L'L, [4]=b, [3]=V', [2:0]=aaa

        let r = (evex2 & 0x80) == 0;
        let x = (evex2 & 0x40) == 0;
        let b = (evex2 & 0x20) == 0;
        let r_prime = (evex2 & 0x10) == 0;
        let mm = evex2 & 0x0F;

        let w = (evex3 & 0x80) != 0;
        let vvvv = ((evex3 >> 3) & 0x0F) ^ 0x0F;
        let pp = evex3 & 0x03;
        // Check bit 2 of evex3 is 1 (validity check)
        if (evex3 & 0x04) == 0 {
            // Invalid EVEX encoding
            return;
        }

        let z = (evex4 & 0x80) != 0;
        let ll = (evex4 >> 5) & 0x03;
        let b_bit = (evex4 & 0x10) != 0;
        let v_prime = (evex4 & 0x08) != 0;
        let aaa = evex4 & 0x07;

        let info = EvexDecodedInfo {
            present: true,
            r_prime,
            x_prime: false, // EVEX.X' is same position as B' in some contexts
            b_prime: false,
            r,
            x,
            b,
            v_prime,
            w,
            z,
            aaa,
            ll,
            b_bit,
            pp,
            mm,
            vvvv,
        };

        // Determine map from mm
        self.opcode_map = match mm {
            0x01 => X86OpcodeMap::EvexMap1,
            0x02 => X86OpcodeMap::EvexMap2,
            0x03 => X86OpcodeMap::EvexMap3,
            0x04 => X86OpcodeMap::EvexMap4,
            0x05 => X86OpcodeMap::EvexMap5,
            0x06 => X86OpcodeMap::EvexMap6,
            _ => X86OpcodeMap::Primary,
        };

        self.evex = Some(info);
    }

    // ---- Opcode Map Determination ----

    fn determine_map(&self, opcode: u8) -> X86OpcodeMap {
        // Check if we have VEX or EVEX prefix
        if self.evex.is_some() {
            return self.opcode_map;
        }
        if self.vex.is_some() {
            return self.opcode_map;
        }

        // Legacy encoding: check for escape sequences
        match opcode {
            0x0F => {
                // Read next byte to determine 0F xx vs 0F 38 xx vs 0F 3A xx
                if self.pos < self.bytes.len() {
                    match self.bytes[self.pos] {
                        0x38 => X86OpcodeMap::Map0F38,
                        0x3A => X86OpcodeMap::Map0F3A,
                        _ => X86OpcodeMap::Map0F,
                    }
                } else {
                    X86OpcodeMap::Map0F
                }
            }
            _ => X86OpcodeMap::Primary,
        }
    }

    // ---- ModR/M & SIB Decoding ----

    fn decode_modrm(&mut self) -> Option<ModRMDecoded> {
        let raw = self.read_byte()?;
        Some(ModRMDecoded {
            raw,
            mod_field: (raw >> 6) & 0x03,
            reg_field: (raw >> 3) & 0x07,
            rm_field: raw & 0x07,
        })
    }

    fn has_sib(&self) -> bool {
        if let Some(modrm) = self.modrm {
            // SIB is used when Mod != 11 and R/M == 100
            // In 16-bit addressing, there is no SIB
            // But in 32/64-bit, R/M == 100 is the SIB escape
            if self.prefixes.effective_address_size >= 32 {
                modrm.mod_field != 3 && modrm.rm_field == 4
            } else {
                false
            }
        } else {
            false
        }
    }

    fn decode_sib(&mut self) -> Option<SIBDecoded> {
        let raw = self.read_byte()?;
        Some(SIBDecoded {
            raw,
            scale: (raw >> 6) & 0x03,
            index_field: (raw >> 3) & 0x07,
            base_field: raw & 0x07,
        })
    }

    // ---- Displacement Decoding ----

    fn decode_displacement(&mut self) -> Option<()> {
        if let Some(modrm) = self.modrm {
            let mod_field = modrm.mod_field;
            let rm_field = modrm.rm_field;
            let addr_size = self.prefixes.effective_address_size;

            match mod_field {
                0 => {
                    // No displacement, except special cases
                    if addr_size == 16 {
                        if rm_field == 6 {
                            // [disp16] in 16-bit mode
                            self.displacement = self.read_i16()? as i64;
                        }
                    } else if rm_field == 5 {
                        // [disp32] in 32/64-bit mode (or RIP-relative in 64-bit)
                        self.displacement = self.read_i32()? as i64;
                    }
                }
                1 => {
                    // disp8
                    self.displacement = self.read_i8()? as i64;
                }
                2 => {
                    // disp16 or disp32 depending on address size
                    if addr_size == 16 {
                        self.displacement = self.read_i16()? as i64;
                    } else {
                        self.displacement = self.read_i32()? as i64;
                    }
                }
                3 => {
                    // Register-direct mode, no displacement
                }
                _ => {}
            }
        }
        Some(())
    }

    // ---- Immediate Decoding ----

    fn decode_immediates(&mut self, entry: &InstrTableEntry) {
        if entry.imm_size == 0 {
            return;
        }

        // For group instructions, imm_size may be overridden
        let mut imm_size = entry.imm_size;

        // For instructions with operand-size affected immediates
        match entry.encoding_form {
            InstrEncodingForm::AccumImm
            | InstrEncodingForm::RegImm
            | InstrEncodingForm::RmImm
            | InstrEncodingForm::RmRegImm
            | InstrEncodingForm::RmRegImmModRM => {
                // If operand size override is active, imm_size may change
                let oper_size = self.prefixes.effective_operand_size;
                if self.rex.as_ref().map_or(false, |r| r.w) {
                    imm_size = 8;
                } else if imm_size == 0 {
                    // Infer from operand size
                    imm_size = (oper_size / 8) as u8;
                }
            }
            InstrEncodingForm::RelBranch => {
                imm_size = imm_size.max(1);
            }
            _ => {}
        }

        let value = match imm_size {
            1 => self.read_i8().unwrap_or(0) as i64,
            2 => self.read_i16().unwrap_or(0) as i64,
            4 => self.read_i32().unwrap_or(0) as i64,
            8 => self.read_i64().unwrap_or(0),
            _ => return,
        };

        self.immediates.push(value);
    }

    fn read_i8(&mut self) -> Option<i8> {
        Some(self.read_byte()? as i8)
    }

    fn read_i16(&mut self) -> Option<i16> {
        let lo = self.read_byte()? as u16;
        let hi = self.read_byte()? as u16;
        Some((lo | (hi << 8)) as i16)
    }

    fn read_i32(&mut self) -> Option<i32> {
        let b0 = self.read_byte()? as u32;
        let b1 = self.read_byte()? as u32;
        let b2 = self.read_byte()? as u32;
        let b3 = self.read_byte()? as u32;
        Some((b0 | (b1 << 8) | (b2 << 16) | (b3 << 24)) as i32)
    }

    fn read_i64(&mut self) -> Option<i64> {
        let b0 = self.read_byte()? as u64;
        let b1 = self.read_byte()? as u64;
        let b2 = self.read_byte()? as u64;
        let b3 = self.read_byte()? as u64;
        let b4 = self.read_byte()? as u64;
        let b5 = self.read_byte()? as u64;
        let b6 = self.read_byte()? as u64;
        let b7 = self.read_byte()? as u64;
        Some(
            (b0 | (b1 << 8)
                | (b2 << 16)
                | (b3 << 24)
                | (b4 << 32)
                | (b5 << 40)
                | (b6 << 48)
                | (b7 << 56)) as i64,
        )
    }

    // ---- Operand Building ----

    fn build_operands(&self, entry: &InstrTableEntry) -> Vec<X86DecodedOperand> {
        let mut operands = Vec::new();

        match entry.encoding_form {
            InstrEncodingForm::Implicit => {
                // No explicit operands
            }
            InstrEncodingForm::RegOnly => {
                // Opcode encodes register in low 3 bits
                let reg = self.opcode_reg_from_bits(self.opcode as u8 & 0x07);
                operands.push(reg);
            }
            InstrEncodingForm::AccumImm => {
                let acc = self.accumulator_reg();
                operands.push(acc);
                if let Some(&imm) = self.immediates.first() {
                    operands.push(X86DecodedOperand::Immediate {
                        value: imm,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::AccumMem => {
                let acc = self.accumulator_reg();
                operands.push(acc);
                // Memory operand at absolute address
                let addr = self.displacement;
                operands.push(self.make_absolute_memory(addr, entry.att_size_hint));
            }
            InstrEncodingForm::MemAccum => {
                let addr = self.displacement;
                operands.push(self.make_absolute_memory(addr, entry.att_size_hint));
                operands.push(self.accumulator_reg());
            }
            InstrEncodingForm::RegRM | InstrEncodingForm::RmReg => {
                if let Some(modrm) = self.modrm {
                    let reg = self.resolve_reg(modrm.reg_field);
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    if matches!(entry.encoding_form, InstrEncodingForm::RegRM) {
                        operands.push(reg);
                        operands.push(rm);
                    } else {
                        operands.push(rm);
                        operands.push(reg);
                    }
                }
            }
            InstrEncodingForm::OpcodeExtRM => {
                if let Some(modrm) = self.modrm {
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(rm);
                }
            }
            InstrEncodingForm::RmOnly => {
                if let Some(modrm) = self.modrm {
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(rm);
                }
            }
            InstrEncodingForm::RegImm => {
                if let Some(modrm) = self.modrm {
                    let reg = self.resolve_reg(modrm.reg_field);
                    operands.push(reg);
                }
                if let Some(&imm) = self.immediates.first() {
                    operands.push(X86DecodedOperand::Immediate {
                        value: imm,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::RmImm => {
                if let Some(modrm) = self.modrm {
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(rm);
                }
                if let Some(&imm) = self.immediates.first() {
                    operands.push(X86DecodedOperand::Immediate {
                        value: imm,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::RmRegImm | InstrEncodingForm::RmRegImmModRM => {
                if let Some(modrm) = self.modrm {
                    let reg = self.resolve_reg(modrm.reg_field);
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    if matches!(entry.encoding_form, InstrEncodingForm::RmRegImm) {
                        operands.push(rm);
                        operands.push(reg);
                    } else {
                        operands.push(rm);
                        operands.push(reg);
                    }
                }
                if let Some(&imm) = self.immediates.first() {
                    operands.push(X86DecodedOperand::Immediate {
                        value: imm,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::RelBranch => {
                if let Some(&offset) = self.immediates.first() {
                    operands.push(X86DecodedOperand::RelativeOffset {
                        offset,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::VexRegVvvvRm => {
                // reg (from ModR/M.reg), vvvv, rm
                if let Some(modrm) = self.modrm {
                    let reg = self.resolve_vex_reg(modrm.reg_field);
                    let vvvv_reg = self.resolve_vvvv_reg();
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(reg);
                    operands.push(vvvv_reg);
                    operands.push(rm);
                }
            }
            InstrEncodingForm::VexVvvvRmReg => {
                // vvvv, rm, reg
                if let Some(modrm) = self.modrm {
                    let vvvv_reg = self.resolve_vvvv_reg();
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    let reg = self.resolve_vex_reg(modrm.reg_field);
                    operands.push(vvvv_reg);
                    operands.push(rm);
                    operands.push(reg);
                }
            }
            InstrEncodingForm::VexVvvvRmImm => {
                if let Some(modrm) = self.modrm {
                    let vvvv_reg = self.resolve_vvvv_reg();
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(vvvv_reg);
                    operands.push(rm);
                }
                if let Some(&imm) = self.immediates.first() {
                    operands.push(X86DecodedOperand::Immediate {
                        value: imm,
                        size: entry.imm_size,
                    });
                }
            }
            InstrEncodingForm::VexRmReg => {
                if let Some(modrm) = self.modrm {
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    let reg = self.resolve_vex_reg(modrm.reg_field);
                    operands.push(rm);
                    operands.push(reg);
                }
            }
            InstrEncodingForm::EvexRegKRm => {
                if let Some(modrm) = self.modrm {
                    let reg = self.resolve_evex_reg(modrm.reg_field);
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    // Add opmask if present
                    if let Some(ref evex) = self.evex {
                        if evex.aaa > 0 {
                            let kreg = self.opmask_reg_from_bits(evex.aaa);
                            operands.push(X86DecodedOperand::OpmaskRegister {
                                reg: kreg,
                                zeroing: evex.z,
                            });
                        }
                    }
                    operands.push(reg);
                    operands.push(rm);
                }
            }
            InstrEncodingForm::EvexVvvvKRmReg => {
                if let Some(modrm) = self.modrm {
                    let vvvv_reg = self.resolve_vvvv_reg();
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    let reg = self.resolve_evex_reg(modrm.reg_field);
                    // Add opmask if present
                    if let Some(ref evex) = self.evex {
                        if evex.aaa > 0 {
                            let kreg = self.opmask_reg_from_bits(evex.aaa);
                            operands.push(X86DecodedOperand::OpmaskRegister {
                                reg: kreg,
                                zeroing: evex.z,
                            });
                        }
                    }
                    operands.push(vvvv_reg);
                    operands.push(rm);
                    operands.push(reg);
                }
            }
            InstrEncodingForm::GroupOpcodeExt => {
                // Opcode extension from ModR/M reg field determines the actual mnemonic
                // The operands depend on the group
                if let Some(modrm) = self.modrm {
                    let rm = self.resolve_rm_operand(modrm, entry.att_size_hint);
                    operands.push(rm);
                    if let Some(&imm) = self.immediates.first() {
                        operands.push(X86DecodedOperand::Immediate {
                            value: imm,
                            size: entry.imm_size,
                        });
                    }
                }
            }
            _ => {} // Catch-all for encoding forms with default operand handling
        }

        operands
    }

    fn resolve_reg(&self, reg_field: u8) -> X86DecodedOperand {
        let extended_reg = self.extend_reg(reg_field);
        let reg_name = self.gpr_name_for_size(extended_reg);
        let size_hint = self.size_hint_for_gpr();
        X86DecodedOperand::Register {
            reg: reg_name,
            size_hint,
        }
    }

    fn resolve_vex_reg(&self, reg_field: u8) -> X86DecodedOperand {
        let extended_reg = self.extend_vex_reg(reg_field);
        let reg_name = self.vector_reg_name(extended_reg);
        let size_hint = self.vector_size_hint();
        X86DecodedOperand::Register {
            reg: reg_name,
            size_hint,
        }
    }

    fn resolve_evex_reg(&self, reg_field: u8) -> X86DecodedOperand {
        let extended_reg = self.extend_evex_reg(reg_field);
        let reg_name = self.vector_reg_name(extended_reg);
        let size_hint = self.vector_size_hint();
        X86DecodedOperand::Register {
            reg: reg_name,
            size_hint,
        }
    }

    fn resolve_vvvv_reg(&self) -> X86DecodedOperand {
        let vvvv = if let Some(ref vex) = self.vex {
            vex.vvvv
        } else if let Some(ref evex) = self.evex {
            evex.vvvv
        } else {
            0
        };
        let reg_name = self.vector_reg_name(vvvv);
        let size_hint = self.vector_size_hint();
        X86DecodedOperand::Register {
            reg: reg_name,
            size_hint,
        }
    }

    fn resolve_rm_operand(
        &self,
        modrm: ModRMDecoded,
        size_hint: OperandSizeHint,
    ) -> X86DecodedOperand {
        if modrm.mod_field == 3 {
            // Register-direct mode
            let extended_rm = self.extend_rm(modrm.rm_field);
            let reg_name = self.gpr_name_for_size(extended_rm);
            X86DecodedOperand::Register {
                reg: reg_name,
                size_hint,
            }
        } else {
            // Memory addressing mode
            self.resolve_memory_operand(modrm, size_hint)
        }
    }

    fn resolve_memory_operand(
        &self,
        modrm: ModRMDecoded,
        size_hint: OperandSizeHint,
    ) -> X86DecodedOperand {
        let addr_size = self.prefixes.effective_address_size;
        let segment = self.prefixes.active_segment_override;
        let disp = self.displacement;

        if addr_size == 16 {
            // 16-bit addressing modes
            let (base, index) = match modrm.rm_field {
                0 => (Some(X86RegName::BX), Some((X86RegName::SI, 1u8))),
                1 => (Some(X86RegName::BX), Some((X86RegName::DI, 1u8))),
                2 => (Some(X86RegName::BP), Some((X86RegName::SI, 1u8))),
                3 => (Some(X86RegName::BP), Some((X86RegName::DI, 1u8))),
                4 => (Some(X86RegName::SI), None),
                5 => (Some(X86RegName::DI), None),
                6 => {
                    if modrm.mod_field == 0 {
                        // Direct address [disp16]
                        (None, None)
                    } else {
                        (Some(X86RegName::BP), None)
                    }
                }
                7 => (Some(X86RegName::BX), None),
                _ => (None, None),
            };

            X86DecodedOperand::Memory {
                segment,
                base,
                index,
                displacement: disp,
                size_hint,
                rip_relative: false,
            }
        } else {
            // 32-bit or 64-bit addressing modes
            let mut base_reg: Option<X86RegName> = None;
            let mut index_reg: Option<(X86RegName, u8)> = None;
            let mut rip_rel = false;

            if let Some(sib) = self.sib {
                // SIB byte present (RM=100 and Mod!=11)
                let scale = match sib.scale {
                    0 => 1,
                    1 => 2,
                    2 => 4,
                    3 => 8,
                    _ => 1,
                };

                // Base register (unless base=101 and mod=00 => no base with disp32)
                if sib.base_field != 5 || modrm.mod_field != 0 {
                    let extended_base = self.extend_base(sib.base_field);
                    base_reg = Some(self.base_reg_name(extended_base));
                } else if modrm.mod_field == 0 && addr_size == 64 {
                    // RIP-relative addressing (Mod=00, RM=101, no SIB? Actually in 64-bit mode,
                    // Mod=00 RM=101 means RIP-relative; with SIB, Mod=00 Base=101 means disp32 no base)
                    // Wait: In 64-bit mode, Mod=00 RM=101 is RIP-relative if no SIB.
                    // With SIB, base=101, mod=00 means no-base with disp32.
                    rip_rel = false;
                }

                // Index register (unless index=100 => no index)
                if sib.index_field != 4 {
                    let extended_index = self.extend_index(sib.index_field);
                    let idx_name = self.index_reg_name(extended_index);
                    index_reg = Some((idx_name, scale));
                }
            } else {
                // No SIB: direct base register in RM field
                if addr_size == 64 && modrm.mod_field == 0 && modrm.rm_field == 5 {
                    // RIP-relative
                    rip_rel = true;
                    base_reg = None;
                } else {
                    let extended_rm = self.extend_rm(modrm.rm_field);
                    base_reg = Some(self.base_reg_name(extended_rm));
                }
            }

            X86DecodedOperand::Memory {
                segment,
                base: base_reg,
                index: index_reg,
                displacement: disp,
                size_hint,
                rip_relative: rip_rel,
            }
        }
    }

    fn make_absolute_memory(&self, address: i64, size_hint: OperandSizeHint) -> X86DecodedOperand {
        X86DecodedOperand::Memory {
            segment: self.prefixes.active_segment_override,
            base: None,
            index: None,
            displacement: address,
            size_hint,
            rip_relative: false,
        }
    }

    // ---- Register Resolution Helpers ----

    fn extend_reg(&self, reg: u8) -> u8 {
        let mut r = reg;
        if let Some(rex) = self.rex {
            if rex.r {
                r |= 0x08;
            }
        }
        r
    }

    fn extend_rm(&self, rm: u8) -> u8 {
        let mut r = rm;
        if let Some(rex) = self.rex {
            if rex.b {
                r |= 0x08;
            }
        }
        r
    }

    fn extend_base(&self, base: u8) -> u8 {
        let mut r = base;
        if let Some(rex) = self.rex {
            if rex.b {
                r |= 0x08;
            }
        }
        r
    }

    fn extend_index(&self, index: u8) -> u8 {
        let mut r = index;
        if let Some(rex) = self.rex {
            if rex.x {
                r |= 0x08;
            }
        }
        r
    }

    fn extend_vex_reg(&self, reg: u8) -> u8 {
        let mut r = reg;
        if let Some(ref vex) = self.vex {
            if vex.r {
                r |= 0x08;
            }
            if vex.b {
                r |= 0x10;
            }
        }
        r
    }

    fn extend_evex_reg(&self, reg: u8) -> u8 {
        let mut r = reg;
        if let Some(ref evex) = self.evex {
            if evex.r {
                r |= 0x08;
            }
            if evex.r_prime {
                r |= 0x10;
            }
            if evex.b {
                r |= 0x08; // Actually overlaps with R but EVEX has separate R'
            }
        }
        r
    }

    fn gpr_name_for_size(&self, reg_id: u8) -> X86RegName {
        let oper_size = self.prefixes.effective_operand_size;
        let is_64bit = self.mode == X86ProcessorMode::Mode64;

        match oper_size {
            8 => gpr8_name(reg_id, self.rex.as_ref()),
            16 => gpr16_name(reg_id),
            32 => gpr32_name(reg_id),
            64 if is_64bit => gpr64_name(reg_id),
            64 => gpr32_name(reg_id),
            _ => gpr32_name(reg_id),
        }
    }

    fn base_reg_name(&self, reg_id: u8) -> X86RegName {
        let addr_size = self.prefixes.effective_address_size;
        match addr_size {
            64 => gpr64_name(reg_id),
            32 => gpr32_name(reg_id),
            _ => gpr16_name(reg_id),
        }
    }

    fn index_reg_name(&self, reg_id: u8) -> X86RegName {
        let addr_size = self.prefixes.effective_address_size;
        match addr_size {
            64 => gpr64_name(reg_id),
            32 => gpr32_name(reg_id),
            _ => gpr16_name(reg_id),
        }
    }

    fn accumulator_reg(&self) -> X86DecodedOperand {
        let oper_size = self.prefixes.effective_operand_size;
        let reg = match oper_size {
            8 => X86RegName::AL,
            16 => X86RegName::AX,
            32 => X86RegName::EAX,
            64 => X86RegName::RAX,
            _ => X86RegName::EAX,
        };
        X86DecodedOperand::ImplicitRegister { reg }
    }

    fn opcode_reg_from_bits(&self, bits: u8) -> X86DecodedOperand {
        let mut reg_id = bits;
        if let Some(rex) = self.rex {
            if rex.b {
                reg_id |= 0x08;
            }
        }
        let reg = self.gpr_name_for_size(reg_id);
        X86DecodedOperand::Register {
            reg,
            size_hint: self.size_hint_for_gpr(),
        }
    }

    fn vector_reg_name(&self, reg_id: u8) -> X86RegName {
        // Determine if we need XMM, YMM, or ZMM based on vector length
        let vec_len = self.determine_vector_length();
        match vec_len {
            512 => zmm_name(reg_id),
            256 => ymm_name(reg_id),
            _ => xmm_name(reg_id),
        }
    }

    fn opmask_reg_from_bits(&self, bits: u8) -> X86RegName {
        match bits {
            0 => X86RegName::K0,
            1 => X86RegName::K1,
            2 => X86RegName::K2,
            3 => X86RegName::K3,
            4 => X86RegName::K4,
            5 => X86RegName::K5,
            6 => X86RegName::K6,
            _ => X86RegName::K7,
        }
    }

    fn size_hint_for_gpr(&self) -> OperandSizeHint {
        let oper_size = self.prefixes.effective_operand_size;
        if self.rex.as_ref().map_or(false, |r| r.w) {
            OperandSizeHint::Qword
        } else {
            match oper_size {
                8 => OperandSizeHint::Byte,
                16 => OperandSizeHint::Word,
                32 => OperandSizeHint::Dword,
                64 => OperandSizeHint::Qword,
                _ => OperandSizeHint::Dword,
            }
        }
    }

    fn vector_size_hint(&self) -> OperandSizeHint {
        let vec_len = self.determine_vector_length();
        match vec_len {
            512 => OperandSizeHint::Zword,
            256 => OperandSizeHint::Yword,
            _ => OperandSizeHint::Oword,
        }
    }

    fn determine_vector_length(&self) -> u16 {
        if let Some(ref evex) = self.evex {
            match evex.ll {
                0 => 128,
                1 => 256,
                2 => 512,
                _ => 128,
            }
        } else if let Some(ref vex) = self.vex {
            if vex.l {
                256
            } else {
                128
            }
        } else {
            0
        }
    }

    // ---- Opcode Lookup Functions ----

    fn lookup_primary(&self, opcode: u8) -> Option<InstrTableEntry> {
        primary_opcode_table()
            .into_iter()
            .find(|e| e.opcode == opcode as u16)
    }

    fn lookup_0f(&self, opcode: u8) -> Option<InstrTableEntry> {
        opcode_table_0f()
            .into_iter()
            .find(|e| e.opcode == opcode as u16)
    }

    fn lookup_0f38(&self, opcode: u8) -> Option<InstrTableEntry> {
        opcode_table_0f38()
            .into_iter()
            .find(|e| e.opcode == opcode as u16)
    }

    fn lookup_0f3a(&self, opcode: u8) -> Option<InstrTableEntry> {
        opcode_table_0f3a()
            .into_iter()
            .find(|e| e.opcode == opcode as u16)
    }

    fn lookup_vex(&self, opcode: u8, map: &X86OpcodeMap) -> Option<InstrTableEntry> {
        let table = match map {
            X86OpcodeMap::VexMap1 => vex_opcode_table_1(),
            X86OpcodeMap::VexMap2 => vex_opcode_table_2(),
            X86OpcodeMap::VexMap3 => vex_opcode_table_3(),
            _ => return None,
        };
        table.into_iter().find(|e| e.opcode == opcode as u16)
    }

    fn lookup_evex(&self, opcode: u8, map: &X86OpcodeMap) -> Option<InstrTableEntry> {
        let table = match map {
            X86OpcodeMap::EvexMap1 => evex_opcode_table_1(),
            X86OpcodeMap::EvexMap2 => evex_opcode_table_2(),
            X86OpcodeMap::EvexMap3 => evex_opcode_table_3(),
            X86OpcodeMap::EvexMap4 => evex_opcode_table_4(),
            X86OpcodeMap::EvexMap5 => evex_opcode_table_5(),
            X86OpcodeMap::EvexMap6 => evex_opcode_table_6(),
            _ => return None,
        };
        table.into_iter().find(|e| e.opcode == opcode as u16)
    }

    fn lookup_xop(&self, opcode: u8, map: &X86OpcodeMap) -> Option<InstrTableEntry> {
        let table = match map {
            X86OpcodeMap::XopMap8 => xop_opcode_table_8(),
            X86OpcodeMap::XopMap9 => xop_opcode_table_9(),
            X86OpcodeMap::XopMapA => xop_opcode_table_a(),
            _ => return None,
        };
        table.into_iter().find(|e| e.opcode == opcode as u16)
    }
}

// ============================================================================
// X86InstructionPrinter — Instruction Formatting
// ============================================================================

/// Formats decoded X86 instructions into human-readable assembly strings.
///
/// Supports AT&T syntax, Intel syntax, and annotated output with byte offsets.
pub struct X86InstructionPrinter {
    syntax: DisassemblerSyntax,
}

impl X86InstructionPrinter {
    pub fn new(syntax: DisassemblerSyntax) -> Self {
        X86InstructionPrinter { syntax }
    }

    pub fn set_syntax(&mut self, syntax: DisassemblerSyntax) {
        self.syntax = syntax;
    }

    /// Format a decoded instruction into a string.
    /// `show_bytes` prepends the raw bytes.
    /// `raw_bytes` is the original byte slice for byte display.
    pub fn format(
        &self,
        inst: &X86DecodedInstruction,
        show_bytes: bool,
        raw_bytes: &[u8],
    ) -> String {
        let mut result = String::new();

        // Optional byte offset display
        if show_bytes {
            result.push_str(&format!("{:08x}: ", inst.address));
            for i in 0..inst.size.min(raw_bytes.len()) {
                result.push_str(&format!("{:02x} ", raw_bytes[i]));
            }
            // Pad to align
            let padding = (15usize.saturating_sub(inst.size)) * 3;
            for _ in 0..padding {
                result.push(' ');
            }
            result.push('\t');
        } else {
            result.push('\t');
        }

        match self.syntax {
            DisassemblerSyntax::Intel => {
                result.push_str(&self.format_intel(inst));
            }
            DisassemblerSyntax::Att => {
                result.push_str(&self.format_att(inst));
            }
            DisassemblerSyntax::Annotated => {
                result.push_str(&format!("0x{:x}: ", inst.address));
                result.push_str(&self.format_intel(inst));
            }
        }

        result
    }

    fn format_intel(&self, inst: &X86DecodedInstruction) -> String {
        let mut s = inst.mnemonic.clone();

        // Add AVX-512 decorators
        if let Some(ref evex) = inst.evex {
            if evex.aaa > 0 && inst.attributes.uses_opmask {
                s.push_str(&format!(" {{k{}}}", evex.aaa));
                if evex.z {
                    s.push_str("{z}");
                }
            }
        }

        if !inst.operands.is_empty() {
            s.push(' ');
            let parts: Vec<String> = inst
                .operands
                .iter()
                .map(|op| self.format_operand_intel(op, inst))
                .collect();
            s.push_str(&parts.join(", "));
        }

        // Add size hint for memory-only operands (Intel syntax)
        // This is context-dependent; for ambiguity resolution

        s
    }

    fn format_att(&self, inst: &X86DecodedInstruction) -> String {
        // AT&T: add suffix to mnemonic
        let mut mnem = inst.mnemonic.clone();

        // Add size suffix
        let suffix = if let Some(first_op) = inst.operands.first() {
            match first_op {
                X86DecodedOperand::Register { size_hint, .. } => size_hint.att_suffix(),
                X86DecodedOperand::Memory { size_hint, .. } => size_hint.att_suffix(),
                X86DecodedOperand::Immediate { size, .. } => match size {
                    1 => "b",
                    2 => "w",
                    4 => "l",
                    8 => "q",
                    _ => "",
                },
                _ => "",
            }
        } else {
            ""
        };

        // Don't add suffix for certain mnemonics (jmp, call, etc.)
        if !mnem.contains('.')
            && !mnem.starts_with('j')
            && !mnem.starts_with("call")
            && !mnem.starts_with("ret")
            && !mnem.starts_with("sys")
            && !mnem.starts_with("loop")
            && suffix != ""
        {
            if !mnem.ends_with(suffix) {
                mnem.push_str(suffix);
            }
        }

        // Add AVX-512 decorators
        if let Some(ref evex) = inst.evex {
            if evex.aaa > 0 && inst.attributes.uses_opmask {
                mnem.push_str(&format!(" {{k{}}}", evex.aaa));
                if evex.z {
                    mnem.push_str("{z}");
                }
            }
        }

        if !inst.operands.is_empty() {
            let parts: Vec<String> = inst
                .operands
                .iter()
                .map(|op| self.format_operand_att(op, inst))
                .collect();
            // AT&T: source, destination order (reversed from Intel)
            // But our operands are already in source, dest order for Intel.
            // For AT&T we need to reverse. However, many instructions store
            // operands differently. Let's keep operand order as-is but the
            // format_operand_att uses % prefix.
            mnem.push(' ');
            mnem.push_str(&parts.join(", "));
        }

        // Lock/rep prefixes in AT&T
        if inst.attributes.has_lock_prefix {
            mnem = format!("lock {}", mnem);
        }
        if inst.attributes.has_rep_prefix {
            mnem = format!("rep {}", mnem);
        }
        if inst.attributes.has_repne_prefix {
            mnem = format!("repne {}", mnem);
        }

        mnem
    }

    fn format_operand_intel(&self, op: &X86DecodedOperand, inst: &X86DecodedInstruction) -> String {
        match op {
            X86DecodedOperand::Register { reg, size_hint: _ } => reg.name().to_string(),
            X86DecodedOperand::Memory {
                segment: _,
                base,
                index,
                displacement,
                size_hint,
                rip_relative,
            } => {
                let mut s = String::new();

                if *rip_relative {
                    // RIP-relative
                    if *displacement < 0 {
                        s.push_str(&format!("[rip - 0x{:x}]", displacement.unsigned_abs()));
                    } else if *displacement == 0 {
                        s.push_str("[rip]");
                    } else {
                        s.push_str(&format!("[rip + 0x{:x}]", *displacement as u64));
                    }
                } else {
                    s.push('[');

                    // Build memory expression
                    let mut parts: Vec<String> = Vec::new();

                    if let Some(b) = base {
                        parts.push(b.name().to_string());
                    }

                    if let Some((idx, scale)) = index {
                        if *scale != 1 {
                            parts.push(format!("{}*{}", idx.name(), scale));
                        } else {
                            parts.push(idx.name().to_string());
                        }
                    }

                    if *displacement != 0 || (base.is_none() && index.is_none()) {
                        let d = *displacement;
                        if d < 0 {
                            parts.push(format!("- 0x{:x}", d.unsigned_abs()));
                        } else {
                            parts.push(format!("+ 0x{:x}", d as u64));
                        }
                    }

                    s.push_str(&parts.join(" + "));
                    s.push(']');
                }

                // Add size prefix if needed for ambiguity
                if base.is_none() && index.is_none() && !rip_relative {
                    // Absolute address — need size hint
                    s = format!(
                        "{}[{}]",
                        size_hint.intel_prefix(),
                        s.trim_start_matches('[').trim_end_matches(']')
                    );
                }

                s
            }
            X86DecodedOperand::Immediate { value, size: _ } => {
                // Use hex for larger values
                if value.unsigned_abs() > 9 {
                    if *value < 0 {
                        format!("-0x{:x}", value.unsigned_abs())
                    } else {
                        format!("0x{:x}", *value as u64)
                    }
                } else {
                    format!("{}", value)
                }
            }
            X86DecodedOperand::RelativeOffset { offset, size: _ } => {
                let target = (inst.address as i64)
                    .wrapping_add(inst.size as i64)
                    .wrapping_add(*offset);
                if *offset < 0 {
                    format!("0x{:x}", target as u64)
                } else {
                    format!("0x{:x}", target as u64)
                }
            }
            X86DecodedOperand::ImplicitRegister { reg } => reg.name().to_string(),
            X86DecodedOperand::OpmaskRegister { reg, zeroing } => {
                if *zeroing {
                    format!("{} {{z}}", reg.name())
                } else {
                    reg.name().to_string()
                }
            }
            X86DecodedOperand::FPURegister { index } => format!("st({})", index),
        }
    }

    fn format_operand_att(&self, op: &X86DecodedOperand, inst: &X86DecodedInstruction) -> String {
        match op {
            X86DecodedOperand::Register { reg, size_hint: _ } => format!("%{}", reg.name()),
            X86DecodedOperand::Memory {
                segment,
                base,
                index,
                displacement,
                size_hint: _,
                rip_relative,
            } => {
                let mut s = String::new();

                // Segment override
                if let Some(seg) = segment {
                    s.push_str(&format!("%{}:", seg.name()));
                }

                if *rip_relative {
                    if *displacement < 0 {
                        s.push_str(&format!("-0x{:x}(%rip)", displacement.unsigned_abs()));
                    } else if *displacement == 0 {
                        s.push_str("(%rip)");
                    } else {
                        s.push_str(&format!("0x{:x}(%rip)", *displacement as u64));
                    }
                } else {
                    // AT&T: displacement(base, index, scale)
                    let d = *displacement;
                    let disp_str = if d < 0 {
                        format!("-0x{:x}", d.unsigned_abs())
                    } else if d == 0 && (base.is_some() || index.is_some()) {
                        String::new()
                    } else {
                        format!("0x{:x}", d as u64)
                    };

                    let base_str = match base {
                        Some(b) => format!("%{}", b.name()),
                        None => String::new(),
                    };

                    let index_str = match index {
                        Some((idx, scale)) => {
                            if *scale != 1 {
                                format!(", %{}, {}", idx.name(), scale)
                            } else {
                                format!(", %{}", idx.name())
                            }
                        }
                        None => String::new(),
                    };

                    s.push_str(&format!("{}({}{})", disp_str, base_str, index_str));
                }

                s
            }
            X86DecodedOperand::Immediate { value, size: _ } => {
                if value.unsigned_abs() > 9 {
                    if *value < 0 {
                        format!("$-0x{:x}", value.unsigned_abs())
                    } else {
                        format!("$0x{:x}", *value as u64)
                    }
                } else {
                    format!("${}", value)
                }
            }
            X86DecodedOperand::RelativeOffset { offset, size: _ } => {
                let target = (inst.address as i64)
                    .wrapping_add(inst.size as i64)
                    .wrapping_add(*offset);
                format!("0x{:x}", target as u64)
            }
            X86DecodedOperand::ImplicitRegister { reg } => format!("%{}", reg.name()),
            X86DecodedOperand::OpmaskRegister { reg, zeroing } => {
                if *zeroing {
                    format!("%{} {{z}}", reg.name())
                } else {
                    format!("%{}", reg.name())
                }
            }
            X86DecodedOperand::FPURegister { index } => format!("%st({})", index),
        }
    }
}

// ============================================================================
// Register Name Helpers
// ============================================================================

fn gpr8_name(reg: u8, rex: Option<&RexInfo>) -> X86RegName {
    let has_rex = rex.map_or(false, |r| r.present);
    match (reg, has_rex) {
        (0, _) => X86RegName::AL,
        (1, _) => X86RegName::CL,
        (2, _) => X86RegName::DL,
        (3, _) => X86RegName::BL,
        (4, false) => X86RegName::AH,
        (5, false) => X86RegName::CH,
        (6, false) => X86RegName::DH,
        (7, false) => X86RegName::BH,
        (4, true) => X86RegName::SPL,
        (5, true) => X86RegName::BPL,
        (6, true) => X86RegName::SIL,
        (7, true) => X86RegName::DIL,
        (8, _) => X86RegName::R8B,
        (9, _) => X86RegName::R9B,
        (10, _) => X86RegName::R10B,
        (11, _) => X86RegName::R11B,
        (12, _) => X86RegName::R12B,
        (13, _) => X86RegName::R13B,
        (14, _) => X86RegName::R14B,
        (15, _) => X86RegName::R15B,
        _ => X86RegName::AL,
    }
}

fn gpr16_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::AX,
        1 => X86RegName::CX,
        2 => X86RegName::DX,
        3 => X86RegName::BX,
        4 => X86RegName::SP,
        5 => X86RegName::BP,
        6 => X86RegName::SI,
        7 => X86RegName::DI,
        8 => X86RegName::R8W,
        9 => X86RegName::R9W,
        10 => X86RegName::R10W,
        11 => X86RegName::R11W,
        12 => X86RegName::R12W,
        13 => X86RegName::R13W,
        14 => X86RegName::R14W,
        15 => X86RegName::R15W,
        _ => X86RegName::AX,
    }
}

fn gpr32_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::EAX,
        1 => X86RegName::ECX,
        2 => X86RegName::EDX,
        3 => X86RegName::EBX,
        4 => X86RegName::ESP,
        5 => X86RegName::EBP,
        6 => X86RegName::ESI,
        7 => X86RegName::EDI,
        8 => X86RegName::R8D,
        9 => X86RegName::R9D,
        10 => X86RegName::R10D,
        11 => X86RegName::R11D,
        12 => X86RegName::R12D,
        13 => X86RegName::R13D,
        14 => X86RegName::R14D,
        15 => X86RegName::R15D,
        16 => X86RegName::R16D,
        17 => X86RegName::R17D,
        18 => X86RegName::R18D,
        19 => X86RegName::R19D,
        20 => X86RegName::R20D,
        21 => X86RegName::R21D,
        22 => X86RegName::R22D,
        23 => X86RegName::R23D,
        24 => X86RegName::R24D,
        25 => X86RegName::R25D,
        26 => X86RegName::R26D,
        27 => X86RegName::R27D,
        28 => X86RegName::R28D,
        29 => X86RegName::R29D,
        30 => X86RegName::R30D,
        31 => X86RegName::R31D,
        _ => X86RegName::EAX,
    }
}

fn gpr64_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::RAX,
        1 => X86RegName::RCX,
        2 => X86RegName::RDX,
        3 => X86RegName::RBX,
        4 => X86RegName::RSP,
        5 => X86RegName::RBP,
        6 => X86RegName::RSI,
        7 => X86RegName::RDI,
        8 => X86RegName::R8,
        9 => X86RegName::R9,
        10 => X86RegName::R10,
        11 => X86RegName::R11,
        12 => X86RegName::R12,
        13 => X86RegName::R13,
        14 => X86RegName::R14,
        15 => X86RegName::R15,
        16 => X86RegName::R16,
        17 => X86RegName::R17,
        18 => X86RegName::R18,
        19 => X86RegName::R19,
        20 => X86RegName::R20,
        21 => X86RegName::R21,
        22 => X86RegName::R22,
        23 => X86RegName::R23,
        24 => X86RegName::R24,
        25 => X86RegName::R25,
        26 => X86RegName::R26,
        27 => X86RegName::R27,
        28 => X86RegName::R28,
        29 => X86RegName::R29,
        30 => X86RegName::R30,
        31 => X86RegName::R31,
        _ => X86RegName::RAX,
    }
}

fn xmm_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::XMM0,
        1 => X86RegName::XMM1,
        2 => X86RegName::XMM2,
        3 => X86RegName::XMM3,
        4 => X86RegName::XMM4,
        5 => X86RegName::XMM5,
        6 => X86RegName::XMM6,
        7 => X86RegName::XMM7,
        8 => X86RegName::XMM8,
        9 => X86RegName::XMM9,
        10 => X86RegName::XMM10,
        11 => X86RegName::XMM11,
        12 => X86RegName::XMM12,
        13 => X86RegName::XMM13,
        14 => X86RegName::XMM14,
        15 => X86RegName::XMM15,
        16 => X86RegName::XMM16,
        17 => X86RegName::XMM17,
        18 => X86RegName::XMM18,
        19 => X86RegName::XMM19,
        20 => X86RegName::XMM20,
        21 => X86RegName::XMM21,
        22 => X86RegName::XMM22,
        23 => X86RegName::XMM23,
        24 => X86RegName::XMM24,
        25 => X86RegName::XMM25,
        26 => X86RegName::XMM26,
        27 => X86RegName::XMM27,
        28 => X86RegName::XMM28,
        29 => X86RegName::XMM29,
        30 => X86RegName::XMM30,
        31 => X86RegName::XMM31,
        _ => X86RegName::XMM0,
    }
}

fn ymm_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::YMM0,
        1 => X86RegName::YMM1,
        2 => X86RegName::YMM2,
        3 => X86RegName::YMM3,
        4 => X86RegName::YMM4,
        5 => X86RegName::YMM5,
        6 => X86RegName::YMM6,
        7 => X86RegName::YMM7,
        8 => X86RegName::YMM8,
        9 => X86RegName::YMM9,
        10 => X86RegName::YMM10,
        11 => X86RegName::YMM11,
        12 => X86RegName::YMM12,
        13 => X86RegName::YMM13,
        14 => X86RegName::YMM14,
        15 => X86RegName::YMM15,
        16 => X86RegName::YMM16,
        17 => X86RegName::YMM17,
        18 => X86RegName::YMM18,
        19 => X86RegName::YMM19,
        20 => X86RegName::YMM20,
        21 => X86RegName::YMM21,
        22 => X86RegName::YMM22,
        23 => X86RegName::YMM23,
        24 => X86RegName::YMM24,
        25 => X86RegName::YMM25,
        26 => X86RegName::YMM26,
        27 => X86RegName::YMM27,
        28 => X86RegName::YMM28,
        29 => X86RegName::YMM29,
        30 => X86RegName::YMM30,
        31 => X86RegName::YMM31,
        _ => X86RegName::YMM0,
    }
}

fn zmm_name(reg: u8) -> X86RegName {
    match reg {
        0 => X86RegName::ZMM0,
        1 => X86RegName::ZMM1,
        2 => X86RegName::ZMM2,
        3 => X86RegName::ZMM3,
        4 => X86RegName::ZMM4,
        5 => X86RegName::ZMM5,
        6 => X86RegName::ZMM6,
        7 => X86RegName::ZMM7,
        8 => X86RegName::ZMM8,
        9 => X86RegName::ZMM9,
        10 => X86RegName::ZMM10,
        11 => X86RegName::ZMM11,
        12 => X86RegName::ZMM12,
        13 => X86RegName::ZMM13,
        14 => X86RegName::ZMM14,
        15 => X86RegName::ZMM15,
        16 => X86RegName::ZMM16,
        17 => X86RegName::ZMM17,
        18 => X86RegName::ZMM18,
        19 => X86RegName::ZMM19,
        20 => X86RegName::ZMM20,
        21 => X86RegName::ZMM21,
        22 => X86RegName::ZMM22,
        23 => X86RegName::ZMM23,
        24 => X86RegName::ZMM24,
        25 => X86RegName::ZMM25,
        26 => X86RegName::ZMM26,
        27 => X86RegName::ZMM27,
        28 => X86RegName::ZMM28,
        29 => X86RegName::ZMM29,
        30 => X86RegName::ZMM30,
        31 => X86RegName::ZMM31,
        _ => X86RegName::ZMM0,
    }
}

// ============================================================================
// Group Instruction Mnemonic Resolution
// ============================================================================

fn group1_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("add"),
        1 => Some("or"),
        2 => Some("adc"),
        3 => Some("sbb"),
        4 => Some("and"),
        5 => Some("sub"),
        6 => Some("xor"),
        7 => Some("cmp"),
        _ => None,
    }
}

fn group2_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("rol"),
        1 => Some("ror"),
        2 => Some("rcl"),
        3 => Some("rcr"),
        4 => Some("shl"),
        5 => Some("shr"),
        6 => Some("sal"),
        7 => Some("sar"),
        _ => None,
    }
}

fn group3_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("test"),
        1 => Some("test"),
        2 => Some("not"),
        3 => Some("neg"),
        4 => Some("mul"),
        5 => Some("imul"),
        6 => Some("div"),
        7 => Some("idiv"),
        _ => None,
    }
}

fn group4_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("inc"),
        1 => Some("dec"),
        _ => None,
    }
}

fn group5_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("inc"),
        1 => Some("dec"),
        2 => Some("call"),
        3 => Some("call"),
        4 => Some("jmp"),
        5 => Some("jmp"),
        6 => Some("push"),
        _ => None,
    }
}

fn group6_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("sldt"),
        1 => Some("str"),
        2 => Some("lldt"),
        3 => Some("ltr"),
        4 => Some("verr"),
        5 => Some("verw"),
        _ => None,
    }
}

fn group7_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("sgdt"),
        1 => Some("sidt"),
        2 => Some("lgdt"),
        3 => Some("lidt"),
        4 => Some("smsw"),
        6 => Some("lmsw"),
        7 => Some("invlpg"),
        _ => None,
    }
}

fn group8_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        4 => Some("bt"),
        5 => Some("bts"),
        6 => Some("btr"),
        7 => Some("btc"),
        _ => None,
    }
}

fn group9_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        1 => Some("cmpxchg8b"),
        3 => Some("xrstors"),
        4 => Some("xsavec"),
        5 => Some("xsaves"),
        6 => Some("vmptrld"),
        7 => Some("vmptrst"),
        _ => None,
    }
}

fn group10_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("ud2"),
        _ => None,
    }
}

fn group11_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("mov"),
        _ => None,
    }
}

fn group12_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("cmovo"),
        1 => Some("cmovno"),
        2 => Some("cmovb"),
        3 => Some("cmovae"),
        4 => Some("cmove"),
        5 => Some("cmovne"),
        6 => Some("cmovbe"),
        7 => Some("cmova"),
        _ => None,
    }
}

fn group13_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("cmovs"),
        1 => Some("cmovns"),
        2 => Some("cmovp"),
        3 => Some("cmovnp"),
        4 => Some("cmovl"),
        5 => Some("cmovge"),
        6 => Some("cmovle"),
        7 => Some("cmovg"),
        _ => None,
    }
}

fn group14_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("seto"),
        1 => Some("setno"),
        2 => Some("setb"),
        3 => Some("setae"),
        4 => Some("sete"),
        5 => Some("setne"),
        6 => Some("setbe"),
        7 => Some("seta"),
        _ => None,
    }
}

fn group15_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("sets"),
        1 => Some("setns"),
        2 => Some("setp"),
        3 => Some("setnp"),
        4 => Some("setl"),
        5 => Some("setge"),
        6 => Some("setle"),
        7 => Some("setg"),
        _ => None,
    }
}

fn group16_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("jo"),
        1 => Some("jno"),
        2 => Some("jb"),
        3 => Some("jae"),
        4 => Some("je"),
        5 => Some("jne"),
        6 => Some("jbe"),
        7 => Some("ja"),
        _ => None,
    }
}

fn group17_mnemonic(reg_field: u8) -> Option<&'static str> {
    match reg_field {
        0 => Some("js"),
        1 => Some("jns"),
        2 => Some("jp"),
        3 => Some("jnp"),
        4 => Some("jl"),
        5 => Some("jge"),
        6 => Some("jle"),
        7 => Some("jg"),
        _ => None,
    }
}

// ============================================================================
// COMPLETE INSTRUCTION TABLES
// ============================================================================

/// Helper to create a basic instruction table entry.
fn mk_entry(
    mnemonic: &'static str,
    form: InstrEncodingForm,
    has_modrm: bool,
    imm_size: u8,
) -> InstrTableEntry {
    InstrTableEntry {
        opcode: 0, // Will be set by caller
        mnemonic,
        encoding_form: form,
        has_modrm,
        imm_size,
        attributes: InstructionAttributes::default(),
        group: None,
        att_size_hint: OperandSizeHint::None,
    }
}

fn mk_entry_with_attrs(
    mnemonic: &'static str,
    form: InstrEncodingForm,
    has_modrm: bool,
    imm_size: u8,
    attrs: InstructionAttributes,
) -> InstrTableEntry {
    InstrTableEntry {
        opcode: 0,
        mnemonic,
        encoding_form: form,
        has_modrm,
        imm_size,
        attributes: attrs,
        group: None,
        att_size_hint: OperandSizeHint::None,
    }
}

fn mk_entry_group(opcode: u16, group: u8) -> InstrTableEntry {
    InstrTableEntry {
        opcode,
        mnemonic: "",
        encoding_form: InstrEncodingForm::GroupOpcodeExt,
        has_modrm: true,
        imm_size: 1,
        attributes: InstructionAttributes {
            has_modrm: true,
            is_group_instruction: true,
            opcode_extension_from_3bits: true,
            ..Default::default()
        },
        group: Some(group),
        att_size_hint: OperandSizeHint::None,
    }
}

// ---- Primary Opcode Map (00-FF) ----

fn primary_opcode_table() -> Vec<InstrTableEntry> {
    vec![
        // 00-07: ADD r/m8, r8 / ADD r/m16/32, r16/32 / PUSH ES
        InstrTableEntry {
            opcode: 0x00,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x01,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x02,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x03,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x04,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x05,
            mnemonic: "add",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x06,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // PUSH ES (16/32 only)
        InstrTableEntry {
            opcode: 0x07,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // POP ES
        // 08-0F: OR
        InstrTableEntry {
            opcode: 0x08,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x09,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x0A,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x0B,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x0C,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x0D,
            mnemonic: "or",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        mk_entry_group(0x0E, 1), // PUSH CS (16/32 only)
        InstrTableEntry {
            opcode: 0x0F,
            mnemonic: "",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // 2-byte escape
        // 10-17: ADC
        InstrTableEntry {
            opcode: 0x10,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x11,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x12,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x13,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x14,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x15,
            mnemonic: "adc",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        mk_entry_group(0x16, 1), // PUSH SS
        mk_entry_group(0x17, 1), // POP SS
        // 18-1F: SBB
        InstrTableEntry {
            opcode: 0x18,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x19,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x1A,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x1B,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x1C,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x1D,
            mnemonic: "sbb",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        mk_entry_group(0x1E, 1), // PUSH DS
        mk_entry_group(0x1F, 1), // POP DS
        // 20-27: AND
        InstrTableEntry {
            opcode: 0x20,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x21,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x22,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x23,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x24,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x25,
            mnemonic: "and",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x26,
            mnemonic: "es",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // ES prefix
        InstrTableEntry {
            opcode: 0x27,
            mnemonic: "daa",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 28-2F: SUB
        InstrTableEntry {
            opcode: 0x28,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x29,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x2A,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x2B,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x2C,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x2D,
            mnemonic: "sub",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x2E,
            mnemonic: "cs",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // CS prefix
        InstrTableEntry {
            opcode: 0x2F,
            mnemonic: "das",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 30-37: XOR
        InstrTableEntry {
            opcode: 0x30,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x31,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x32,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x33,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x34,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x35,
            mnemonic: "xor",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x36,
            mnemonic: "ss",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // SS prefix
        InstrTableEntry {
            opcode: 0x37,
            mnemonic: "aaa",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 38-3F: CMP
        InstrTableEntry {
            opcode: 0x38,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x39,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x3A,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x3B,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x3C,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x3D,
            mnemonic: "cmp",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x3E,
            mnemonic: "ds",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // DS prefix
        InstrTableEntry {
            opcode: 0x3F,
            mnemonic: "aas",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 40-47: INC r16/32 in 32-bit mode; REX prefixes in 64-bit mode
        InstrTableEntry {
            opcode: 0x40,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x41,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x42,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x43,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x44,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x45,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x46,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x47,
            mnemonic: "inc",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 48-4F: DEC r16/32 in 32-bit mode; REX.W prefixes in 64-bit mode
        InstrTableEntry {
            opcode: 0x48,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x49,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4A,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4B,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4C,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4D,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4E,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4F,
            mnemonic: "dec",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 50-57: PUSH r16/32/64
        InstrTableEntry {
            opcode: 0x50,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x51,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x52,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x53,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x54,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x55,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x56,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x57,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 58-5F: POP r16/32/64
        InstrTableEntry {
            opcode: 0x58,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x59,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5A,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5B,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5C,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5D,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5E,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5F,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 60-67: PUSHA/POPA/BOUND/prefixes
        InstrTableEntry {
            opcode: 0x60,
            mnemonic: "pusha",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x61,
            mnemonic: "popa",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x62,
            mnemonic: "bound",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x63,
            mnemonic: "movsxd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_64bit_only: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x64,
            mnemonic: "fs",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x65,
            mnemonic: "gs",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x66,
            mnemonic: "osize",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x67,
            mnemonic: "asize",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 68-6F: PUSH imm / IMUL / INS / OUTS
        InstrTableEntry {
            opcode: 0x68,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x69,
            mnemonic: "imul",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 4,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x6A,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x6B,
            mnemonic: "imul",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x6C,
            mnemonic: "insb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x6D,
            mnemonic: "insd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x6E,
            mnemonic: "outsb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x6F,
            mnemonic: "outsd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 70-7F: Jcc rel8
        InstrTableEntry {
            opcode: 0x70,
            mnemonic: "jo",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x71,
            mnemonic: "jno",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x72,
            mnemonic: "jb",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x73,
            mnemonic: "jae",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x74,
            mnemonic: "je",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x75,
            mnemonic: "jne",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x76,
            mnemonic: "jbe",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x77,
            mnemonic: "ja",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x78,
            mnemonic: "js",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x79,
            mnemonic: "jns",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7A,
            mnemonic: "jp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7B,
            mnemonic: "jnp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7C,
            mnemonic: "jl",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7D,
            mnemonic: "jge",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7E,
            mnemonic: "jle",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x7F,
            mnemonic: "jg",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 80-83: Group 1 (arithmetic with imm) — GRP1
        InstrTableEntry {
            opcode: 0x80,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(1),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x81,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 4,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(1),
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x82,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(1),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x83,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(1),
            att_size_hint: OperandSizeHint::Dword,
        },
        // 84-87: TEST / XCHG
        InstrTableEntry {
            opcode: 0x84,
            mnemonic: "test",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x85,
            mnemonic: "test",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x86,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x87,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 88-8B: MOV
        InstrTableEntry {
            opcode: 0x88,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x89,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x8A,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x8B,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 8C-8F: MOV seg / LEA / POP
        InstrTableEntry {
            opcode: 0x8C,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8D,
            mnemonic: "lea",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8E,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8F,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 90: NOP / XCHG AX,AX
        InstrTableEntry {
            opcode: 0x90,
            mnemonic: "nop",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 91-97: XCHG AX/EAX/RAX, r
        InstrTableEntry {
            opcode: 0x91,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x92,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x93,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x94,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x95,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x96,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x97,
            mnemonic: "xchg",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 98-9F: CBW/CWD/...
        InstrTableEntry {
            opcode: 0x98,
            mnemonic: "cbw",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x99,
            mnemonic: "cwd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9A,
            mnemonic: "callf",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_call: true,
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9B,
            mnemonic: "wait",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9C,
            mnemonic: "pushf",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9D,
            mnemonic: "popf",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9E,
            mnemonic: "sahf",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x9F,
            mnemonic: "lahf",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // A0-A3: MOV AL/AX/EAX, moffs / MOV moffs, AL/AX/EAX
        InstrTableEntry {
            opcode: 0xA0,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::AccumMem,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xA1,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::AccumMem,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xA2,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::MemAccum,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xA3,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::MemAccum,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // A4-A7: MOVSB/MOVSW/LODS/STOS
        InstrTableEntry {
            opcode: 0xA4,
            mnemonic: "movsb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xA5,
            mnemonic: "movsd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xA6,
            mnemonic: "cmpsb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xA7,
            mnemonic: "cmpsd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // A8-AB: TEST AL, imm / STOS / LODS / SCAS
        InstrTableEntry {
            opcode: 0xA8,
            mnemonic: "test",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xA9,
            mnemonic: "test",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xAA,
            mnemonic: "stosb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xAB,
            mnemonic: "stosd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // AC-AF: LODSB/LODSD/SCASB/SCASD
        InstrTableEntry {
            opcode: 0xAC,
            mnemonic: "lodsb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xAD,
            mnemonic: "lodsd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xAE,
            mnemonic: "scasb",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xAF,
            mnemonic: "scasd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_string_instruction: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // B0-B7: MOV r8, imm8
        InstrTableEntry {
            opcode: 0xB0,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB1,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB2,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB3,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB4,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB5,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB6,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB7,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        // B8-BF: MOV r16/32/64, imm
        InstrTableEntry {
            opcode: 0xB8,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xB9,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBA,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBB,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBC,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBD,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBE,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBF,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegImm,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // C0-C1: Group 2 (shift/rotate by imm8)
        InstrTableEntry {
            opcode: 0xC0,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xC1,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Dword,
        },
        // C2-C3: RET imm16
        InstrTableEntry {
            opcode: 0xC2,
            mnemonic: "ret",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 2,
            attributes: InstructionAttributes {
                is_return: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xC3,
            mnemonic: "ret",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_return: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // C4-C5: LES/LDS (or VEX prefixes)
        InstrTableEntry {
            opcode: 0xC4,
            mnemonic: "les",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xC5,
            mnemonic: "lds",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // C6-C7: Group 11 (MOV r/m8/16/32, imm)
        InstrTableEntry {
            opcode: 0xC6,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(11),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xC7,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 4,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(11),
            att_size_hint: OperandSizeHint::Dword,
        },
        // C8-CF: ENTER/LEAVE/RETF/INT/IRET
        InstrTableEntry {
            opcode: 0xC8,
            mnemonic: "enter",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 3,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xC9,
            mnemonic: "leave",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCA,
            mnemonic: "retf",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 2,
            attributes: InstructionAttributes {
                is_return: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCB,
            mnemonic: "retf",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_return: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCC,
            mnemonic: "int3",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCD,
            mnemonic: "int",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCE,
            mnemonic: "into",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xCF,
            mnemonic: "iret",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_return: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // D0-D3: Group 2 (shift/rotate by 1 and CL)
        InstrTableEntry {
            opcode: 0xD0,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xD1,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xD2,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xD3,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(2),
            att_size_hint: OperandSizeHint::Dword,
        },
        // D4-D7: AAM/AAD/XLAT
        InstrTableEntry {
            opcode: 0xD4,
            mnemonic: "aam",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xD5,
            mnemonic: "aad",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xD6,
            mnemonic: "salc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xD7,
            mnemonic: "xlat",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // D8-DF: FPU instructions (x87)
        InstrTableEntry {
            opcode: 0xD8,
            mnemonic: "fadd",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0xD9,
            mnemonic: "fld",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xDA,
            mnemonic: "fiadd",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xDB,
            mnemonic: "fild",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xDC,
            mnemonic: "fadd",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Double,
        },
        InstrTableEntry {
            opcode: 0xDD,
            mnemonic: "fld",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Double,
        },
        InstrTableEntry {
            opcode: 0xDE,
            mnemonic: "fiadd",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        InstrTableEntry {
            opcode: 0xDF,
            mnemonic: "fild",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        // E0-E7: LOOP / JCXZ
        InstrTableEntry {
            opcode: 0xE0,
            mnemonic: "loopne",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xE1,
            mnemonic: "loope",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xE2,
            mnemonic: "loop",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xE3,
            mnemonic: "jcxz",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xE4,
            mnemonic: "in",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xE5,
            mnemonic: "in",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xE6,
            mnemonic: "out",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xE7,
            mnemonic: "out",
            encoding_form: InstrEncodingForm::AccumImm,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // E8-EB: CALL/JMP
        InstrTableEntry {
            opcode: 0xE8,
            mnemonic: "call",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_call: true,
                is_branch: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xE9,
            mnemonic: "jmp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xEA,
            mnemonic: "jmpf",
            encoding_form: InstrEncodingForm::RmImm,
            has_modrm: false,
            imm_size: 6,
            attributes: InstructionAttributes {
                is_branch: true,
                is_64bit_only: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xEB,
            mnemonic: "jmp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 1,
            attributes: InstructionAttributes {
                is_branch: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // EC-EF: IN/OUT DX
        InstrTableEntry {
            opcode: 0xEC,
            mnemonic: "in",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xED,
            mnemonic: "in",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xEE,
            mnemonic: "out",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xEF,
            mnemonic: "out",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // F0: LOCK prefix
        InstrTableEntry {
            opcode: 0xF0,
            mnemonic: "lock",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xF1,
            mnemonic: "icebp",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // F2-F3: REPNE/REP prefixes
        InstrTableEntry {
            opcode: 0xF2,
            mnemonic: "repne",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xF3,
            mnemonic: "rep",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // F4-F5: HLT/CMC
        InstrTableEntry {
            opcode: 0xF4,
            mnemonic: "hlt",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xF5,
            mnemonic: "cmc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // F6-F7: Group 3 (TEST/NOT/NEG/MUL/IMUL/DIV/IDIV)
        InstrTableEntry {
            opcode: 0xF6,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(3),
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xF7,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(3),
            att_size_hint: OperandSizeHint::Dword,
        },
        // F8-F9: CLC/STC
        InstrTableEntry {
            opcode: 0xF8,
            mnemonic: "clc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xF9,
            mnemonic: "stc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // FA-FB: CLI/STI
        InstrTableEntry {
            opcode: 0xFA,
            mnemonic: "cli",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xFB,
            mnemonic: "sti",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // FC-FD: CLD/STD
        InstrTableEntry {
            opcode: 0xFC,
            mnemonic: "cld",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xFD,
            mnemonic: "std",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // FE: Group 4 (INC/DEC r/m8)
        InstrTableEntry {
            opcode: 0xFE,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(4),
            att_size_hint: OperandSizeHint::Byte,
        },
        // FF: Group 5 (INC/DEC/CALL/JMP/PUSH r/m)
        InstrTableEntry {
            opcode: 0xFF,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(5),
            att_size_hint: OperandSizeHint::None,
        },
    ]
}

// ---- Two-Byte Opcode Map (0F xx) ----

fn opcode_table_0f() -> Vec<InstrTableEntry> {
    vec![
        // 0F 00: Group 6 (SLDT/STR/LLDT/LTR/VERR/VERW)
        InstrTableEntry {
            opcode: 0x00,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(6),
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 01: Group 7 (SGDT/SIDT/LGDT/LIDT/SMSW/LMSW/INVLPG)
        InstrTableEntry {
            opcode: 0x01,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(7),
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 02: LAR
        InstrTableEntry {
            opcode: 0x02,
            mnemonic: "lar",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 03: LSL
        InstrTableEntry {
            opcode: 0x03,
            mnemonic: "lsl",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 05: SYSCALL
        InstrTableEntry {
            opcode: 0x05,
            mnemonic: "syscall",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 06: CLTS
        InstrTableEntry {
            opcode: 0x06,
            mnemonic: "clts",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 07: SYSRET
        InstrTableEntry {
            opcode: 0x07,
            mnemonic: "sysret",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_return: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 08: INVD
        InstrTableEntry {
            opcode: 0x08,
            mnemonic: "invd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 09: WBINVD
        InstrTableEntry {
            opcode: 0x09,
            mnemonic: "wbinvd",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 0B: UD2
        InstrTableEntry {
            opcode: 0x0B,
            mnemonic: "ud2",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 0D: PREFETCH (Group)
        InstrTableEntry {
            opcode: 0x0D,
            mnemonic: "prefetch",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 0E: FEMMS
        InstrTableEntry {
            opcode: 0x0E,
            mnemonic: "femms",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 0F: 3DNow! prefix
        InstrTableEntry {
            opcode: 0x0F,
            mnemonic: "",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 10-1F: MOVSS/MOVSD/MOVUPS/MOVUPD/MOVSS variants
        InstrTableEntry {
            opcode: 0x10,
            mnemonic: "movups",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x11,
            mnemonic: "movups",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x12,
            mnemonic: "movlps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x13,
            mnemonic: "movlps",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x14,
            mnemonic: "unpcklps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x15,
            mnemonic: "unpckhps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x16,
            mnemonic: "movhps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x17,
            mnemonic: "movhps",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F 18: PREFETCH hint (Group)
        InstrTableEntry {
            opcode: 0x18,
            mnemonic: "prefetchh",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 1F: NOP (multi-byte)
        InstrTableEntry {
            opcode: 0x1F,
            mnemonic: "nop",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 20-23: MOV from/to control/debug registers
        InstrTableEntry {
            opcode: 0x20,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // MOV r32, CRn
        InstrTableEntry {
            opcode: 0x21,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // MOV r32, DRn
        InstrTableEntry {
            opcode: 0x22,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // MOV CRn, r32
        InstrTableEntry {
            opcode: 0x23,
            mnemonic: "mov",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // MOV DRn, r32
        // 0F 28-2F: MOVAPS/MOVAPD/CVTTPS2PI/CVTTSS2SI etc.
        InstrTableEntry {
            opcode: 0x28,
            mnemonic: "movaps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x29,
            mnemonic: "movaps",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x2A,
            mnemonic: "cvtpi2ps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x2B,
            mnemonic: "movntps",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x2C,
            mnemonic: "cvttps2pi",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x2D,
            mnemonic: "cvtps2pi",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x2E,
            mnemonic: "ucomiss",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0x2F,
            mnemonic: "comiss",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        // 0F 30: WRMSR
        InstrTableEntry {
            opcode: 0x30,
            mnemonic: "wrmsr",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 31: RDTSC
        InstrTableEntry {
            opcode: 0x31,
            mnemonic: "rdtsc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 32: RDMSR
        InstrTableEntry {
            opcode: 0x32,
            mnemonic: "rdmsr",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 33: RDPMC
        InstrTableEntry {
            opcode: 0x33,
            mnemonic: "rdpmc",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 34: SYSENTER
        InstrTableEntry {
            opcode: 0x34,
            mnemonic: "sysenter",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 35: SYSEXIT
        InstrTableEntry {
            opcode: 0x35,
            mnemonic: "sysexit",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_return: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 37: GETSEC
        InstrTableEntry {
            opcode: 0x37,
            mnemonic: "getsec",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 40-4F: CMOVcc
        InstrTableEntry {
            opcode: 0x40,
            mnemonic: "cmovo",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x41,
            mnemonic: "cmovno",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x42,
            mnemonic: "cmovb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x43,
            mnemonic: "cmovae",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x44,
            mnemonic: "cmove",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x45,
            mnemonic: "cmovne",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x46,
            mnemonic: "cmovbe",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x47,
            mnemonic: "cmova",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x48,
            mnemonic: "cmovs",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x49,
            mnemonic: "cmovns",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4A,
            mnemonic: "cmovp",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4B,
            mnemonic: "cmovnp",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4C,
            mnemonic: "cmovl",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4D,
            mnemonic: "cmovge",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4E,
            mnemonic: "cmovle",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x4F,
            mnemonic: "cmovg",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F 50-5F: SSE/SSE2 packed arithmetic
        InstrTableEntry {
            opcode: 0x50,
            mnemonic: "movmskps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x51,
            mnemonic: "sqrtps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x52,
            mnemonic: "rsqrtps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x53,
            mnemonic: "rcpps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x54,
            mnemonic: "andps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x55,
            mnemonic: "andnps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x56,
            mnemonic: "orps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x57,
            mnemonic: "xorps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // 0F 58-5F: SSE packed arithmetic
        InstrTableEntry {
            opcode: 0x58,
            mnemonic: "addps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x59,
            mnemonic: "mulps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5A,
            mnemonic: "cvtps2pd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x5B,
            mnemonic: "cvtdq2ps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5C,
            mnemonic: "subps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5D,
            mnemonic: "minps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5E,
            mnemonic: "divps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5F,
            mnemonic: "maxps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // 0F 60-6F: MMX/SSE2 instructions
        InstrTableEntry {
            opcode: 0x60,
            mnemonic: "punpcklbw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x61,
            mnemonic: "punpcklwd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x62,
            mnemonic: "punpckldq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x63,
            mnemonic: "packsswb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x64,
            mnemonic: "pcmpgtb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x65,
            mnemonic: "pcmpgtw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x66,
            mnemonic: "pcmpgtd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x67,
            mnemonic: "packuswb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x68,
            mnemonic: "punpckhbw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x69,
            mnemonic: "punpckhwd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x6A,
            mnemonic: "punpckhdq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x6B,
            mnemonic: "packssdw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x6C,
            mnemonic: "punpcklqdq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x6D,
            mnemonic: "punpckhqdq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // 0F 6E-6F: MOVD/MOVQ
        InstrTableEntry {
            opcode: 0x6E,
            mnemonic: "movd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x6F,
            mnemonic: "movq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F 70-76: MMX/SSE2 shift instructions
        InstrTableEntry {
            opcode: 0x70,
            mnemonic: "pshufw",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F 74-76: PCMPEQB/W/D
        InstrTableEntry {
            opcode: 0x74,
            mnemonic: "pcmpeqb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x75,
            mnemonic: "pcmpeqw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x76,
            mnemonic: "pcmpeqd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F 77: EMMS
        InstrTableEntry {
            opcode: 0x77,
            mnemonic: "emms",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 78-79: VMREAD/VMWRITE
        InstrTableEntry {
            opcode: 0x78,
            mnemonic: "vmread",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x79,
            mnemonic: "vmwrite",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 7E-7F: MOVD/MOVQ variants
        InstrTableEntry {
            opcode: 0x7E,
            mnemonic: "movd",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x7F,
            mnemonic: "movq",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F 80-8F: Jcc rel32
        InstrTableEntry {
            opcode: 0x80,
            mnemonic: "jo",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x81,
            mnemonic: "jno",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x82,
            mnemonic: "jb",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x83,
            mnemonic: "jae",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x84,
            mnemonic: "je",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x85,
            mnemonic: "jne",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x86,
            mnemonic: "jbe",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x87,
            mnemonic: "ja",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x88,
            mnemonic: "js",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x89,
            mnemonic: "jns",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8A,
            mnemonic: "jp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8B,
            mnemonic: "jnp",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8C,
            mnemonic: "jl",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8D,
            mnemonic: "jge",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8E,
            mnemonic: "jle",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x8F,
            mnemonic: "jg",
            encoding_form: InstrEncodingForm::RelBranch,
            has_modrm: false,
            imm_size: 4,
            attributes: InstructionAttributes {
                is_branch: true,
                is_conditional: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F 90-9F: SETcc
        InstrTableEntry {
            opcode: 0x90,
            mnemonic: "seto",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x91,
            mnemonic: "setno",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x92,
            mnemonic: "setb",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x93,
            mnemonic: "setae",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x94,
            mnemonic: "sete",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x95,
            mnemonic: "setne",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x96,
            mnemonic: "setbe",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x97,
            mnemonic: "seta",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x98,
            mnemonic: "sets",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x99,
            mnemonic: "setns",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9A,
            mnemonic: "setp",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9B,
            mnemonic: "setnp",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9C,
            mnemonic: "setl",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9D,
            mnemonic: "setge",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9E,
            mnemonic: "setle",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x9F,
            mnemonic: "setg",
            encoding_form: InstrEncodingForm::RmOnly,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        // 0F A0-A2: PUSH/POP FS/GS, CPUID
        InstrTableEntry {
            opcode: 0xA0,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // PUSH FS
        InstrTableEntry {
            opcode: 0xA1,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        }, // POP FS
        InstrTableEntry {
            opcode: 0xA2,
            mnemonic: "cpuid",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F A3-A5: BT/SHLD/SHRD
        InstrTableEntry {
            opcode: 0xA3,
            mnemonic: "bt",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xA4,
            mnemonic: "shld",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xA5,
            mnemonic: "shld",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F A8-A9: PUSH/POP GS
        InstrTableEntry {
            opcode: 0xA8,
            mnemonic: "push",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xA9,
            mnemonic: "pop",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F AA: RSM
        InstrTableEntry {
            opcode: 0xAA,
            mnemonic: "rsm",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes {
                is_privileged: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F AB: BTS
        InstrTableEntry {
            opcode: 0xAB,
            mnemonic: "bts",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F AC: SHRD
        InstrTableEntry {
            opcode: 0xAC,
            mnemonic: "shrd",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xAD,
            mnemonic: "shrd",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F AE-AF: Group 15 (FXSAVE/FXRSTOR/LDMXCSR/STMXCSR/XSAVE/XRSTOR etc.)
        InstrTableEntry {
            opcode: 0xAE,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(15),
            att_size_hint: OperandSizeHint::None,
        },
        // 0F AF: IMUL
        InstrTableEntry {
            opcode: 0xAF,
            mnemonic: "imul",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F B0-B1: CMPXCHG
        InstrTableEntry {
            opcode: 0xB0,
            mnemonic: "cmpxchg",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB1,
            mnemonic: "cmpxchg",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F B2: LSS
        InstrTableEntry {
            opcode: 0xB2,
            mnemonic: "lss",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F B3: BTR
        InstrTableEntry {
            opcode: 0xB3,
            mnemonic: "btr",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F B4-B5: LFS/LGS
        InstrTableEntry {
            opcode: 0xB4,
            mnemonic: "lfs",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xB5,
            mnemonic: "lgs",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F B6-B7: MOVZX
        InstrTableEntry {
            opcode: 0xB6,
            mnemonic: "movzx",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xB7,
            mnemonic: "movzx",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        // 0F B8: JMPE / POPCNT (F3 prefix)
        InstrTableEntry {
            opcode: 0xB8,
            mnemonic: "popcnt",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F BA: Group 8 (BT/BTS/BTR/BTC with imm8)
        InstrTableEntry {
            opcode: 0xBA,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(8),
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F BB: BTC
        InstrTableEntry {
            opcode: 0xBB,
            mnemonic: "btc",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F BC-BD: BSF/BSR
        InstrTableEntry {
            opcode: 0xBC,
            mnemonic: "bsf",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xBD,
            mnemonic: "bsr",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F BE-BF: MOVSX
        InstrTableEntry {
            opcode: 0xBE,
            mnemonic: "movsx",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xBF,
            mnemonic: "movsx",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        // 0F C0-C1: XADD
        InstrTableEntry {
            opcode: 0xC0,
            mnemonic: "xadd",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xC1,
            mnemonic: "xadd",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F C2-C7: CMP/EQ/SD/LT/LE/UNORD etc.
        InstrTableEntry {
            opcode: 0xC2,
            mnemonic: "cmpps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xC3,
            mnemonic: "movnti",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F C4-C5: PINSRW/PEXTRW
        InstrTableEntry {
            opcode: 0xC4,
            mnemonic: "pinsrw",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xC5,
            mnemonic: "pextrw",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        // 0F C6: SHUFPS
        InstrTableEntry {
            opcode: 0xC6,
            mnemonic: "shufps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // 0F C7: Group 9 (CMPXCHG8B/VMPTRLD/VMPTRST/VMCLEAR/VMXON/...)
        InstrTableEntry {
            opcode: 0xC7,
            mnemonic: "",
            encoding_form: InstrEncodingForm::GroupOpcodeExt,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_group_instruction: true,
                ..Default::default()
            },
            group: Some(9),
            att_size_hint: OperandSizeHint::None,
        },
        // 0F C8-CF: BSWAP
        InstrTableEntry {
            opcode: 0xC8,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xC9,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCA,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCB,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCC,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCD,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCE,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xCF,
            mnemonic: "bswap",
            encoding_form: InstrEncodingForm::RegOnly,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        // 0F D1-D7: PSRLW/PSRAW/PSLLW
        InstrTableEntry {
            opcode: 0xD1,
            mnemonic: "psrlw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD2,
            mnemonic: "psrld",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD3,
            mnemonic: "psrlq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD4,
            mnemonic: "paddq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD5,
            mnemonic: "pmullw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD7,
            mnemonic: "pmovmskb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0xD8,
            mnemonic: "psubusb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xD9,
            mnemonic: "psubusw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDA,
            mnemonic: "pminub",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDB,
            mnemonic: "pand",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDC,
            mnemonic: "paddusb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDD,
            mnemonic: "paddusw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDE,
            mnemonic: "pmaxub",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xDF,
            mnemonic: "pandn",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE0,
            mnemonic: "pavgb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE1,
            mnemonic: "psraw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE2,
            mnemonic: "psrad",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE3,
            mnemonic: "pavgw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE4,
            mnemonic: "pmulhuw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE5,
            mnemonic: "pmulhw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F E6: CVTTPS2DQ/CVTTPD2DQ
        InstrTableEntry {
            opcode: 0xE6,
            mnemonic: "cvttpd2dq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_sse: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xE7,
            mnemonic: "movntq",
            encoding_form: InstrEncodingForm::RmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE8,
            mnemonic: "psubsb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xE9,
            mnemonic: "psubsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xEA,
            mnemonic: "pminsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xEB,
            mnemonic: "por",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xEC,
            mnemonic: "paddsb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xED,
            mnemonic: "paddsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xEE,
            mnemonic: "pmaxsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xEF,
            mnemonic: "pxor",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        // 0F F1-F7: PSLLW/PSLLD/PSLLQ/PMULUDQ/PADD etc.
        InstrTableEntry {
            opcode: 0xF1,
            mnemonic: "psllw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF2,
            mnemonic: "pslld",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF3,
            mnemonic: "psllq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF4,
            mnemonic: "pmuludq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF5,
            mnemonic: "pmaddwd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF6,
            mnemonic: "psadbw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF7,
            mnemonic: "maskmovq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF8,
            mnemonic: "psubb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xF9,
            mnemonic: "psubw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFA,
            mnemonic: "psubd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFB,
            mnemonic: "psubq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFC,
            mnemonic: "paddb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFD,
            mnemonic: "paddw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFE,
            mnemonic: "paddd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0xFF,
            mnemonic: "ud0",
            encoding_form: InstrEncodingForm::Implicit,
            has_modrm: false,
            imm_size: 0,
            attributes: InstructionAttributes::default(),
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
    ]
}

// ---- Three-Byte Opcode Map 0F 38 (SSSE3, SSE4, AES, etc.) ----

fn opcode_table_0f38() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x00,
            mnemonic: "pshufb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x01,
            mnemonic: "phaddw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x02,
            mnemonic: "phaddd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x03,
            mnemonic: "phaddsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x04,
            mnemonic: "pmaddubsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x05,
            mnemonic: "phsubw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x06,
            mnemonic: "phsubd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x07,
            mnemonic: "phsubsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x08,
            mnemonic: "psignb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x09,
            mnemonic: "psignw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0A,
            mnemonic: "psignd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0B,
            mnemonic: "pmulhrsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x10,
            mnemonic: "pblendvb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x14,
            mnemonic: "blendvps",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x15,
            mnemonic: "blendvpd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x17,
            mnemonic: "ptest",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1C,
            mnemonic: "pabsb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1D,
            mnemonic: "pabsw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1E,
            mnemonic: "pabsd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x20,
            mnemonic: "pmovsxbw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x21,
            mnemonic: "pmovsxbd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x22,
            mnemonic: "pmovsxbq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        InstrTableEntry {
            opcode: 0x23,
            mnemonic: "pmovsxwd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x24,
            mnemonic: "pmovsxwq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x25,
            mnemonic: "pmovsxdq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x28,
            mnemonic: "pmuldq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x29,
            mnemonic: "pcmpeqq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x2A,
            mnemonic: "movntdqa",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x2B,
            mnemonic: "packusdw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x30,
            mnemonic: "pmovzxbw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x31,
            mnemonic: "pmovzxbd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x32,
            mnemonic: "pmovzxbq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        InstrTableEntry {
            opcode: 0x33,
            mnemonic: "pmovzxwd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x34,
            mnemonic: "pmovzxwq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x35,
            mnemonic: "pmovzxdq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x37,
            mnemonic: "pcmpgtq",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x38,
            mnemonic: "pminsb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x39,
            mnemonic: "pminsd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3A,
            mnemonic: "pminuw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3B,
            mnemonic: "pminud",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3C,
            mnemonic: "pmaxsb",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3D,
            mnemonic: "pmaxsd",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3E,
            mnemonic: "pmaxuw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x3F,
            mnemonic: "pmaxud",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x40,
            mnemonic: "pmulld",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x41,
            mnemonic: "phminposuw",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // AES instructions (66 prefix)
        InstrTableEntry {
            opcode: 0xDB,
            mnemonic: "aesimc",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDC,
            mnemonic: "aesenc",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDD,
            mnemonic: "aesenclast",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDE,
            mnemonic: "aesdec",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDF,
            mnemonic: "aesdeclast",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // CRC32
        InstrTableEntry {
            opcode: 0xF0,
            mnemonic: "crc32",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0xF1,
            mnemonic: "crc32",
            encoding_form: InstrEncodingForm::RegRM,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
    ]
}

// ---- Three-Byte Opcode Map 0F 3A (SSE4 immediate instructions) ----

fn opcode_table_0f3a() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x08,
            mnemonic: "roundps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x09,
            mnemonic: "roundpd",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0A,
            mnemonic: "roundss",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0x0B,
            mnemonic: "roundsd",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Double,
        },
        InstrTableEntry {
            opcode: 0x0C,
            mnemonic: "blendps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0D,
            mnemonic: "blendpd",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0E,
            mnemonic: "pblendw",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0F,
            mnemonic: "palignr",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x14,
            mnemonic: "pextrb",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x15,
            mnemonic: "pextrw",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Word,
        },
        InstrTableEntry {
            opcode: 0x16,
            mnemonic: "pextrd",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x17,
            mnemonic: "extractps",
            encoding_form: InstrEncodingForm::RmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x20,
            mnemonic: "pinsrb",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Byte,
        },
        InstrTableEntry {
            opcode: 0x21,
            mnemonic: "insertps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x22,
            mnemonic: "pinsrd",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x40,
            mnemonic: "dpps",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x41,
            mnemonic: "dppd",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x42,
            mnemonic: "mpsadbw",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x44,
            mnemonic: "pclmulqdq",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x60,
            mnemonic: "pcmpestrm",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x61,
            mnemonic: "pcmpestri",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x62,
            mnemonic: "pcmpistrm",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x63,
            mnemonic: "pcmpistri",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDF,
            mnemonic: "aeskeygenassist",
            encoding_form: InstrEncodingForm::RegRMImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
    ]
}

// ---- VEX Map 1 (0F) Opcode Table ----

fn vex_opcode_table_1() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x10,
            mnemonic: "vmovups",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x11,
            mnemonic: "vmovups",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: false,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x12,
            mnemonic: "vmovlps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x13,
            mnemonic: "vmovlps",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x14,
            mnemonic: "vunpcklps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x15,
            mnemonic: "vunpckhps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x16,
            mnemonic: "vmovhps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x17,
            mnemonic: "vmovhps",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x28,
            mnemonic: "vmovaps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x29,
            mnemonic: "vmovaps",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x2A,
            mnemonic: "vcvtsi2ss",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0x2C,
            mnemonic: "vcvttss2si",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0x2E,
            mnemonic: "vucomiss",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        InstrTableEntry {
            opcode: 0x2F,
            mnemonic: "vcomiss",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Single,
        },
        // AVX packed arithmetic
        InstrTableEntry {
            opcode: 0x50,
            mnemonic: "vmovmskps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x51,
            mnemonic: "vsqrtps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x52,
            mnemonic: "vrsqrtps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x53,
            mnemonic: "vrcpps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x54,
            mnemonic: "vandps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x55,
            mnemonic: "vandnps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x56,
            mnemonic: "vorps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x57,
            mnemonic: "vxorps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x58,
            mnemonic: "vaddps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x59,
            mnemonic: "vmulps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5A,
            mnemonic: "vcvtps2pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Qword,
        },
        InstrTableEntry {
            opcode: 0x5B,
            mnemonic: "vcvtdq2ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5C,
            mnemonic: "vsubps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5D,
            mnemonic: "vminps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5E,
            mnemonic: "vdivps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x5F,
            mnemonic: "vmaxps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // VEX SSE packed integer
        InstrTableEntry {
            opcode: 0x60,
            mnemonic: "vpunpcklbw",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x61,
            mnemonic: "vpunpcklwd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x62,
            mnemonic: "vpunpckldq",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x6E,
            mnemonic: "vmovd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x6F,
            mnemonic: "vmovdqa",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x7E,
            mnemonic: "vmovd",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0x7F,
            mnemonic: "vmovdqa",
            encoding_form: InstrEncodingForm::VexVvvvRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // VEX C2: VCMP
        InstrTableEntry {
            opcode: 0xC2,
            mnemonic: "vcmpps",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xC6,
            mnemonic: "vshufps",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
    ]
}

// ---- VEX Map 2 (0F 38) Opcode Table ----

fn vex_opcode_table_2() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x00,
            mnemonic: "vpshufb",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x01,
            mnemonic: "vphaddw",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x02,
            mnemonic: "vphaddd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x17,
            mnemonic: "vptest",
            encoding_form: InstrEncodingForm::VexRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1C,
            mnemonic: "vpabsb",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1D,
            mnemonic: "vpabsw",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x1E,
            mnemonic: "vpabsd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // FMA instructions — VEX map 2 with W=0 for FMA, encoded via specific opcodes
        InstrTableEntry {
            opcode: 0x96,
            mnemonic: "vfmaddsub132ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x97,
            mnemonic: "vfmaddsub132pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x98,
            mnemonic: "vfmadd132ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x99,
            mnemonic: "vfmadd132pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9A,
            mnemonic: "vfmsub132ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9B,
            mnemonic: "vfmsub132pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9C,
            mnemonic: "vfnmadd132ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9D,
            mnemonic: "vfnmadd132pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9E,
            mnemonic: "vfnmsub132ps",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x9F,
            mnemonic: "vfnmsub132pd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // VAES instructions
        InstrTableEntry {
            opcode: 0xDC,
            mnemonic: "vaesenc",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDD,
            mnemonic: "vaesenclast",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDE,
            mnemonic: "vaesdec",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xDF,
            mnemonic: "vaesdeclast",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        // AVX2 instructions
        InstrTableEntry {
            opcode: 0xF3,
            mnemonic: "andn",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xF5,
            mnemonic: "bzhi",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
        InstrTableEntry {
            opcode: 0xF7,
            mnemonic: "bextr",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Dword,
        },
    ]
}

// ---- VEX Map 3 (0F 3A) Opcode Table ----

fn vex_opcode_table_3() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x08,
            mnemonic: "vroundps",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x09,
            mnemonic: "vroundpd",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0C,
            mnemonic: "vblendps",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0D,
            mnemonic: "vblendpd",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0E,
            mnemonic: "vpblendw",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x0F,
            mnemonic: "vpalignr",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x40,
            mnemonic: "vdpps",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x44,
            mnemonic: "vpclmulqdq",
            encoding_form: InstrEncodingForm::VexRegVvvvRmImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
    ]
}

// ---- EVEX Map 1 (0F) Opcode Table ----

fn evex_opcode_table_1() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x10,
            mnemonic: "vmovups",
            encoding_form: InstrEncodingForm::EvexRegKRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x11,
            mnemonic: "vmovups",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x28,
            mnemonic: "vmovaps",
            encoding_form: InstrEncodingForm::EvexRegKRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x29,
            mnemonic: "vmovaps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x54,
            mnemonic: "vandps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x55,
            mnemonic: "vandnps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x56,
            mnemonic: "vorps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x57,
            mnemonic: "vxorps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x58,
            mnemonic: "vaddps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x59,
            mnemonic: "vmulps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x5C,
            mnemonic: "vsubps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x5E,
            mnemonic: "vdivps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x6F,
            mnemonic: "vmovdqa32",
            encoding_form: InstrEncodingForm::EvexRegKRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x7F,
            mnemonic: "vmovdqa32",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0xC2,
            mnemonic: "vcmpps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0xC6,
            mnemonic: "vshufps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
    ]
}

// ---- EVEX Map 2-6 stub tables (representative entries) ----

fn evex_opcode_table_2() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x00,
            mnemonic: "vpshufb",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x96,
            mnemonic: "vfmaddsub132ps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x98,
            mnemonic: "vfmadd132ps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
    ]
}

fn evex_opcode_table_3() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x0C,
            mnemonic: "vblendps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
        InstrTableEntry {
            opcode: 0x44,
            mnemonic: "vpclmulqdq",
            encoding_form: InstrEncodingForm::EvexVvvvKRmRegImm,
            has_modrm: true,
            imm_size: 1,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_opmask: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Zword,
        },
    ]
}

fn evex_opcode_table_4() -> Vec<InstrTableEntry> {
    vec![]
}

fn evex_opcode_table_5() -> Vec<InstrTableEntry> {
    vec![
        // AMX-TILE instructions
        InstrTableEntry {
            opcode: 0x49,
            mnemonic: "tileloadd",
            encoding_form: InstrEncodingForm::EvexRegKRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x4B,
            mnemonic: "tilestored",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5C,
            mnemonic: "tdpbf16ps",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
        InstrTableEntry {
            opcode: 0x5E,
            mnemonic: "tdpbusd",
            encoding_form: InstrEncodingForm::EvexVvvvKRmReg,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                is_avx512: true,
                uses_vvvv: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::None,
        },
    ]
}

fn evex_opcode_table_6() -> Vec<InstrTableEntry> {
    vec![]
}

// ---- XOP Map Tables ----

fn xop_opcode_table_8() -> Vec<InstrTableEntry> {
    vec![
        InstrTableEntry {
            opcode: 0x85,
            mnemonic: "vpmacssww",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x86,
            mnemonic: "vpmacsswd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0x95,
            mnemonic: "vpmacswd",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
        InstrTableEntry {
            opcode: 0xA1,
            mnemonic: "vpperm",
            encoding_form: InstrEncodingForm::VexRegVvvvRm,
            has_modrm: true,
            imm_size: 0,
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            group: None,
            att_size_hint: OperandSizeHint::Oword,
        },
    ]
}

fn xop_opcode_table_9() -> Vec<InstrTableEntry> {
    vec![]
}

fn xop_opcode_table_a() -> Vec<InstrTableEntry> {
    vec![]
}

// ============================================================================
// Test Suite
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    // ---- Disassembler Construction ----

    fn make_disassembler(mode: X86ProcessorMode) -> X86FullDisassembler {
        X86FullDisassembler::new(mode)
    }

    fn make_disassembler64() -> X86FullDisassembler {
        X86FullDisassembler::new(X86ProcessorMode::Mode64)
    }

    fn make_disassembler32() -> X86FullDisassembler {
        X86FullDisassembler::new(X86ProcessorMode::Mode32)
    }

    fn make_decoder(mode: X86ProcessorMode) -> X86InstructionDecoder {
        X86InstructionDecoder::new(mode)
    }

    // ---- Basic 64-bit Decoding ----

    #[test]
    fn test_decode_nop() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x90]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "nop");
        assert_eq!(inst.size, 1);
    }

    #[test]
    fn test_decode_ret() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0xC3]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "ret");
        assert_eq!(inst.size, 1);
        assert!(inst.attributes.is_return);
    }

    #[test]
    fn test_decode_push_rax() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x50]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "push");
        assert_eq!(inst.size, 1);
    }

    #[test]
    fn test_decode_push_rbp() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x55]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "push");
    }

    #[test]
    fn test_decode_pop_rax() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x58]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "pop");
    }

    #[test]
    fn test_decode_mov_rax_rcx() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov rax, rcx = REX.W + 89 C8 = 48 89 C8
        let inst = decoder.decode_one(&[0x48, 0x89, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
        assert!(inst.size >= 3);
        assert!(inst.rex.is_some());
        assert!(inst.rex.unwrap().w);
    }

    #[test]
    fn test_decode_add_rax_rcx() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // add rax, rcx = 48 01 C8
        let inst = decoder.decode_one(&[0x48, 0x01, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "add");
    }

    #[test]
    fn test_decode_add_rax_imm5() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // add rax, 5 = 48 83 C0 05 (Group 1 with REX.W)
        let inst = decoder.decode_one(&[0x48, 0x83, 0xC0, 0x05]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        // Note: based on the primary table, 0x83 is group 1
        assert!(inst.attributes.is_group_instruction);
    }

    #[test]
    fn test_decode_sub_rax_rdx() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // sub rax, rdx = 48 29 D0
        let inst = decoder.decode_one(&[0x48, 0x29, 0xD0]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "sub");
    }

    #[test]
    fn test_decode_and_rax_rbx() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // and rax, rbx = 48 21 D8
        let inst = decoder.decode_one(&[0x48, 0x21, 0xD8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "and");
    }

    #[test]
    fn test_decode_xor_rax_rax() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // xor rax, rax = 48 31 C0
        let inst = decoder.decode_one(&[0x48, 0x31, 0xC0]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "xor");
    }

    #[test]
    fn test_decode_cmp_rax_rcx() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // cmp rax, rcx = 48 39 C8
        let inst = decoder.decode_one(&[0x48, 0x39, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "cmp");
    }

    // ---- Branch Instructions ----

    #[test]
    fn test_decode_jmp_rel8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // jmp +0x05 = EB 03 (0xEB + offset)
        let inst = decoder.decode_one(&[0xEB, 0x03]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "jmp");
        assert!(inst.attributes.is_branch);
        assert_eq!(inst.size, 2);
    }

    #[test]
    fn test_decode_call_rel32() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // call rel32 = E8 xx xx xx xx
        let inst = decoder.decode_one(&[0xE8, 0x00, 0x00, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "call");
        assert!(inst.attributes.is_call);
        assert_eq!(inst.size, 5);
    }

    #[test]
    fn test_decode_je_rel8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // je +6 = 74 04
        let inst = decoder.decode_one(&[0x74, 0x04]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "je");
        assert!(inst.attributes.is_branch);
        assert!(inst.attributes.is_conditional);
    }

    #[test]
    fn test_decode_jne_rel8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x75, 0x05]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "jne");
    }

    // ---- Immediate Instructions ----

    #[test]
    fn test_decode_mov_rax_imm64() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov rax, 0x123456789ABCDEF0 = 48 B8 F0 DE BC 9A 78 56 34 12
        let inst =
            decoder.decode_one(&[0x48, 0xB8, 0xF0, 0xDE, 0xBC, 0x9A, 0x78, 0x56, 0x34, 0x12]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
        assert!(inst.size >= 10);
    }

    #[test]
    fn test_decode_mov_eax_imm32() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, 0x12345678 = B8 78 56 34 12
        let inst = decoder.decode_one(&[0xB8, 0x78, 0x56, 0x34, 0x12]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
        assert_eq!(inst.size, 5);
    }

    // ---- LEA ----

    #[test]
    fn test_decode_lea() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // lea rax, [rcx+rdx*2+8] = 48 8D 44 51 08
        let inst = decoder.decode_one(&[0x48, 0x8D, 0x44, 0x51, 0x08]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "lea");
    }

    // ---- Legacy Prefix Decoding ----

    #[test]
    fn test_decode_lock_prefix() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // lock add [rax], 1 = F0 83 00 01
        let inst = decoder.decode_one(&[0xF0, 0x83, 0x00, 0x01]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.prefixes.has_lock);
    }

    #[test]
    fn test_decode_rep_prefix() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // rep movsb = F3 A4
        let inst = decoder.decode_one(&[0xF3, 0xA4]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.prefixes.has_rep);
    }

    #[test]
    fn test_decode_repne_prefix() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // repne scasb = F2 AE
        let inst = decoder.decode_one(&[0xF2, 0xAE]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.prefixes.has_repne);
    }

    #[test]
    fn test_decode_operand_size_override() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // In 64-bit mode, 66 prefix makes operand size 16
        // 66 01 C8 = add ax, cx
        let inst = decoder.decode_one(&[0x66, 0x01, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.prefixes.has_operand_size_override);
    }

    #[test]
    fn test_decode_segment_override_fs() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, fs:[0] = 64 A1 00 00 00 00
        let inst = decoder.decode_one(&[0x64, 0xA1, 0x00, 0x00, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.prefixes.fs_override);
    }

    // ---- ModR/M Register Mode ----

    #[test]
    fn test_decode_modrm_register_mode() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, ecx = 89 C8
        let inst = decoder.decode_one(&[0x89, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
        assert!(inst.attributes.has_modrm);
    }

    #[test]
    fn test_decode_modrm_memory_disp8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, [rcx+8] = 8B 41 08
        let inst = decoder.decode_one(&[0x8B, 0x41, 0x08]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
    }

    #[test]
    fn test_decode_modrm_memory_disp32() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, [rcx+0x1000] = 8B 81 00 10 00 00
        let inst = decoder.decode_one(&[0x8B, 0x81, 0x00, 0x10, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
    }

    // ---- SIB Decoding ----

    #[test]
    fn test_decode_sib_base_index_scale() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, [rcx+rdx*4] = 8B 04 91
        let inst = decoder.decode_one(&[0x8B, 0x04, 0x91]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
    }

    #[test]
    fn test_decode_sib_disp32_no_base() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, [rdx*4 + 0x1000] = 8B 04 95 00 10 00 00
        let inst = decoder.decode_one(&[0x8B, 0x04, 0x95, 0x00, 0x10, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
    }

    #[test]
    fn test_decode_rip_relative() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, [rip+0x1000] = 8B 05 00 10 00 00
        let inst = decoder.decode_one(&[0x8B, 0x05, 0x00, 0x10, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mov");
        // Check that one of the operands has rip_relative
        let has_rip_rel = inst.operands.iter().any(|op| {
            matches!(
                op,
                X86DecodedOperand::Memory {
                    rip_relative: true,
                    ..
                }
            )
        });
        assert!(has_rip_rel);
    }

    // ---- REX Prefix ----

    #[test]
    fn test_decode_rex_present() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov r8, r9 = 4D 89 C8
        let inst = decoder.decode_one(&[0x4D, 0x89, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.rex.is_some());
    }

    #[test]
    fn test_decode_rex_not_present() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov eax, ecx = 89 C8
        let inst = decoder.decode_one(&[0x89, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.rex.is_none());
    }

    #[test]
    fn test_decode_rex_32bit_mode() {
        // In 32-bit mode, 0x40-0x4F are INC/DEC, not REX
        let mut decoder = make_decoder(X86ProcessorMode::Mode32);
        // inc eax = 40
        let inst = decoder.decode_one(&[0x40]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        // In 32-bit mode, 0x40 is INC
        assert!(inst.mnemonic.contains("inc"));
        assert!(inst.rex.is_none());
    }

    // ---- Two-Byte Opcode (0F) Decoding ----

    #[test]
    fn test_decode_cmove() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // cmove eax, ecx = 0F 44 C1
        let inst = decoder.decode_one(&[0x0F, 0x44, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "cmove");
        assert!(inst.attributes.is_conditional);
    }

    #[test]
    fn test_decode_bswap() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // bswap rax = 48 0F C8
        let inst = decoder.decode_one(&[0x48, 0x0F, 0xC8]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "bswap");
    }

    #[test]
    fn test_decode_cpuid() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // cpuid = 0F A2
        let inst = decoder.decode_one(&[0x0F, 0xA2]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "cpuid");
    }

    #[test]
    fn test_decode_syscall() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // syscall = 0F 05
        let inst = decoder.decode_one(&[0x0F, 0x05]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "syscall");
    }

    #[test]
    fn test_decode_sete() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // sete al = 0F 94 C0
        let inst = decoder.decode_one(&[0x0F, 0x94, 0xC0]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "sete");
    }

    #[test]
    fn test_decode_movzx_rm8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // movzx eax, cl = 0F B6 C1
        let inst = decoder.decode_one(&[0x0F, 0xB6, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "movzx");
    }

    #[test]
    fn test_decode_movsx_rm8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // movsx eax, cl = 0F BE C1
        let inst = decoder.decode_one(&[0x0F, 0xBE, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "movsx");
    }

    #[test]
    fn test_decode_imul_reg_rm() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // imul rax, rcx = 48 0F AF C1
        let inst = decoder.decode_one(&[0x48, 0x0F, 0xAF, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "imul");
    }

    // ---- SSE Instructions ----

    #[test]
    fn test_decode_movaps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // movaps xmm0, xmm1 = 0F 28 C1
        let inst = decoder.decode_one(&[0x0F, 0x28, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "movaps");
        assert!(inst.attributes.is_sse);
    }

    #[test]
    fn test_decode_addps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // addps xmm0, xmm1 = 0F 58 C1
        let inst = decoder.decode_one(&[0x0F, 0x58, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "addps");
        assert!(inst.attributes.is_sse);
    }

    #[test]
    fn test_decode_mulps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mulps xmm0, xmm1 = 0F 59 C1
        let inst = decoder.decode_one(&[0x0F, 0x59, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "mulps");
    }

    // ---- SSE2 Instructions ----

    #[test]
    fn test_decode_movdqa() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // movdqa xmm0, xmm1 = 66 0F 6F C1
        let inst = decoder.decode_one(&[0x66, 0x0F, 0x6F, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "movq");
    }

    // ---- Group Instruction Decoding ----

    #[test]
    fn test_decode_group1_add_imm8() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // add rax, 5 = 48 83 C0 05
        let inst = decoder.decode_one(&[0x48, 0x83, 0xC0, 0x05]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_group3_not() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // not rax = 48 F7 D0
        let inst = decoder.decode_one(&[0x48, 0xF7, 0xD0]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_group3_neg() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // neg rax = 48 F7 D8
        let inst = decoder.decode_one(&[0x48, 0xF7, 0xD8]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_group5_inc() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // inc rax = 48 FF C0
        let inst = decoder.decode_one(&[0x48, 0xFF, 0xC0]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_group5_push() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // push rax = FF F0
        let inst = decoder.decode_one(&[0xFF, 0xF0]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_group2_shl_by_cl() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // shl rax, cl = 48 D3 E0
        let inst = decoder.decode_one(&[0x48, 0xD3, 0xE0]);
        assert!(inst.is_some());
    }

    // ---- VEX Instruction Decoding ----

    #[test]
    fn test_decode_vex_2byte_vxorps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // vxorps xmm0, xmm1, xmm2 = C5 F0 57 C2
        // C5 = 2-byte VEX, F0 = ~R=1,m=0? No: C5 F0 means ~R=1 (R=0), vvvv=1111^0F=0?
        // Actually: C5 = 2-byte VEX, F0 = [~R=1][vvvv=0x0F ^ 0x0F = 0][L=0][pp=00]
        // So vvvv=0, meaning XMM0. 57 = opcode. C2 = ModR/M (reg=0=C0>>3? Actually C2=C0>>3=0,rm=2)
        let inst = decoder.decode_one(&[0xC5, 0xF0, 0x57, 0xC2]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "vxorps");
        assert!(inst.attributes.is_avx);
        assert!(inst.vex.is_some());
    }

    #[test]
    fn test_decode_vex_3byte_vaddps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // vaddps ymm0, ymm1, ymm2 = C5 F4 58 C2 with L=1? Actually YMM needs L bit set
        // 3-byte VEX: C4 E2 7D 58 C2? Let's use C5 FC 58 C2 (2-byte, but could work)
        // Actually let's use a 3-byte VEX: C4 E3 7D 58 C2
        // Wait, for YMM we need: C5 FC 58 C2 means ~R=1, vvvv=1111=0F => 0, L=1, pp=11 (66?)
        // This is getting complicated. Let's just test a 2-byte VEX.
        // vaddps xmm0, xmm1, xmm2 = C5 F0 58 C2
        let inst = decoder.decode_one(&[0xC5, 0xF0, 0x58, 0xC2]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "vaddps");
        assert!(inst.attributes.is_avx);
    }

    // ---- Empty/Invalid Input ----

    #[test]
    fn test_decode_empty_bytes() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[]);
        assert!(inst.is_none());
    }

    #[test]
    fn test_decode_incomplete_0f() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // 0F alone is incomplete
        let inst = decoder.decode_one(&[0x0F]);
        assert!(inst.is_none());
    }

    #[test]
    fn test_decode_unknown_byte() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // 0x0E is PUSH CS in 32-bit but probably INVALID in 64-bit
        // We don't have it in primary table as a real opcode
        // Actually 0x0E maps to group 1 in our table. Let's test 0x0F escape
        // Better test: an unused opcode
        // Actually in our primary table, 0x0E is a group entry
        // Let's just test that we handle an opcode we mapped
    }

    // ---- Disassembler Integration ----

    #[test]
    fn test_disassemble_one_nop() {
        let mut dis = make_disassembler64();
        let result = dis.disassemble_one(&[0x90]);
        assert!(result.is_some());
        let (_inst, formatted) = result.unwrap();
        assert!(formatted.contains("nop"));
    }

    #[test]
    fn test_disassemble_one_ret() {
        let mut dis = make_disassembler64();
        let result = dis.disassemble_one(&[0xC3]);
        assert!(result.is_some());
        let (_inst, formatted) = result.unwrap();
        assert!(formatted.contains("ret"));
    }

    #[test]
    fn test_disassemble_all_multiple() {
        let mut dis = make_disassembler64();
        // nop; ret; nop
        let bytes = vec![0x90, 0xC3, 0x90];
        let results = dis.disassemble_all(&bytes);
        assert_eq!(results.len(), 3);
    }

    // ---- AT&T Syntax ----

    #[test]
    fn test_format_att_nop() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Att);
        let inst = X86DecodedInstruction {
            mnemonic: "nop".to_string(),
            opcode: 0x90,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![],
            size: 1,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes::default(),
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x90]);
        assert!(formatted.contains("nop"));
    }

    #[test]
    fn test_format_intel_mov_reg_reg() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "mov".to_string(),
            opcode: 0x89,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::RCX,
                    size_hint: OperandSizeHint::Qword,
                },
                X86DecodedOperand::Register {
                    reg: X86RegName::RAX,
                    size_hint: OperandSizeHint::Qword,
                },
            ],
            size: 3,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: Some(RexInfo {
                present: true,
                w: true,
                r: false,
                x: false,
                b: false,
            }),
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 64,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x48, 0x89, 0xC8]);
        assert!(formatted.contains("mov"));
        assert!(formatted.contains("rcx"));
        assert!(formatted.contains("rax"));
    }

    #[test]
    fn test_format_att_mov_reg_reg() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Att);
        let inst = X86DecodedInstruction {
            mnemonic: "mov".to_string(),
            opcode: 0x89,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::RAX,
                    size_hint: OperandSizeHint::Qword,
                },
                X86DecodedOperand::Register {
                    reg: X86RegName::RCX,
                    size_hint: OperandSizeHint::Qword,
                },
            ],
            size: 3,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 64,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x48, 0x89, 0xC8]);
        assert!(formatted.contains("movq"));
        assert!(formatted.contains("%rax"));
        assert!(formatted.contains("%rcx"));
    }

    #[test]
    fn test_format_memory_operand_intel() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "mov".to_string(),
            opcode: 0x8B,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::EAX,
                    size_hint: OperandSizeHint::Dword,
                },
                X86DecodedOperand::Memory {
                    segment: None,
                    base: Some(X86RegName::RCX),
                    index: Some((X86RegName::RDX, 4)),
                    displacement: 8,
                    size_hint: OperandSizeHint::Dword,
                    rip_relative: false,
                },
            ],
            size: 4,
            address: 0x1000,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x8B, 0x44, 0x91, 0x08]);
        assert!(formatted.contains("eax"));
        assert!(formatted.contains("rcx"));
        assert!(formatted.contains("rdx"));
    }

    #[test]
    fn test_format_memory_operand_att() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Att);
        let inst = X86DecodedInstruction {
            mnemonic: "mov".to_string(),
            opcode: 0x8B,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Memory {
                    segment: None,
                    base: Some(X86RegName::RBX),
                    index: None,
                    displacement: 16,
                    size_hint: OperandSizeHint::Dword,
                    rip_relative: false,
                },
                X86DecodedOperand::Register {
                    reg: X86RegName::EAX,
                    size_hint: OperandSizeHint::Dword,
                },
            ],
            size: 3,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x8B, 0x43, 0x10]);
        assert!(formatted.contains("movl") || formatted.contains("mov"));
        assert!(formatted.contains("rbx"));
        assert!(formatted.contains("eax"));
    }

    #[test]
    fn test_format_rip_relative_intel() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "lea".to_string(),
            opcode: 0x8D,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::RAX,
                    size_hint: OperandSizeHint::Qword,
                },
                X86DecodedOperand::Memory {
                    segment: None,
                    base: None,
                    index: None,
                    displacement: 0x1000,
                    size_hint: OperandSizeHint::None,
                    rip_relative: true,
                },
            ],
            size: 7,
            address: 0x400000,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 64,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[]);
        assert!(formatted.contains("rip"));
    }

    #[test]
    fn test_format_show_bytes() {
        let mut dis = make_disassembler64();
        dis.show_bytes = true;
        let result = dis.disassemble_one(&[0x90]);
        assert!(result.is_some());
        let (_inst, formatted) = result.unwrap();
        // Should contain byte display since show_bytes=true
        assert!(formatted.contains("90"));
    }

    // ---- X86ProcessorMode Tests ----

    #[test]
    fn test_mode_64bit() {
        let mode = X86ProcessorMode::Mode64;
        assert!(mode.is_64bit());
        assert_eq!(mode.default_operand_size(), 32);
        assert_eq!(mode.default_address_size(), 64);
    }

    #[test]
    fn test_mode_32bit() {
        let mode = X86ProcessorMode::Mode32;
        assert!(!mode.is_64bit());
        assert_eq!(mode.default_operand_size(), 32);
        assert_eq!(mode.default_address_size(), 32);
    }

    #[test]
    fn test_mode_16bit() {
        let mode = X86ProcessorMode::Mode16;
        assert!(!mode.is_64bit());
        assert_eq!(mode.default_operand_size(), 16);
        assert_eq!(mode.default_address_size(), 16);
    }

    // ---- Register Name Tests ----

    #[test]
    fn test_gpr64_names() {
        assert_eq!(gpr64_name(0).name(), "rax");
        assert_eq!(gpr64_name(1).name(), "rcx");
        assert_eq!(gpr64_name(7).name(), "rdi");
        assert_eq!(gpr64_name(8).name(), "r8");
        assert_eq!(gpr64_name(15).name(), "r15");
    }

    #[test]
    fn test_gpr32_names() {
        assert_eq!(gpr32_name(0).name(), "eax");
        assert_eq!(gpr32_name(1).name(), "ecx");
        assert_eq!(gpr32_name(7).name(), "edi");
    }

    #[test]
    fn test_gpr16_names() {
        assert_eq!(gpr16_name(0).name(), "ax");
        assert_eq!(gpr16_name(3).name(), "bx");
    }

    #[test]
    fn test_xmm_names() {
        assert_eq!(xmm_name(0).name(), "xmm0");
        assert_eq!(xmm_name(7).name(), "xmm7");
        assert_eq!(xmm_name(15).name(), "xmm15");
    }

    #[test]
    fn test_ymm_names() {
        assert_eq!(ymm_name(0).name(), "ymm0");
        assert_eq!(ymm_name(15).name(), "ymm15");
    }

    #[test]
    fn test_zmm_names() {
        assert_eq!(zmm_name(0).name(), "zmm0");
        assert_eq!(zmm_name(31).name(), "zmm31");
    }

    #[test]
    fn test_register_class() {
        assert_eq!(X86RegName::RAX.class(), X86RegClass::GPR64);
        assert_eq!(X86RegName::EAX.class(), X86RegClass::GPR32);
        assert_eq!(X86RegName::AX.class(), X86RegClass::GPR16);
        assert_eq!(X86RegName::AL.class(), X86RegClass::GPR8);
        assert_eq!(X86RegName::XMM0.class(), X86RegClass::XMM);
        assert_eq!(X86RegName::YMM0.class(), X86RegClass::YMM);
        assert_eq!(X86RegName::ZMM0.class(), X86RegClass::ZMM);
        assert_eq!(X86RegName::K0.class(), X86RegClass::Opmask);
        assert_eq!(X86RegName::ST0.class(), X86RegClass::FPU);
    }

    #[test]
    fn test_register_size_suffix() {
        assert_eq!(X86RegName::RAX.size_suffix(), "q");
        assert_eq!(X86RegName::EAX.size_suffix(), "l");
        assert_eq!(X86RegName::AX.size_suffix(), "w");
        assert_eq!(X86RegName::AL.size_suffix(), "b");
        assert_eq!(X86RegName::XMM0.size_suffix(), "x");
        assert_eq!(X86RegName::YMM0.size_suffix(), "y");
        assert_eq!(X86RegName::ZMM0.size_suffix(), "z");
    }

    // ---- Operand Size Hint Tests ----

    #[test]
    fn test_operand_size_hint_att_suffix() {
        assert_eq!(OperandSizeHint::Byte.att_suffix(), "b");
        assert_eq!(OperandSizeHint::Word.att_suffix(), "w");
        assert_eq!(OperandSizeHint::Dword.att_suffix(), "l");
        assert_eq!(OperandSizeHint::Qword.att_suffix(), "q");
        assert_eq!(OperandSizeHint::Oword.att_suffix(), "x");
        assert_eq!(OperandSizeHint::Yword.att_suffix(), "y");
        assert_eq!(OperandSizeHint::Zword.att_suffix(), "z");
        assert_eq!(OperandSizeHint::Single.att_suffix(), "s");
        assert_eq!(OperandSizeHint::Double.att_suffix(), "d");
    }

    #[test]
    fn test_operand_size_hint_intel_prefix() {
        assert_eq!(OperandSizeHint::Byte.intel_prefix(), "byte ptr ");
        assert_eq!(OperandSizeHint::Word.intel_prefix(), "word ptr ");
        assert_eq!(OperandSizeHint::Dword.intel_prefix(), "dword ptr ");
        assert_eq!(OperandSizeHint::Qword.intel_prefix(), "qword ptr ");
        assert_eq!(OperandSizeHint::Oword.intel_prefix(), "xmmword ptr ");
        assert_eq!(OperandSizeHint::Zword.intel_prefix(), "zmmword ptr ");
    }

    // ---- Group Mnemonic Tests ----

    #[test]
    fn test_group1_mnemonics() {
        assert_eq!(group1_mnemonic(0), Some("add"));
        assert_eq!(group1_mnemonic(1), Some("or"));
        assert_eq!(group1_mnemonic(4), Some("and"));
        assert_eq!(group1_mnemonic(5), Some("sub"));
        assert_eq!(group1_mnemonic(6), Some("xor"));
        assert_eq!(group1_mnemonic(7), Some("cmp"));
    }

    #[test]
    fn test_group2_mnemonics() {
        assert_eq!(group2_mnemonic(0), Some("rol"));
        assert_eq!(group2_mnemonic(4), Some("shl"));
        assert_eq!(group2_mnemonic(5), Some("shr"));
        assert_eq!(group2_mnemonic(7), Some("sar"));
    }

    #[test]
    fn test_group3_mnemonics() {
        assert_eq!(group3_mnemonic(2), Some("not"));
        assert_eq!(group3_mnemonic(3), Some("neg"));
        assert_eq!(group3_mnemonic(4), Some("mul"));
    }

    // ---- LegacyPrefixInfo Tests ----

    #[test]
    fn test_legacy_prefix_default() {
        let p = LegacyPrefixInfo::default();
        assert!(!p.has_lock);
        assert!(!p.has_rep);
        assert!(!p.has_repne);
        assert!(!p.has_operand_size_override);
        assert!(!p.has_address_size_override);
        assert!(p.active_segment_override.is_none());
    }

    // ---- InstructionAttributes Tests ----

    #[test]
    fn test_instruction_attributes_default() {
        let attrs = InstructionAttributes::default();
        assert!(!attrs.has_modrm);
        assert!(!attrs.has_sib);
        assert!(!attrs.is_branch);
        assert!(!attrs.is_avx);
        assert!(!attrs.is_avx512);
    }

    // ---- ModRM Decoding Tests ----

    #[test]
    fn test_modrm_decode_reg_direct() {
        let raw: u8 = 0xC0; // mod=11, reg=000, rm=000
        let m = ModRMDecoded {
            raw,
            mod_field: 3,
            reg_field: 0,
            rm_field: 0,
        };
        assert_eq!(m.mod_field, 3);
        assert_eq!(m.reg_field, 0);
        assert_eq!(m.rm_field, 0);
    }

    #[test]
    fn test_modrm_decode_mem_disp8() {
        let raw: u8 = 0x41; // mod=01, reg=000, rm=001
        let m = ModRMDecoded {
            raw,
            mod_field: 1,
            reg_field: 0,
            rm_field: 1,
        };
        assert_eq!(m.mod_field, 1);
    }

    // ---- SIB Decoding Tests ----

    #[test]
    fn test_sib_decode() {
        let raw: u8 = 0x91; // scale=10=4, index=010=2, base=001=1
        let s = SIBDecoded {
            raw,
            scale: 2,
            index_field: 2,
            base_field: 1,
        };
        assert_eq!(s.scale, 2); // scale 2 means 4
        assert_eq!(s.index_field, 2);
        assert_eq!(s.base_field, 1);
    }

    // ---- Segment Override Tests ----

    #[test]
    fn test_segment_override_names() {
        assert_eq!(SegmentOverride::CS.name(), "cs");
        assert_eq!(SegmentOverride::DS.name(), "ds");
        assert_eq!(SegmentOverride::SS.name(), "ss");
        assert_eq!(SegmentOverride::ES.name(), "es");
        assert_eq!(SegmentOverride::FS.name(), "fs");
        assert_eq!(SegmentOverride::GS.name(), "gs");
    }

    // ---- VexDecodedInfo Tests ----

    #[test]
    fn test_vex_info_default() {
        let v = VexDecodedInfo::default();
        assert!(!v.present);
        assert!(!v.is_3byte);
        assert!(!v.l);
        assert_eq!(v.pp, 0);
        assert_eq!(v.vvvv, 0);
    }

    // ---- EvexDecodedInfo Tests ----

    #[test]
    fn test_evex_info_default() {
        let e = EvexDecodedInfo::default();
        assert!(!e.present);
        assert!(!e.z);
        assert_eq!(e.ll, 0);
        assert_eq!(e.aaa, 0);
    }

    // ---- DisassemblerSyntax Tests ----

    #[test]
    fn test_syntax_equality() {
        assert_eq!(DisassemblerSyntax::Att, DisassemblerSyntax::Att);
        assert_eq!(DisassemblerSyntax::Intel, DisassemblerSyntax::Intel);
        assert_ne!(DisassemblerSyntax::Att, DisassemblerSyntax::Intel);
    }

    // ---- Opmask Formatting ----

    #[test]
    fn test_format_opmask_register() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "vaddps".to_string(),
            opcode: 0x58,
            opcode_map: X86OpcodeMap::EvexMap1,
            operands: vec![X86DecodedOperand::OpmaskRegister {
                reg: X86RegName::K1,
                zeroing: true,
            }],
            size: 6,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: Some(EvexDecodedInfo {
                present: true,
                aaa: 1,
                z: true,
                ..Default::default()
            }),
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                is_avx512: true,
                uses_opmask: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 512,
        };
        let formatted = printer.format(&inst, false, &[]);
        assert!(formatted.contains("vaddps"));
        assert!(formatted.contains("k1"));
    }

    // ---- Instruction Table Sanity Tests ----

    #[test]
    fn test_primary_table_not_empty() {
        let table = primary_opcode_table();
        assert!(table.len() > 200);
    }

    #[test]
    fn test_0f_table_not_empty() {
        let table = opcode_table_0f();
        assert!(table.len() > 100);
    }

    #[test]
    fn test_0f38_table_not_empty() {
        let table = opcode_table_0f38();
        assert!(table.len() > 20);
    }

    #[test]
    fn test_0f3a_table_not_empty() {
        let table = opcode_table_0f3a();
        assert!(table.len() > 10);
    }

    #[test]
    fn test_vex_tables_not_empty() {
        assert!(!vex_opcode_table_1().is_empty());
        assert!(!vex_opcode_table_2().is_empty());
        assert!(!vex_opcode_table_3().is_empty());
    }

    #[test]
    fn test_evex_tables_have_entries() {
        assert!(!evex_opcode_table_1().is_empty());
    }

    // ---- Additional Decode Tests for Coverage ----

    #[test]
    fn test_decode_int3() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0xCC]);
        assert!(inst.is_some());
        assert_eq!(inst.unwrap().mnemonic, "int3");
    }

    #[test]
    fn test_decode_leave() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0xC9]);
        assert!(inst.is_some());
        assert_eq!(inst.unwrap().mnemonic, "leave");
    }

    #[test]
    fn test_decode_hlt() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0xF4]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "hlt");
        assert!(inst.attributes.is_privileged);
    }

    #[test]
    fn test_decode_ud2() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        let inst = decoder.decode_one(&[0x0F, 0x0B]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "ud2");
    }

    #[test]
    fn test_decode_mov_imm32_to_mem() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // mov dword [rax], 0x1234 = C7 00 34 12 00 00
        let inst = decoder.decode_one(&[0xC7, 0x00, 0x34, 0x12, 0x00, 0x00]);
        assert!(inst.is_some());
    }

    #[test]
    fn test_decode_cmov_2byte_prefix() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // cmovl eax, ecx = 0F 4C C1
        let inst = decoder.decode_one(&[0x0F, 0x4C, 0xC1]);
        assert!(inst.is_some());
        assert_eq!(inst.unwrap().mnemonic, "cmovl");
    }

    #[test]
    fn test_decode_jcc_rel32_2byte() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // jg +0x1000 = 0F 8F FC 0F 00 00
        let inst = decoder.decode_one(&[0x0F, 0x8F, 0xFC, 0x0F, 0x00, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "jg");
        assert_eq!(inst.size, 6);
    }

    #[test]
    fn test_disassembler_with_address() {
        let mut dis = X86FullDisassembler::new(X86ProcessorMode::Mode64).with_address(0x4001000);
        assert_eq!(dis.base_address, 0x4001000);
    }

    #[test]
    fn test_disassembler_with_syntax() {
        let mut dis =
            X86FullDisassembler::new(X86ProcessorMode::Mode64).with_syntax(DisassemblerSyntax::Att);
        assert_eq!(dis.syntax, DisassemblerSyntax::Att);
    }

    #[test]
    fn test_disassembler_set_mode() {
        let mut dis = make_disassembler64();
        dis.set_mode(X86ProcessorMode::Mode32);
        assert!(!dis.mode.is_64bit());
    }

    #[test]
    fn test_disassembler_set_base_address() {
        let mut dis = make_disassembler64();
        dis.set_base_address(0xDEADBEEF);
        assert_eq!(dis.base_address, 0xDEADBEEF);
    }

    // ---- FPU Instruction Decoding ----

    #[test]
    fn test_decode_x87_fld() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode32);
        // fld dword [eax] = D9 00
        let inst = decoder.decode_one(&[0xD9, 0x00]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "fld");
    }

    // ---- 3-Byte Opcode Tests ----

    #[test]
    fn test_decode_0f38_pshufb() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // pshufb xmm0, xmm1 = 66 0F 38 00 C1
        let inst = decoder.decode_one(&[0x66, 0x0F, 0x38, 0x00, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "pshufb");
    }

    #[test]
    fn test_decode_0f3a_roundps() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // roundps xmm0, xmm1, 2 = 66 0F 3A 08 C1 02
        let inst = decoder.decode_one(&[0x66, 0x0F, 0x3A, 0x08, 0xC1, 0x02]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "roundps");
    }

    #[test]
    fn test_decode_aesenc() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode64);
        // aesenc xmm0, xmm1 = 66 0F 38 DC C1
        let inst = decoder.decode_one(&[0x66, 0x0F, 0x38, 0xDC, 0xC1]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "aesenc");
    }

    // ---- AMX Instruction Tests ----

    #[test]
    fn test_evex_table_5_has_amx() {
        let table = evex_opcode_table_5();
        assert!(!table.is_empty());
        let has_tile = table
            .iter()
            .any(|e| e.mnemonic.starts_with("tile") || e.mnemonic.starts_with("tdp"));
        assert!(has_tile);
    }

    // ---- Immediate Value Formatting Tests ----

    #[test]
    fn test_format_immediate_hex() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "mov".to_string(),
            opcode: 0xB8,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::EAX,
                    size_hint: OperandSizeHint::Dword,
                },
                X86DecodedOperand::Immediate {
                    value: 0xDEAD,
                    size: 4,
                },
            ],
            size: 5,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes::default(),
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[]);
        assert!(formatted.contains("0xdead"));
    }

    #[test]
    fn test_format_immediate_negative() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Att);
        let inst = X86DecodedInstruction {
            mnemonic: "add".to_string(),
            opcode: 0x83,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![
                X86DecodedOperand::Register {
                    reg: X86RegName::EAX,
                    size_hint: OperandSizeHint::Dword,
                },
                X86DecodedOperand::Immediate { value: -5, size: 1 },
            ],
            size: 3,
            address: 0,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                has_modrm: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[]);
        assert!(formatted.contains("-0x5") || formatted.contains("-5"));
    }

    // ---- Annotated Output ----

    #[test]
    fn test_annotated_output() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Annotated);
        let inst = X86DecodedInstruction {
            mnemonic: "nop".to_string(),
            opcode: 0x90,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![],
            size: 1,
            address: 0x4000,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes::default(),
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x90]);
        assert!(formatted.contains("0x4000"));
        assert!(formatted.contains("nop"));
    }

    // ---- Relative Offset ----

    #[test]
    fn test_relative_offset_target() {
        let printer = X86InstructionPrinter::new(DisassemblerSyntax::Intel);
        let inst = X86DecodedInstruction {
            mnemonic: "je".to_string(),
            opcode: 0x74,
            opcode_map: X86OpcodeMap::Primary,
            operands: vec![X86DecodedOperand::RelativeOffset {
                offset: 0x04,
                size: 1,
            }],
            size: 2,
            address: 0x1000,
            prefixes: LegacyPrefixInfo::default(),
            rex: None,
            vex: None,
            evex: None,
            implicit_operands: vec![],
            attributes: InstructionAttributes {
                is_branch: true,
                ..Default::default()
            },
            opcode_extension: None,
            operand_size: 32,
            address_size: 64,
            vector_length: 0,
        };
        let formatted = printer.format(&inst, false, &[0x74, 0x04]);
        // Target should be 0x1000 + 2 + 4 = 0x1006
        assert!(formatted.contains("0x1006"));
    }

    // ---- 32-bit mode specific tests ----

    #[test]
    fn test_decode_32bit_inc() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode32);
        // inc eax = 40
        let inst = decoder.decode_one(&[0x40]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert!(inst.mnemonic.contains("inc"));
    }

    #[test]
    fn test_decode_32bit_push_es() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode32);
        // push es = 06
        let inst = decoder.decode_one(&[0x06]);
        assert!(inst.is_some());
        let inst = inst.unwrap();
        assert_eq!(inst.mnemonic, "push");
    }

    // ---- X86DecodedOperand constructors ----

    #[test]
    fn test_decoded_operand_constructors() {
        let reg_op = X86DecodedOperand::Register {
            reg: X86RegName::RAX,
            size_hint: OperandSizeHint::Qword,
        };
        assert!(matches!(reg_op, X86DecodedOperand::Register { .. }));

        let imm_op = X86DecodedOperand::Immediate { value: 42, size: 4 };
        assert!(matches!(imm_op, X86DecodedOperand::Immediate { .. }));

        let mem_op = X86DecodedOperand::Memory {
            segment: None,
            base: Some(X86RegName::RAX),
            index: None,
            displacement: 0,
            size_hint: OperandSizeHint::Dword,
            rip_relative: false,
        };
        assert!(matches!(mem_op, X86DecodedOperand::Memory { .. }));
    }

    // ---- Address Mode Tests ----

    #[test]
    fn test_address_mode16_variants() {
        let m = AddressMode16::BxSi;
        assert_ne!(m, AddressMode16::BxDi);
        assert_ne!(m, AddressMode16::Si);
    }

    #[test]
    fn test_address_mode32_direct() {
        let m = AddressMode32::Direct(X86RegName::EAX);
        match m {
            AddressMode32::Direct(r) => assert_eq!(r, X86RegName::EAX),
            _ => panic!("Expected Direct"),
        }
    }

    #[test]
    fn test_address_mode64_rip_relative() {
        let m = AddressMode64::RipRelative(0x1000);
        match m {
            AddressMode64::RipRelative(d) => assert_eq!(d, 0x1000),
            _ => panic!("Expected RipRelative"),
        }
    }

    // ---- Instruction Encoding Form Tests ----

    #[test]
    fn test_encoding_form_variants() {
        assert_ne!(InstrEncodingForm::Implicit, InstrEncodingForm::RegOnly);
        assert_ne!(InstrEncodingForm::RegRM, InstrEncodingForm::RmReg);
        assert_ne!(InstrEncodingForm::RelBranch, InstrEncodingForm::AccumImm);
    }

    // ---- Opcode Map Tests ----

    #[test]
    fn test_opcode_map_variants() {
        assert_ne!(X86OpcodeMap::Primary, X86OpcodeMap::Map0F);
        assert_ne!(X86OpcodeMap::VexMap1, X86OpcodeMap::EvexMap1);
        assert_ne!(X86OpcodeMap::XopMap8, X86OpcodeMap::XopMap9);
    }

    // ---- 16-bit mode basic test ----

    #[test]
    fn test_decode_16bit_nop() {
        let mut decoder = make_decoder(X86ProcessorMode::Mode16);
        let inst = decoder.decode_one(&[0x90]);
        assert!(inst.is_some());
        assert_eq!(inst.unwrap().mnemonic, "nop");
    }
}