llvm-native-core 0.1.16

//! RISC-V Subtarget — CPU feature detection, extension parsing,
//! and subtarget capability queries for the RISC-V backend.
//!
//! Clean-room behavioral reconstruction from the RISC-V ISA Manual
//! and LLVM's RISCVSubtarget. Zero LLVM source consultation.
//!
//! The subtarget determines which ISA extensions are available
//! and provides capability queries used throughout the backend.

use std::collections::HashSet;

// ---------------------------------------------------------------------------
// Known CPU definitions
// ---------------------------------------------------------------------------

/// Known RISC-V CPU names with their default ISA feature sets.
const KNOWN_CPUS: &[(&str, &[&str])] = &[
    // Generic
    ("generic-rv32", &["i"]),
    ("generic-rv64", &["i"]),
    // SiFive E-series (embedded, RV32)
    ("sifive-e20", &["i", "m", "c"]),
    ("sifive-e24", &["i", "m", "c"]),
    ("sifive-e31", &["i", "m", "a", "c"]),
    ("sifive-e34", &["i", "m", "a", "c"]),
    ("sifive-e76", &["i", "m", "a", "f", "d", "c"]),
    // SiFive S-series (supervisor, RV64)
    ("sifive-s21", &["i", "m", "a", "c"]),
    ("sifive-s51", &["i", "m", "a", "c"]),
    ("sifive-s54", &["i", "m", "a", "f", "d", "c"]),
    ("sifive-s76", &["i", "m", "a", "f", "d", "c"]),
    // SiFive U-series (Linux-capable, RV64)
    ("sifive-u54", &["i", "m", "a", "f", "d", "c"]),
    ("sifive-u74", &["i", "m", "a", "f", "d", "c"]),
    // Rocket (UC Berkeley)
    ("rocket-rv32", &["i", "m", "a", "f", "d", "c"]),
    ("rocket-rv64", &["i", "m", "a", "f", "d", "c"]),
    // BOOM (UC Berkeley, out-of-order)
    ("boom-v1", &["i", "m", "a", "f", "d", "c"]),
    ("boom-v2", &["i", "m", "a", "f", "d", "c"]),
    (
        "boom-v3",
        &["i", "m", "a", "f", "d", "c", "zba", "zbb", "zbs"],
    ),
    // T-Head (Alibaba)
    ("c906", &["i", "m", "a", "f", "d", "c", "v"]),
    (
        "c910",
        &[
            "i", "m", "a", "f", "d", "c", "v", "zba", "zbb", "zbc", "zbs",
        ],
    ),
    (
        "c920",
        &[
            "i", "m", "a", "f", "d", "c", "v", "zba", "zbb", "zbc", "zbs", "zkn", "zks",
        ],
    ),
    // Kendryte K210 (RV64GC)
    ("k210", &["i", "m", "a", "f", "d", "c"]),
    // XiangShan (Chinese Academy of Sciences, high-perf OoO)
    (
        "xiangshan-nanhu",
        &[
            "i", "m", "a", "f", "d", "c", "v", "zba", "zbb", "zbc", "zbs", "zkn",
        ],
    ),
    // SpacemiT K1 / M1 (RVA22 profile)
    (
        "spacemit-x60",
        &[
            "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbs", "zicbom", "zicboz", "zicbop",
        ],
    ),
    // SOPHGO SG2042 (many-core RV64GC)
    ("sg2042", &["i", "m", "a", "f", "d", "c", "v"]),
    // Milk-V Duo / CV1800B (embedded RV64)
    ("c906fdv", &["i", "m", "a", "f", "d", "c", "v"]),
];

// ---------------------------------------------------------------------------
// RiscVSubtarget
// ---------------------------------------------------------------------------

/// RISC-V subtarget: encapsulates feature set derived from the
/// target triple, CPU name, and explicit feature string.
///
/// # Fields
/// * `is_64bit` — RV64 (true) or RV32 (false).
/// * `cpu` — CPU name for tuning.
/// * `features` — full set of enabled ISA extensions.
/// * Extension flags: `has_m`, `has_a`, `has_f`, `has_d`, `has_c`, `has_v`.
/// * Bit-manipulation: `has_zba`, `has_zbb`, `has_zbc`, `has_zbs`.
/// * Cache management: `has_zicbom`, `has_zicboz`, `has_zicbop`.
/// * Misc: `has_zihintpause`, `has_zawrs`.
/// * Tuning: `stack_alignment`, `max_inline_size`, `pref_vector_width`.
pub struct RiscVSubtarget {
    /// Whether this is an RV64 (true) or RV32 (false) target.
    pub is_64bit: bool,
    /// CPU name string.
    pub cpu: String,
    /// Full set of enabled ISA extensions (e.g. "m", "a", "f", "d", "c").
    pub features: HashSet<String>,
    /// Has M extension (integer multiply/divide).
    pub has_m: bool,
    /// Has A extension (atomics).
    pub has_a: bool,
    /// Has F extension (single-precision floating-point).
    pub has_f: bool,
    /// Has D extension (double-precision floating-point).
    pub has_d: bool,
    /// Has C extension (compressed instructions).
    pub has_c: bool,
    /// Has V extension (vector).
    pub has_v: bool,
    /// Has Zba (address generation bit-manipulation).
    pub has_zba: bool,
    /// Has Zbb (basic bit-manipulation).
    pub has_zbb: bool,
    /// Has Zbc (carry-less multiply bit-manipulation).
    pub has_zbc: bool,
    /// Has Zbs (single-bit bit-manipulation).
    pub has_zbs: bool,
    /// Has Zicbom (cache block operation: management).
    pub has_zicbom: bool,
    /// Has Zicboz (cache block operation: zero).
    pub has_zicboz: bool,
    /// Has Zicbop (cache block operation: prefetch).
    pub has_zicbop: bool,
    /// Has Zihintpause (pause hint).
    pub has_zihintpause: bool,
    /// Has Zawrs (wait-on-reservation-set).
    pub has_zawrs: bool,
    /// Stack alignment in bytes (typically 16 per psABI).
    pub stack_alignment: u32,
    /// Maximum size (in bytes) for automatic function inlining.
    pub max_inline_size: u32,
    /// Preferred vector width in bits for auto-vectorization.
    pub pref_vector_width: u32,
}

impl RiscVSubtarget {
    /// Construct a new `RiscVSubtarget` from a triple, CPU name, and
    /// explicit feature string.
    ///
    /// The `is_64bit` flag is derived from the triple.  The feature
    /// set is built by merging the CPU's default features with any
    /// explicitly enabled (+) or disabled (-) features from the
    /// feature string.
    pub fn new(triple: &str, cpu: &str, features: &str) -> Self {
        let is_64bit = triple.to_lowercase().starts_with("riscv64");

        // Start with the CPU's default feature set
        let mut feature_set = Self::get_features_for_cpu(cpu);

        // Parse explicit +/- features
        Self::parse_feature_string(&mut feature_set, features);

        let has_m = feature_set.contains("m");
        let has_a = feature_set.contains("a");
        let has_f = feature_set.contains("f");
        let has_d = feature_set.contains("d");
        let has_c = feature_set.contains("c");
        let has_v = feature_set.contains("v");
        let has_zba = feature_set.contains("zba");
        let has_zbb = feature_set.contains("zbb");
        let has_zbc = feature_set.contains("zbc");
        let has_zbs = feature_set.contains("zbs");
        let has_zicbom = feature_set.contains("zicbom");
        let has_zicboz = feature_set.contains("zicboz");
        let has_zicbop = feature_set.contains("zicbop");
        let has_zihintpause = feature_set.contains("zihintpause");
        let has_zawrs = feature_set.contains("zawrs");

        // Tuning defaults
        let max_inline_size = if is_64bit { 128 } else { 64 };
        let pref_vector_width = if has_v { 128 } else { 0 };

        RiscVSubtarget {
            is_64bit,
            cpu: cpu.to_string(),
            features: feature_set,
            has_m,
            has_a,
            has_f,
            has_d,
            has_c,
            has_v,
            has_zba,
            has_zbb,
            has_zbc,
            has_zbs,
            has_zicbom,
            has_zicboz,
            has_zicbop,
            has_zihintpause,
            has_zawrs,
            stack_alignment: 16,
            max_inline_size,
            pref_vector_width,
        }
    }

    /// Parse a feature string like "+m,+a,+f,+d,+c,-c,+v,+zba,+zbb"
    /// and update the given feature set accordingly.
    ///
    /// * `+ext` enables the extension.
    /// * `-ext` disables the extension.
    /// * Unknown extensions are silently ignored.
    fn parse_feature_string(features: &mut HashSet<String>, feature_str: &str) {
        if feature_str.is_empty() {
            return;
        }

        for part in feature_str.split(',') {
            let part = part.trim();
            if part.is_empty() {
                continue;
            }

            if let Some(ext) = part.strip_prefix('+') {
                features.insert(ext.to_string());
                // Enabling D implies F
                if ext == "d" {
                    features.insert("f".to_string());
                }
                // Enabling V implies Zve32x
                if ext == "v" {
                    features.insert("zve32x".to_string());
                }
            } else if let Some(ext) = part.strip_prefix('-') {
                features.remove(ext);
                // Disabling F disables D
                if ext == "f" {
                    features.remove("d");
                }
            }
        }
    }

    /// Return the default ISA feature set for a known CPU name.
    /// Returns `["i"]` for unknown CPUs.
    pub fn get_features_for_cpu(cpu: &str) -> HashSet<String> {
        for &(name, feats) in KNOWN_CPUS {
            if name == cpu {
                return feats.iter().map(|s| s.to_string()).collect();
            }
        }
        // Unknown CPU: default to base "i"
        ["i".to_string()].into_iter().collect()
    }

    // ------------------------------------------------------------------
    // Capability queries
    // ------------------------------------------------------------------

    /// Returns true if hardware floating-point is available
    /// (either F or D extension).
    pub fn has_hard_float(&self) -> bool {
        self.has_f || self.has_d
    }

    /// Returns true if double-precision floating-point is available
    /// (D extension).
    pub fn has_double_float(&self) -> bool {
        self.has_d
    }

    /// Returns true if single-precision floating-point is available
    /// (F extension or D extension, since D implies F).
    pub fn has_single_float(&self) -> bool {
        self.has_f
    }

    /// Returns true if compressed instructions are available.
    pub fn has_compressed(&self) -> bool {
        self.has_c
    }

    /// Returns true if the vector extension is available.
    pub fn has_vector(&self) -> bool {
        self.has_v
    }

    /// Returns true if atomics are available.
    pub fn has_atomics(&self) -> bool {
        self.has_a
    }

    /// Returns true if multiply/divide is available.
    pub fn has_muldiv(&self) -> bool {
        self.has_m
    }

    /// Returns true if any bit-manipulation extension is available.
    pub fn has_bitmanip(&self) -> bool {
        self.has_zba || self.has_zbb || self.has_zbc || self.has_zbs
    }

    /// Returns true if cache block operations are available.
    pub fn has_cache_ops(&self) -> bool {
        self.has_zicbom || self.has_zicboz || self.has_zicbop
    }

    /// Returns the XLEN in bits: 64 for RV64, 32 for RV32.
    pub fn xlen(&self) -> u32 {
        if self.is_64bit {
            64
        } else {
            32
        }
    }

    /// Returns the floating-point register width in bits.
    /// D → 64, F → 32, none → 0.
    pub fn flen(&self) -> u32 {
        if self.has_d {
            64
        } else if self.has_f {
            32
        } else {
            0
        }
    }

    /// Returns the ABI name inferred from the feature set.
    ///
    /// - RV64 + D → lp64d
    /// - RV64 + F → lp64f
    /// - RV64     → lp64
    /// - RV32 + D → ilp32d
    /// - RV32 + F → ilp32f
    /// - RV32     → ilp32
    pub fn abi_name(&self) -> &'static str {
        if self.is_64bit {
            if self.has_d {
                "lp64d"
            } else if self.has_f {
                "lp64f"
            } else {
                "lp64"
            }
        } else {
            if self.has_d {
                "ilp32d"
            } else if self.has_f {
                "ilp32f"
            } else {
                "ilp32"
            }
        }
    }

    /// Returns the ISA string for this subtarget
    /// (e.g. "rv64imafdc" or "rv32imac").
    pub fn isa_string(&self) -> String {
        let mut s = if self.is_64bit {
            "rv64i".to_string()
        } else {
            "rv32i".to_string()
        };
        // Standard extensions in canonical order:
        // m, a, f, d, c, v
        if self.has_m {
            s.push('m');
        }
        if self.has_a {
            s.push('a');
        }
        if self.has_f {
            s.push('f');
        }
        if self.has_d {
            s.push('d');
        }
        if self.has_c {
            s.push('c');
        }
        if self.has_v {
            s.push('v');
        }
        s
    }

    /// Returns a string describing all enabled features.
    pub fn describe(&self) -> String {
        let mut feat_list: Vec<String> = Vec::new();
        if self.has_m {
            feat_list.push("m".to_string());
        }
        if self.has_a {
            feat_list.push("a".to_string());
        }
        if self.has_f {
            feat_list.push("f".to_string());
        }
        if self.has_d {
            feat_list.push("d".to_string());
        }
        if self.has_c {
            feat_list.push("c".to_string());
        }
        if self.has_v {
            feat_list.push("v".to_string());
        }
        if self.has_zba {
            feat_list.push("zba".to_string());
        }
        if self.has_zbb {
            feat_list.push("zbb".to_string());
        }
        if self.has_zbc {
            feat_list.push("zbc".to_string());
        }
        if self.has_zbs {
            feat_list.push("zbs".to_string());
        }
        if self.has_zicbom {
            feat_list.push("zicbom".to_string());
        }
        if self.has_zicboz {
            feat_list.push("zicboz".to_string());
        }
        if self.has_zicbop {
            feat_list.push("zicbop".to_string());
        }
        if self.has_zihintpause {
            feat_list.push("zihintpause".to_string());
        }
        if self.has_zawrs {
            feat_list.push("zawrs".to_string());
        }

        format!(
            "RiscVSubtarget {{ cpu: \"{}\", is_64bit: {}, abi: {}, isa: {}, features: [{}] }}",
            self.cpu,
            self.is_64bit,
            self.abi_name(),
            self.isa_string(),
            feat_list.join(", "),
        )
    }

    // ==================================================================
    // Enhanced ISA string parsing with canonical ordering
    // ==================================================================

    /// Returns the full ISA string with all standard and Z* extensions
    /// in canonical order per the RISC-V ISA naming convention.
    ///
    /// Canonical order: rv32/rv64 I M A F D G (G = IMAFD)
    /// then Z* extensions alphabetically: Zawrs, Zba, Zbb, Zbc, Zbs,
    /// Zicbom, Zicboz, Zicbop, Zihintpause, Zkn, Zks, Zfh, etc.
    pub fn full_isa_string(&self) -> String {
        let mut s = if self.is_64bit {
            "rv64".to_string()
        } else {
            "rv32".to_string()
        };

        // Use G shorthand when all of IMAFD are present with C
        let has_g = self.has_m && self.has_a && self.has_f && self.has_d && self.has_c;
        if has_g {
            s.push_str("gc");
        } else {
            s.push('i');
            if self.has_m {
                s.push('m');
            }
            if self.has_a {
                s.push('a');
            }
            if self.has_f {
                s.push('f');
            }
            if self.has_d {
                s.push('d');
            }
            if self.has_c {
                s.push('c');
            }
        }

        if self.has_v {
            s.push('v');
        }

        // Z* extensions in alphabetical order
        let mut z_exts: Vec<&str> = Vec::new();
        if self.has_zawrs {
            z_exts.push("zawrs");
        }
        if self.has_zba {
            z_exts.push("zba");
        }
        if self.has_zbb {
            z_exts.push("zbb");
        }
        if self.has_zbc {
            z_exts.push("zbc");
        }
        if self.has_zbs {
            z_exts.push("zbs");
        }
        if self.has_zicbom {
            z_exts.push("zicbom");
        }
        if self.has_zicboz {
            z_exts.push("zicboz");
        }
        if self.has_zicbop {
            z_exts.push("zicbop");
        }
        if self.has_zihintpause {
            z_exts.push("zihintpause");
        }

        // Sort Z* extensions alphabetically
        z_exts.sort();
        for ext in z_exts {
            s.push('_');
            s.push_str(ext);
        }

        s
    }
}

// ==================================================================
// Scheduling model classification (public enum)
// ==================================================================

/// The scheduling model for this CPU.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum SchedModel {
    /// In-order, single-issue (SiFive E-series, Rocket)
    InOrderSingleIssue,
    /// In-order, dual-issue (SiFive U74)
    InOrderDualIssue,
    /// Out-of-order, 3-wide (BOOM v1)
    OutOfOrder3Wide,
    /// Out-of-order, 4-wide (BOOM v2)
    OutOfOrder4Wide,
    /// Out-of-order, 6-wide (XiangShan)
    OutOfOrder6Wide,
    /// Out-of-order, 3-wide (T-Head C910)
    OutOfOrderC910,
    /// Custom / unknown
    Generic,
}

impl RiscVSubtarget {
    /// Determine the scheduling model for the current CPU.
    pub fn scheduling_model(&self) -> SchedModel {
        match self.cpu.as_str() {
            // SiFive E-series: in-order, single-issue
            "sifive-e20" | "sifive-e24" | "sifive-e31" | "sifive-e34" => {
                SchedModel::InOrderSingleIssue
            }
            "sifive-e76" => SchedModel::InOrderSingleIssue,
            // SiFive S-series: in-order, single-issue
            "sifive-s21" | "sifive-s51" | "sifive-s54" | "sifive-s76" => {
                SchedModel::InOrderSingleIssue
            }
            // SiFive U54: single-issue; U74: dual-issue
            "sifive-u54" => SchedModel::InOrderSingleIssue,
            "sifive-u74" => SchedModel::InOrderDualIssue,
            // Rocket: in-order, single-issue
            "rocket-rv32" | "rocket-rv64" => SchedModel::InOrderSingleIssue,
            // BOOM v1: 3-wide OoO; v2: 4-wide; v3+: 6-wide
            "boom-v1" => SchedModel::OutOfOrder3Wide,
            "boom-v2" => SchedModel::OutOfOrder4Wide,
            "boom-v3" => SchedModel::OutOfOrder6Wide,
            // T-Head C906: in-order; C910: 3-wide OoO; C920: 4-wide OoO
            "c906" | "c906fdv" => SchedModel::InOrderDualIssue,
            "c910" => SchedModel::OutOfOrderC910,
            "c920" => SchedModel::OutOfOrder4Wide,
            // XiangShan: 6-wide OoO
            "xiangshan-nanhu" => SchedModel::OutOfOrder6Wide,
            // K210: in-order dual-issue
            "k210" => SchedModel::InOrderDualIssue,
            // SG2042: in-order single-issue (C906 cores)
            "sg2042" => SchedModel::InOrderSingleIssue,
            // SpacemiT X60: dual-issue
            "spacemit-x60" => SchedModel::InOrderDualIssue,
            // Generic
            _ => SchedModel::Generic,
        }
    }

    /// Returns the issue width of the CPU.
    pub fn issue_width(&self) -> u32 {
        match self.scheduling_model() {
            SchedModel::InOrderSingleIssue => 1,
            SchedModel::InOrderDualIssue => 2,
            SchedModel::OutOfOrder3Wide => 3,
            SchedModel::OutOfOrder4Wide => 4,
            SchedModel::OutOfOrder6Wide => 6,
            SchedModel::OutOfOrderC910 => 3,
            SchedModel::Generic => 2,
        }
    }

    /// Returns true if the CPU is out-of-order.
    pub fn is_out_of_order(&self) -> bool {
        matches!(
            self.scheduling_model(),
            SchedModel::OutOfOrder3Wide
                | SchedModel::OutOfOrder4Wide
                | SchedModel::OutOfOrder6Wide
                | SchedModel::OutOfOrderC910
        )
    }

    // ==================================================================
    // Tuning flags
    // ==================================================================

    /// Whether to use save/restore libcalls for callee-saved registers.
    /// Common on SiFive E-series to reduce code size.
    pub fn use_save_restore_libcalls(&self) -> bool {
        match self.cpu.as_str() {
            "sifive-e20" | "sifive-e24" | "sifive-e31" | "sifive-e34" => true,
            "sifive-e76" => false, // Has F/D, more registers to save
            _ => false,
        }
    }

    /// Whether to use TP (x4) for TLS base pointer.
    /// Almost all RISC-V targets use TP for TLS.
    pub fn use_tp_for_tls(&self) -> bool {
        // All standard RISC-V targets use TP for TLS
        true
    }

    /// Whether to use the ABI-mandated atomic sequences for
    /// targets without the A extension.
    pub fn use_atomic_abi_libcalls(&self) -> bool {
        !self.has_a
    }

    /// Whether to enable the MachineOutliner for code size reduction.
    pub fn enable_machine_outliner(&self) -> bool {
        // Enable on embedded targets for code size
        self.cpu.starts_with("sifive-e") || self.cpu == "generic-rv32"
    }

    /// Preferred loop unrolling factor for this CPU.
    pub fn loop_unroll_factor(&self) -> u32 {
        match self.scheduling_model() {
            SchedModel::InOrderSingleIssue => 2,
            SchedModel::InOrderDualIssue => 4,
            SchedModel::OutOfOrder3Wide => 4,
            SchedModel::OutOfOrder4Wide => 6,
            SchedModel::OutOfOrder6Wide => 8,
            SchedModel::OutOfOrderC910 => 6,
            SchedModel::Generic => 4,
        }
    }

    /// Maximum number of instructions to consider for interleaving
    /// in the instruction scheduler.
    pub fn scheduler_buffer_size(&self) -> u32 {
        match self.scheduling_model() {
            SchedModel::InOrderSingleIssue => 16,
            SchedModel::InOrderDualIssue => 32,
            SchedModel::OutOfOrder3Wide => 48,
            SchedModel::OutOfOrder4Wide => 64,
            SchedModel::OutOfOrder6Wide => 128,
            SchedModel::OutOfOrderC910 => 64,
            SchedModel::Generic => 32,
        }
    }

    /// Load-to-use latency in cycles.
    pub fn load_to_use_latency(&self) -> u32 {
        match self.scheduling_model() {
            SchedModel::InOrderSingleIssue => 2,
            SchedModel::InOrderDualIssue => 3,
            _ => 4, // OoO cores can hide some latency
        }
    }

    /// Branch misprediction penalty in cycles.
    pub fn branch_mispredict_penalty(&self) -> u32 {
        match self.scheduling_model() {
            SchedModel::InOrderSingleIssue => 3,
            SchedModel::InOrderDualIssue => 4,
            SchedModel::OutOfOrder3Wide => 8,
            SchedModel::OutOfOrder4Wide => 10,
            SchedModel::OutOfOrder6Wide => 12,
            SchedModel::OutOfOrderC910 => 10,
            SchedModel::Generic => 5,
        }
    }

    /// Whether the CPU supports macro-op fusion.
    pub fn has_macro_fusion(&self) -> bool {
        matches!(
            self.scheduling_model(),
            SchedModel::OutOfOrder3Wide
                | SchedModel::OutOfOrder4Wide
                | SchedModel::OutOfOrder6Wide
                | SchedModel::OutOfOrderC910
        )
    }

    /// Whether to enable tail duplication for this CPU.
    pub fn enable_tail_duplication(&self) -> bool {
        self.is_out_of_order()
    }

    /// Whether to prefer predication over branching.
    pub fn prefer_predication(&self) -> bool {
        // OoO cores benefit more from predication
        self.branch_mispredict_penalty() >= 8
    }
}

// ---------------------------------------------------------------------------
// Tests
// ---------------------------------------------------------------------------

#[cfg(test)]
mod tests {
    use super::*;

    // ------------------------------------------------------------------
    // Construction and feature tests
    // ------------------------------------------------------------------

    #[test]
    fn test_new_generic_rv64() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(st.is_64bit);
        assert_eq!(st.xlen(), 64);
        assert!(!st.has_m);
        assert!(!st.has_f);
        assert!(!st.has_d);
        assert!(!st.has_c);
    }

    #[test]
    fn test_new_generic_rv32() {
        let st = RiscVSubtarget::new("riscv32-unknown-elf", "generic-rv32", "");
        assert!(!st.is_64bit);
        assert_eq!(st.xlen(), 32);
    }

    #[test]
    fn test_new_with_explicit_features() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+f,+d,+c");
        assert!(st.has_m);
        assert!(st.has_a);
        assert!(st.has_f);
        assert!(st.has_d);
        assert!(st.has_c);
        assert!(st.has_hard_float());
        assert!(st.has_double_float());
    }

    #[test]
    fn test_new_with_feature_disable() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+f,+d,+c,-c");
        assert!(st.has_m);
        assert!(!st.has_c);
    }

    #[test]
    fn test_enabling_d_implies_f() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+d");
        assert!(st.has_d);
        assert!(st.has_f, "Enabling D should imply F");
    }

    #[test]
    fn test_disabling_f_disables_d() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+d,-f");
        assert!(!st.has_f);
        assert!(!st.has_d, "Disabling F should disable D");
    }

    #[test]
    fn test_vector_extension() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+v");
        assert!(st.has_v);
        assert!(st.has_vector());
        assert_eq!(st.pref_vector_width, 128);
    }

    #[test]
    fn test_bitmanip_extensions() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+zba,+zbb,+zbc,+zbs");
        assert!(st.has_zba);
        assert!(st.has_zbb);
        assert!(st.has_zbc);
        assert!(st.has_zbs);
        assert!(st.has_bitmanip());
    }

    #[test]
    fn test_cache_ops_extensions() {
        let st = RiscVSubtarget::new(
            "riscv64-unknown-elf",
            "generic-rv64",
            "+zicbom,+zicboz,+zicbop",
        );
        assert!(st.has_zicbom);
        assert!(st.has_zicboz);
        assert!(st.has_zicbop);
        assert!(st.has_cache_ops());
    }

    #[test]
    fn test_abi_name_lp64d() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+d");
        assert_eq!(st.abi_name(), "lp64d");
    }

    #[test]
    fn test_abi_name_lp64f() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+f");
        assert_eq!(st.abi_name(), "lp64f");
    }

    #[test]
    fn test_abi_name_lp64() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert_eq!(st.abi_name(), "lp64");
    }

    #[test]
    fn test_abi_name_ilp32d() {
        let st = RiscVSubtarget::new("riscv32-unknown-elf", "generic-rv32", "+d");
        assert_eq!(st.abi_name(), "ilp32d");
    }

    #[test]
    fn test_abi_name_ilp32() {
        let st = RiscVSubtarget::new("riscv32-unknown-elf", "generic-rv32", "");
        assert_eq!(st.abi_name(), "ilp32");
    }

    #[test]
    fn test_isa_string() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+f,+d,+c");
        assert_eq!(st.isa_string(), "rv64imafdc");
        let st32 = RiscVSubtarget::new("riscv32-unknown-elf", "generic-rv32", "+m,+a,+c");
        assert_eq!(st32.isa_string(), "rv32imac");
    }

    #[test]
    fn test_flen() {
        let st_none = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert_eq!(st_none.flen(), 0);
        let st_f = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+f");
        assert_eq!(st_f.flen(), 32);
        let st_d = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+d");
        assert_eq!(st_d.flen(), 64);
    }

    #[test]
    fn test_get_features_for_cpu_c906() {
        let feats = RiscVSubtarget::get_features_for_cpu("c906");
        assert!(feats.contains("v"));
        assert!(feats.contains("f"));
        assert!(feats.contains("d"));
    }

    #[test]
    fn test_get_features_for_cpu_c910() {
        let feats = RiscVSubtarget::get_features_for_cpu("c910");
        assert!(feats.contains("zba"));
        assert!(feats.contains("zbb"));
        assert!(feats.contains("v"));
    }

    #[test]
    fn test_get_features_for_cpu_unknown() {
        let feats = RiscVSubtarget::get_features_for_cpu("unknown-cpu");
        assert_eq!(feats.len(), 1);
        assert!(feats.contains("i"));
    }

    #[test]
    fn test_get_features_for_cpu_sifive_u54() {
        let feats = RiscVSubtarget::get_features_for_cpu("sifive-u54");
        assert!(feats.contains("i"));
        assert!(feats.contains("m"));
        assert!(feats.contains("a"));
        assert!(feats.contains("f"));
        assert!(feats.contains("d"));
        assert!(feats.contains("c"));
    }

    #[test]
    fn test_get_features_for_cpu_k210() {
        let feats = RiscVSubtarget::get_features_for_cpu("k210");
        assert!(feats.contains("f"));
        assert!(feats.contains("d"));
        assert!(feats.contains("c"));
    }

    #[test]
    fn test_has_hard_float() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+f");
        assert!(st.has_hard_float());
        let st_no = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(!st_no.has_hard_float());
    }

    #[test]
    fn test_has_atomics() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+a");
        assert!(st.has_atomics());
        let st_no = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(!st_no.has_atomics());
    }

    #[test]
    fn test_has_muldiv() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m");
        assert!(st.has_muldiv());
        let st_no = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(!st_no.has_muldiv());
    }

    #[test]
    fn test_describe() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "sifive-u54", "+m");
        let desc = st.describe();
        assert!(desc.contains("sifive-u54"));
        assert!(desc.contains("rv64i"));
        assert!(desc.contains("lp64d"));
    }

    #[test]
    fn test_parse_empty_feature_string() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(st.features.contains("i"));
        assert_eq!(st.features.len(), 1);
    }

    #[test]
    fn test_parse_feature_string_with_spaces() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m, +a, +c");
        assert!(st.has_m);
        assert!(st.has_a);
        assert!(st.has_c);
    }

    #[test]
    fn test_hint_extensions() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+zihintpause,+zawrs");
        assert!(st.has_zihintpause);
        assert!(st.has_zawrs);
    }

    // ==================================================================
    // Scheduling model tests
    // ==================================================================

    #[test]
    fn test_scheduling_model_inorder() {
        let st = RiscVSubtarget::new("riscv32-unknown-elf", "sifive-e31", "");
        assert_eq!(st.scheduling_model(), SchedModel::InOrderSingleIssue);
        assert_eq!(st.issue_width(), 1);
        assert!(!st.is_out_of_order());
    }

    #[test]
    fn test_scheduling_model_dual_issue() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "sifive-u74", "");
        assert_eq!(st.scheduling_model(), SchedModel::InOrderDualIssue);
        assert_eq!(st.issue_width(), 2);
    }

    #[test]
    fn test_scheduling_model_ooo() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "boom-v2", "");
        assert_eq!(st.scheduling_model(), SchedModel::OutOfOrder4Wide);
        assert_eq!(st.issue_width(), 4);
        assert!(st.is_out_of_order());
    }

    #[test]
    fn test_scheduling_model_xiangshan() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "xiangshan-nanhu", "");
        assert_eq!(st.scheduling_model(), SchedModel::OutOfOrder6Wide);
        assert_eq!(st.issue_width(), 6);
    }

    #[test]
    fn test_scheduling_model_c910() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "c910", "");
        assert_eq!(st.scheduling_model(), SchedModel::OutOfOrderC910);
        assert_eq!(st.issue_width(), 3);
    }

    // ==================================================================
    // Tuning flag tests
    // ==================================================================

    #[test]
    fn test_use_save_restore_libcalls() {
        let st_embed = RiscVSubtarget::new("riscv32-unknown-elf", "sifive-e20", "");
        assert!(st_embed.use_save_restore_libcalls());

        let st_big = RiscVSubtarget::new("riscv64-unknown-elf", "sifive-u74", "");
        assert!(!st_big.use_save_restore_libcalls());
    }

    #[test]
    fn test_use_tp_for_tls() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(st.use_tp_for_tls());
    }

    #[test]
    fn test_use_atomic_abi_libcalls() {
        let st_no_a = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(st_no_a.use_atomic_abi_libcalls());

        let st_with_a = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+a");
        assert!(!st_with_a.use_atomic_abi_libcalls());
    }

    #[test]
    fn test_enable_machine_outliner() {
        let st_embed = RiscVSubtarget::new("riscv32-unknown-elf", "sifive-e31", "");
        assert!(st_embed.enable_machine_outliner());

        let st_big = RiscVSubtarget::new("riscv64-unknown-elf", "sifive-u74", "");
        assert!(!st_big.enable_machine_outliner());
    }

    #[test]
    fn test_loop_unroll_factor() {
        let st_ino = RiscVSubtarget::new("riscv32-unknown-elf", "sifive-e31", "");
        assert_eq!(st_ino.loop_unroll_factor(), 2);

        let st_ooo = RiscVSubtarget::new("riscv64-unknown-elf", "boom-v2", "");
        assert_eq!(st_ooo.loop_unroll_factor(), 6);
    }

    #[test]
    fn test_scheduler_buffer_size() {
        let st_ino = RiscVSubtarget::new("riscv32-unknown-elf", "sifive-e31", "");
        assert_eq!(st_ino.scheduler_buffer_size(), 16);

        let st_ooo = RiscVSubtarget::new("riscv64-unknown-elf", "xiangshan-nanhu", "");
        assert_eq!(st_ooo.scheduler_buffer_size(), 128);
    }

    #[test]
    fn test_load_to_use_latency() {
        let st_ino = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert_eq!(st_ino.load_to_use_latency(), 2);
    }

    #[test]
    fn test_branch_mispredict_penalty() {
        let st_ino = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert_eq!(st_ino.branch_mispredict_penalty(), 5);

        let st_ooo = RiscVSubtarget::new("riscv64-unknown-elf", "boom-v2", "");
        assert_eq!(st_ooo.branch_mispredict_penalty(), 10);
    }

    #[test]
    fn test_has_macro_fusion() {
        let st_ino = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(!st_ino.has_macro_fusion());

        let st_ooo = RiscVSubtarget::new("riscv64-unknown-elf", "boom-v2", "");
        assert!(st_ooo.has_macro_fusion());
    }

    #[test]
    fn test_full_isa_string() {
        let st = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "+m,+a,+f,+d,+c");
        assert_eq!(st.full_isa_string(), "rv64gc");

        let st32 = RiscVSubtarget::new("riscv32-unknown-elf", "generic-rv32", "+m,+a,+c");
        assert_eq!(st32.full_isa_string(), "rv32imac");
    }

    #[test]
    fn test_full_isa_string_with_z_exts() {
        let st = RiscVSubtarget::new(
            "riscv64-unknown-elf",
            "generic-rv64",
            "+m,+a,+f,+d,+c,+zba,+zbb",
        );
        let isa = st.full_isa_string();
        assert!(isa.starts_with("rv64gc"));
        assert!(isa.contains("zba"));
        assert!(isa.contains("zbb"));
    }

    #[test]
    fn test_get_features_for_cpu_c920() {
        let feats = RiscVSubtarget::get_features_for_cpu("c920");
        assert!(feats.contains("v"));
        assert!(feats.contains("zkn"));
        assert!(feats.contains("zks"));
    }

    #[test]
    fn test_get_features_for_xiangshan() {
        let feats = RiscVSubtarget::get_features_for_cpu("xiangshan-nanhu");
        assert!(feats.contains("v"));
        assert!(feats.contains("zba"));
        assert!(feats.contains("zbb"));
    }

    #[test]
    fn test_prefer_predication() {
        let st_ino = RiscVSubtarget::new("riscv64-unknown-elf", "generic-rv64", "");
        assert!(!st_ino.prefer_predication());

        let st_ooo = RiscVSubtarget::new("riscv64-unknown-elf", "xiangshan-nanhu", "");
        assert!(st_ooo.prefer_predication());
    }
}