llvm-native-core 0.1.16

//! AMDGPU Target Backend — AMD GCN/RDNA GPU instruction set.
//!
//! Clean-room behavioral reconstruction from the AMD GCN3/RDNA
//! ISA manuals, AMD ROCm documentation, and published specifications.
//! Zero LLVM source code consultation.
//!
//! Architecture coverage:
//! - GCN (Graphics Core Next): GFX6–GFX9
//! - RDNA 1/2/3: GFX1010–GFX1150
//! - Register files: SGPRs, VGPRs, AGPRs (652 registers total)
//! - 12 instruction formats: SOP1, SOP2, SOPC, SOPK, SOPP,
//!   VOP1, VOP2, VOPC, VOP3, VOP3P, SMEM, FLAT, DS, MIMG, EXP, VINTRP
//! - 250+ opcodes with complete encoding descriptors
//! - Bit-field encoder for all formats (32-bit and 64-bit)
//! - Kernel ABI lowering (work-item ID, dispatch)
//! - ELF code object emission with note records
//!
//! Modules:
//! - amdgpu_register_info: 652 registers (SGPRs, VGPRs, AGPRs, special)
//! - amdgpu_instr_info: 250+ opcodes across all 12 encoding formats
//! - amdgpu_mc_encoder: Bit-field encoding for all instruction formats
//! - amdgpu_isel: Instruction selection from LLVM IR to AMDGPU
//! - amdgpu_asm_printer: AMDGPU assembly printer
//! - amdgpu_target_machine: ISA versions, subtarget features
//! - amdgpu_kernel_lowering: Kernel ABI, work-item ID computation
//! - amdgpu_code_object: ELF code object emission

pub mod amdgpu_asm_printer;
pub mod amdgpu_code_object;
pub mod amdgpu_instr_info;
pub mod amdgpu_isel;
pub mod amdgpu_isel_full;
pub mod amdgpu_kernel_lowering;
pub mod amdgpu_mc_encoder;
pub mod amdgpu_register_info;
pub mod amdgpu_target_machine;
pub mod amdgpu_x86_bridge;

pub use amdgpu_asm_printer::AmdgpuAsmPrinter;
pub use amdgpu_code_object::AmdgpuCodeObject;
pub use amdgpu_instr_info::{AmdgpuEncodingFormat, AmdgpuInstrDesc, AmdgpuInstrInfo, AmdgpuOpcode};
pub use amdgpu_isel::AmdgpuInstructionSelector;
pub use amdgpu_isel_full::{
    AmdgpuExportTarget, AmdgpuFeatureQuery, AmdgpuFullInstructionSelector, AmdgpuGfxVersion,
    AmdgpuImageOp, AmdgpuMemOp,
};
pub use amdgpu_kernel_lowering::{AmdgpuKernelDescriptor, AmdgpuKernelLowering, AmdgpuWorkItemId};
pub use amdgpu_mc_encoder::AmdgpuMCEncoder;
pub use amdgpu_register_info::{AmdgpuRegClass, AmdgpuRegisterDesc, AmdgpuRegisterInfo};
pub use amdgpu_target_machine::{
    AmdgpuGeneration, AmdgpuIsaVersion, AmdgpuSubtargetFeatures, AmdgpuTargetMachine,
};

/// Maximum number of SGPRs per wave (GFX9+ supports up to 104).
pub const AMDGPU_MAX_SGPRS: u32 = 104;

/// Maximum number of VGPRs per wave (256).
pub const AMDGPU_MAX_VGPRS: u32 = 256;

/// Wavefront size (always 64 for GCN, 32 for RDNA in wave32 mode).
pub const AMDGPU_WAVEFRONT_SIZE: u32 = 64;

/// Local Data Share size in bytes (64 KiB per CU).
pub const AMDGPU_LDS_SIZE: u32 = 65536;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_amdgpu_constants() {
        assert_eq!(AMDGPU_MAX_SGPRS, 104);
        assert_eq!(AMDGPU_MAX_VGPRS, 256);
        assert_eq!(AMDGPU_WAVEFRONT_SIZE, 64);
        assert_eq!(AMDGPU_LDS_SIZE, 65536);
    }

    #[test]
    fn test_register_info_exists() {
        let info = AmdgpuRegisterInfo::new();
        assert_eq!(info.count(), 651);
    }

    #[test]
    fn test_instr_info_exists() {
        let info = AmdgpuInstrInfo::new();
        assert!(info.count() >= 60);
    }

    #[test]
    fn test_encoder_exists() {
        let mut enc = AmdgpuMCEncoder::new();
        let bytes = enc.encode(AmdgpuOpcode::SNop, &[0]);
        assert_eq!(bytes.len(), 4);
    }

    #[test]
    fn test_target_machine_exists() {
        let tm = AmdgpuTargetMachine::from_cpu("gfx900").unwrap();
        assert!(tm.is_gcn());
    }
}