llvm-native-core 0.1.15

LLVM-native core semantic engine — IR, CodeGen, X86 MC, Clang frontend pipeline
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//! MSP430 Target Backend — Texas Instruments 16-bit ultra-low-power MCU.
//!
//! Complete register information, instruction set metadata, instruction
//! selection, MC encoding, and assembly printer for the MSP430 and
//! MSP430X microcontroller families.
//!
//! Clean-room behavioral reconstruction from the MSP430x1xx/MSP430x2xx
//! Family User's Guide, the MSP430 Assembly Language Tools User's Guide,
//! and the MSP430 ABI specification. Zero LLVM source consultation.
//!
//! Architecture coverage:
//! - MSP430: 16-bit core with 27 core instructions + 24 emulated
//! - MSP430X: 20-bit extensions (MOVA, CALLA, PUSHM, POPM, etc.)
//! - Variable instruction length: 16-bit, 32-bit, 48-bit instructions
//! - Constant generators: CG1 (2), CG2 (4), CG3 (8), CG4 (-1)

pub mod msp430_asm_printer;
pub mod msp430_instr_info;
pub mod msp430_isel;
pub mod msp430_mc_encoder;
pub mod msp430_register_info;
pub mod msp430_x86_bridge;

pub use msp430_asm_printer::Msp430AsmPrinter;
pub use msp430_instr_info::{Msp430InstrDesc, Msp430InstrInfo, Msp430Opcode, Msp430OperandType};
pub use msp430_isel::Msp430InstructionSelector;
pub use msp430_mc_encoder::Msp430MCEncoder;
pub use msp430_register_info::{
    Msp430RegClass, Msp430RegisterInfo, MSP430_GPR_BASE, MSP430_GPR_COUNT, MSP430_MAX_REG_ID,
};

/// MSP430 is little-endian.
pub const MSP430_ENDIANNESS: &str = "little";

/// MSP430 stack alignment (2 bytes).
pub const MSP430_STACK_ALIGNMENT: u32 = 2;

/// MSP430 red zone size (none defined).
pub const MSP430_RED_ZONE_SIZE: u32 = 0;

/// Default MSP430 page size (not applicable for bare metal, but 64 KiB).
pub const MSP430_PAGE_SIZE: u32 = 65536;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_msp430_constants() {
        assert_eq!(MSP430_ENDIANNESS, "little");
        assert_eq!(MSP430_STACK_ALIGNMENT, 2);
        assert_eq!(MSP430_RED_ZONE_SIZE, 0);
        assert_eq!(MSP430_PAGE_SIZE, 65536);
    }
}