llvm-native-core 0.1.15

//! MIPS Target Backend — complete register information,
//! instruction set metadata, instruction selection, MC encoding,
//! and assembly printer for the MIPS32/MIPS64 architecture family.
//!
//! Clean-room behavioral reconstruction from the MIPS32/MIPS64
//! Architecture for Programmers Volumes I-III, the MIPS ABI
//! Supplement, and the SEE MIPS Run reference. Zero LLVM source
//! code consultation.
//!
//! Architecture coverage:
//! - MIPS32 Release 2: base 32-bit integer instruction set
//! - MIPS64 Release 2: 64-bit integer extensions
//! - FPU: single-precision (S) and double-precision (D) operations
//! - Pseudo-instructions: NOP, MOVE, LI, LA, B, BGE, BLT, BGT, BLE
//! - ABIs: O32, N32, N64

pub mod mips_asm_printer;
pub mod mips_instr_info;
pub mod mips_isel;
pub mod mips_mc_encoder;
pub mod mips_msa_isel;
pub mod mips_register_info;
pub mod mips_x86_bridge;

// Re-export key types for convenience
pub use mips_asm_printer::MipsAsmPrinter;
pub use mips_instr_info::{MipsInstrDesc, MipsInstrInfo, MipsOpcode, MipsOperandType};
pub use mips_isel::MipsInstructionSelector;
pub use mips_mc_encoder::MipsMCEncoder;
pub use mips_register_info::{
    MipsRegClass, MipsRegisterInfo, MIPS_FPR_BASE, MIPS_FPR_COUNT, MIPS_GPR_BASE, MIPS_GPR_COUNT,
    MIPS_MAX_REG_ID,
};

/// MIPS endianness can be configured as big-endian or little-endian.
/// The default for MIPS Linux targets is big-endian.
pub const MIPS_ENDIANNESS: &str = "big";

/// MIPS stack alignment (8 bytes for O32, 16 bytes for N32/N64).
pub const MIPS_STACK_ALIGNMENT: u32 = 16;

/// MIPS red zone size (none defined by ABI).
pub const MIPS_RED_ZONE_SIZE: u32 = 0;

/// Default MIPS page size (4 KiB).
pub const MIPS_PAGE_SIZE: u32 = 4096;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_mips_constants() {
        assert_eq!(MIPS_ENDIANNESS, "big");
        assert_eq!(MIPS_STACK_ALIGNMENT, 16);
        assert_eq!(MIPS_RED_ZONE_SIZE, 0);
        assert_eq!(MIPS_PAGE_SIZE, 4096);
    }
}