llvm-native-core 0.1.15

//! AArch64 SVE2 Instruction Selection Table
//!
//! Declarative ISel patterns for Scalable Vector Extension 2 (SVE2)
//! instructions. Extends the SVE ISel table with SVE2-specific operations
//! including saturating arithmetic, complex multiply-add, narrowing,
//! pairwise, bitwise selection, histogram, character match, cryptographic
//! acceleration, table lookup, and permute operations.
//!
//! Clean-room behavioural reconstruction from:
//! - Arm Architecture Reference Manual Supplement — SVE2
//! - Arm A64 ISA XML descriptions
//! - Black-box oracle interrogation
//! - Zero LLVM source code consultation

use crate::arm::arm_instr_info::ArmOpcode;
use crate::opcode::Opcode;
use std::collections::HashMap;

use super::arm_isel_table::{ImmConstraint, IselOperand, IselPattern, IselStats};

// ============================================================================
// SVE2 ISel Table
// ============================================================================

/// Complete SVE2 ISel table.
pub struct SVE2IselTable {
    /// All SVE2 ISel patterns.
    pub patterns: Vec<IselPattern>,
    /// ISel statistics.
    pub stats: IselStats,
}

/// Create the SVE2 ISel pattern table.
pub fn sve2_isel_table() -> Vec<IselPattern> {
    let mut table = Vec::new();

    // ================================================================
    // SVE2 Saturating Integer — SADD/SSUB (signed saturating add/sub)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sadd z.b, p/m, z.b, z.b — SVE2 signed saturating add 8-bit",
        result_opcode: ArmOpcode::SADD_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sadd z.h, p/m, z.h, z.h — SVE2 signed saturating add 16-bit",
        result_opcode: ArmOpcode::SADD_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sadd z.s, p/m, z.s, z.s — SVE2 signed saturating add 32-bit",
        result_opcode: ArmOpcode::SADD_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sadd z.d, p/m, z.d, z.d — SVE2 signed saturating add 64-bit",
        result_opcode: ArmOpcode::SADD_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "ssub z.b, p/m, z.b, z.b — SVE2 signed saturating sub 8-bit",
        result_opcode: ArmOpcode::SSUB_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "ssub z.h, p/m, z.h, z.h — SVE2 signed saturating sub 16-bit",
        result_opcode: ArmOpcode::SSUB_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "ssub z.s, p/m, z.s, z.s — SVE2 signed saturating sub 32-bit",
        result_opcode: ArmOpcode::SSUB_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "ssub z.d, p/m, z.d, z.d — SVE2 signed saturating sub 64-bit",
        result_opcode: ArmOpcode::SSUB_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Unsigned — UADD/USUB
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uadd z.b, p/m, z.b, z.b — SVE2 unsigned saturating add 8-bit",
        result_opcode: ArmOpcode::UADD_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uadd z.h, p/m, z.h, z.h — SVE2 unsigned saturating add 16-bit",
        result_opcode: ArmOpcode::UADD_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uadd z.s, p/m, z.s, z.s — SVE2 unsigned saturating add 32-bit",
        result_opcode: ArmOpcode::UADD_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uadd z.d, p/m, z.d, z.d — SVE2 unsigned saturating add 64-bit",
        result_opcode: ArmOpcode::UADD_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "usub z.b, p/m, z.b, z.b — SVE2 unsigned saturating sub 8-bit",
        result_opcode: ArmOpcode::USUB_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "usub z.h, p/m, z.h, z.h — SVE2 unsigned saturating sub 16-bit",
        result_opcode: ArmOpcode::USUB_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "usub z.s, p/m, z.s, z.s — SVE2 unsigned saturating sub 32-bit",
        result_opcode: ArmOpcode::USUB_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "usub z.d, p/m, z.d, z.d — SVE2 unsigned saturating sub 64-bit",
        result_opcode: ArmOpcode::USUB_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Accumulate — SUQADD/USQADD
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "suqadd z.b, p/m, z.b, z.b — SVE2 signed saturating accumulate unsigned 8-bit",
        result_opcode: ArmOpcode::SUQADD_Z,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "suqadd z.h, p/m, z.h, z.h — SVE2 signed saturating accumulate unsigned 16-bit",
        result_opcode: ArmOpcode::SUQADD_Z,
        priority: 109,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "suqadd z.s, p/m, z.s, z.s — SVE2 signed saturating accumulate unsigned 32-bit",
        result_opcode: ArmOpcode::SUQADD_Z,
        priority: 110,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "suqadd z.d, p/m, z.d, z.d — SVE2 signed saturating accumulate unsigned 64-bit",
        result_opcode: ArmOpcode::SUQADD_Z,
        priority: 111,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "usqadd z.b, p/m, z.b, z.b — SVE2 unsigned saturating accumulate signed 8-bit",
        result_opcode: ArmOpcode::USQADD_Z,
        priority: 112,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "usqadd z.h, p/m, z.h, z.h — SVE2 unsigned saturating accumulate signed 16-bit",
        result_opcode: ArmOpcode::USQADD_Z,
        priority: 113,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "usqadd z.s, p/m, z.s, z.s — SVE2 unsigned saturating accumulate signed 32-bit",
        result_opcode: ArmOpcode::USQADD_Z,
        priority: 114,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "usqadd z.d, p/m, z.d, z.d — SVE2 unsigned saturating accumulate signed 64-bit",
        result_opcode: ArmOpcode::USQADD_Z,
        priority: 115,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Signed/Unsigned — SQADD/UQADD/SQSUB/UQSUB
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sqadd z.b, z.b, z.b — SVE2 signed saturating add (unpredicated) 8-bit",
        result_opcode: ArmOpcode::SQADD_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sqadd z.h, z.h, z.h — SVE2 signed saturating add (unpredicated) 16-bit",
        result_opcode: ArmOpcode::SQADD_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sqadd z.s, z.s, z.s — SVE2 signed saturating add (unpredicated) 32-bit",
        result_opcode: ArmOpcode::SQADD_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "sqadd z.d, z.d, z.d — SVE2 signed saturating add (unpredicated) 64-bit",
        result_opcode: ArmOpcode::SQADD_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uqadd z.b, z.b, z.b — SVE2 unsigned saturating add (unpredicated) 8-bit",
        result_opcode: ArmOpcode::UQADD_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uqadd z.h, z.h, z.h — SVE2 unsigned saturating add (unpredicated) 16-bit",
        result_opcode: ArmOpcode::UQADD_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uqadd z.s, z.s, z.s — SVE2 unsigned saturating add (unpredicated) 32-bit",
        result_opcode: ArmOpcode::UQADD_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "uqadd z.d, z.d, z.d — SVE2 unsigned saturating add (unpredicated) 64-bit",
        result_opcode: ArmOpcode::UQADD_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "sqsub z.b, z.b, z.b — SVE2 signed saturating sub (unpredicated) 8-bit",
        result_opcode: ArmOpcode::SQSUB_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "sqsub z.h, z.h, z.h — SVE2 signed saturating sub (unpredicated) 16-bit",
        result_opcode: ArmOpcode::SQSUB_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "sqsub z.s, z.s, z.s — SVE2 signed saturating sub (unpredicated) 32-bit",
        result_opcode: ArmOpcode::SQSUB_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "sqsub z.d, z.d, z.d — SVE2 signed saturating sub (unpredicated) 64-bit",
        result_opcode: ArmOpcode::SQSUB_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "uqsub z.b, z.b, z.b — SVE2 unsigned saturating sub (unpredicated) 8-bit",
        result_opcode: ArmOpcode::UQSUB_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "uqsub z.h, z.h, z.h — SVE2 unsigned saturating sub (unpredicated) 16-bit",
        result_opcode: ArmOpcode::UQSUB_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "uqsub z.s, z.s, z.s — SVE2 unsigned saturating sub (unpredicated) 32-bit",
        result_opcode: ArmOpcode::UQSUB_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Sub,
        description: "uqsub z.d, z.d, z.d — SVE2 unsigned saturating sub (unpredicated) 64-bit",
        result_opcode: ArmOpcode::UQSUB_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Complex Integer — CADD (complex addition with rotation)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.b, z.b, z.b, #90 — SVE2 complex add rotate 90° 8-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.h, z.h, z.h, #90 — SVE2 complex add rotate 90° 16-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.s, z.s, z.s, #90 — SVE2 complex add rotate 90° 32-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.b, z.b, z.b, #270 — SVE2 complex add rotate 270° 8-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.h, z.h, z.h, #270 — SVE2 complex add rotate 270° 16-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "cadd z.s, z.s, z.s, #270 — SVE2 complex add rotate 270° 32-bit",
        result_opcode: ArmOpcode::CADD_SVE,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Complex Multiply-Add — CMLA (complex multiply-add with rotation)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.b, z.b, z.b, #0 — SVE2 complex multiply-add rotate 0° 8-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.h, z.h, z.h, #0 — SVE2 complex multiply-add rotate 0° 16-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.s, z.s, z.s, #0 — SVE2 complex multiply-add rotate 0° 32-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.b, z.b, z.b, #90 — SVE2 complex multiply-add rotate 90° 8-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.h, z.h, z.h, #90 — SVE2 complex multiply-add rotate 90° 16-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.s, z.s, z.s, #90 — SVE2 complex multiply-add rotate 90° 32-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.b, z.b, z.b, #180 — SVE2 complex multiply-add rotate 180° 8-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.h, z.h, z.h, #180 — SVE2 complex multiply-add rotate 180° 16-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.s, z.s, z.s, #180 — SVE2 complex multiply-add rotate 180° 32-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.b, z.b, z.b, #270 — SVE2 complex multiply-add rotate 270° 8-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 109,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.h, z.h, z.h, #270 — SVE2 complex multiply-add rotate 270° 16-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 110,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "cmla z.s, z.s, z.s, #270 — SVE2 complex multiply-add rotate 270° 32-bit",
        result_opcode: ArmOpcode::CMLA_SVE,
        priority: 111,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Rounding Doubling Multiply-Add High — SQRDMLAH
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlah z.b, z.b, z.b — SVE2 saturating rounding doubling MLA high 8-bit",
        result_opcode: ArmOpcode::SQRDMLAH_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlah z.h, z.h, z.h — SVE2 saturating rounding doubling MLA high 16-bit",
        result_opcode: ArmOpcode::SQRDMLAH_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlah z.s, z.s, z.s — SVE2 saturating rounding doubling MLA high 32-bit",
        result_opcode: ArmOpcode::SQRDMLAH_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Rounding Doubling Multiply-Subtract High — SQRDMLSH
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlsh z.b, z.b, z.b — SVE2 saturating rounding doubling MLS high 8-bit",
        result_opcode: ArmOpcode::SQRDMLSH_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlsh z.h, z.h, z.h — SVE2 saturating rounding doubling MLS high 16-bit",
        result_opcode: ArmOpcode::SQRDMLSH_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqrdmlsh z.s, z.s, z.s — SVE2 saturating rounding doubling MLS high 32-bit",
        result_opcode: ArmOpcode::SQRDMLSH_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Indexed Multiply — MUL (indexed)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mul z.h, z.h, z.h[i] — SVE2 indexed multiply 16-bit",
        result_opcode: ArmOpcode::MUL_I_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mul z.s, z.s, z.s[i] — SVE2 indexed multiply 32-bit",
        result_opcode: ArmOpcode::MUL_I_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mul z.d, z.d, z.d[i] — SVE2 indexed multiply 64-bit",
        result_opcode: ArmOpcode::MUL_I_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Indexed Multiply-Add — MLA (indexed)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mla z.h, z.h, z.h[i] — SVE2 indexed multiply-add 16-bit",
        result_opcode: ArmOpcode::MLA_I_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mla z.s, z.s, z.s[i] — SVE2 indexed multiply-add 32-bit",
        result_opcode: ArmOpcode::MLA_I_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mla z.d, z.d, z.d[i] — SVE2 indexed multiply-add 64-bit",
        result_opcode: ArmOpcode::MLA_I_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Indexed Multiply-Subtract — MLS (indexed)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mls z.h, z.h, z.h[i] — SVE2 indexed multiply-subtract 16-bit",
        result_opcode: ArmOpcode::MLS_I_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mls z.s, z.s, z.s[i] — SVE2 indexed multiply-subtract 32-bit",
        result_opcode: ArmOpcode::MLS_I_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "mls z.d, z.d, z.d[i] — SVE2 indexed multiply-subtract 64-bit",
        result_opcode: ArmOpcode::MLS_I_Z,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Widening Multiply-Subtract Long — SMLSL/UMLSL
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smlslb z.d, z.s, z.s — SVE2 signed multiply-subtract long bottom 32→64",
        result_opcode: ArmOpcode::SMLSLB_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smlslt z.d, z.s, z.s — SVE2 signed multiply-subtract long top 32→64",
        result_opcode: ArmOpcode::SMLSLT_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umlslb z.d, z.s, z.s — SVE2 unsigned multiply-subtract long bottom 32→64",
        result_opcode: ArmOpcode::UMLSLB_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umlslt z.d, z.s, z.s — SVE2 unsigned multiply-subtract long top 32→64",
        result_opcode: ArmOpcode::UMLSLT_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Doubling Multiply-Add Long — SQDMLAL/UQDMLAL
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqdmlalb z.d, z.s, z.s — SVE2 saturating doubling MLA long bottom 32→64",
        result_opcode: ArmOpcode::SQDMLALB_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sqdmlalt z.d, z.s, z.s — SVE2 saturating doubling MLA long top 32→64",
        result_opcode: ArmOpcode::SQDMLALT_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uqdmlalb z.d, z.s, z.s — SVE2 unsigned saturating doubling MLA long bottom 32→64",
        result_opcode: ArmOpcode::UQDMLALB_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uqdmlalt z.d, z.s, z.s — SVE2 unsigned saturating doubling MLA long top 32→64",
        result_opcode: ArmOpcode::UQDMLALT_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Narrowing — SHRNB/SHRNT (shift right narrow)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnb z.b, z.h, #imm — SVE2 shift right narrow bottom 16→8",
        result_opcode: ArmOpcode::SHRNB,
        priority: 100,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnt z.b, z.h, #imm — SVE2 shift right narrow top 16→8",
        result_opcode: ArmOpcode::SHRNT,
        priority: 101,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnb z.h, z.s, #imm — SVE2 shift right narrow bottom 32→16",
        result_opcode: ArmOpcode::SHRNB,
        priority: 102,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnt z.h, z.s, #imm — SVE2 shift right narrow top 32→16",
        result_opcode: ArmOpcode::SHRNT,
        priority: 103,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnb z.s, z.d, #imm — SVE2 shift right narrow bottom 64→32",
        result_opcode: ArmOpcode::SHRNB,
        priority: 104,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount64),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "shrnt z.s, z.d, #imm — SVE2 shift right narrow top 64→32",
        result_opcode: ArmOpcode::SHRNT,
        priority: 105,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount64),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Saturating Narrowing — SQSHRN/SQSHRUN/UQSHRN
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "sqshrnb z.b, z.h, #imm — SVE2 saturating shift right narrow bottom 16→8",
        result_opcode: ArmOpcode::SQSHRUNB,
        priority: 100,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "sqshrunt z.b, z.h, #imm — SVE2 saturating shift right narrow top 16→8",
        result_opcode: ArmOpcode::SQSHRUNT,
        priority: 101,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "sqshrnb z.h, z.s, #imm — SVE2 saturating shift right narrow bottom 32→16",
        result_opcode: ArmOpcode::SQSHRUNB,
        priority: 102,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "sqshrunt z.h, z.s, #imm — SVE2 saturating shift right narrow top 32→16",
        result_opcode: ArmOpcode::SQSHRUNT,
        priority: 103,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "uqshrnb z.b, z.h, #imm — SVE2 unsigned saturating shift right narrow bottom 16→8",
        result_opcode: ArmOpcode::UQSHRNB,
        priority: 104,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "uqshrnt z.b, z.h, #imm — SVE2 unsigned saturating shift right narrow top 16→8",
        result_opcode: ArmOpcode::UQSHRNT,
        priority: 105,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "uqshrnb z.h, z.s, #imm — SVE2 unsigned saturating shift right narrow bottom 32→16",
        result_opcode: ArmOpcode::UQSHRNB,
        priority: 106,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::AShr,
        description: "uqshrnt z.h, z.s, #imm — SVE2 unsigned saturating shift right narrow top 32→16",
        result_opcode: ArmOpcode::UQSHRNT,
        priority: 107,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Adding Narrow High — ADDHNB/ADDHNT
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnb z.b, z.h, z.h — SVE2 add narrow high bottom 16→8",
        result_opcode: ArmOpcode::ADDHNB,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnt z.b, z.h, z.h — SVE2 add narrow high top 16→8",
        result_opcode: ArmOpcode::ADDHNT,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnb z.h, z.s, z.s — SVE2 add narrow high bottom 32→16",
        result_opcode: ArmOpcode::ADDHNB,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnt z.h, z.s, z.s — SVE2 add narrow high top 32→16",
        result_opcode: ArmOpcode::ADDHNT,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnb z.s, z.d, z.d — SVE2 add narrow high bottom 64→32",
        result_opcode: ArmOpcode::ADDHNB,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addhnt z.s, z.d, z.d — SVE2 add narrow high top 64→32",
        result_opcode: ArmOpcode::ADDHNT,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Rounding Add Narrow High — RADDHNB/RADDHNT
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnb z.b, z.h, z.h — SVE2 rounding add narrow high bottom 16→8",
        result_opcode: ArmOpcode::RADDHNB,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnt z.b, z.h, z.h — SVE2 rounding add narrow high top 16→8",
        result_opcode: ArmOpcode::RADDHNT,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnb z.h, z.s, z.s — SVE2 rounding add narrow high bottom 32→16",
        result_opcode: ArmOpcode::RADDHNB,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnt z.h, z.s, z.s — SVE2 rounding add narrow high top 32→16",
        result_opcode: ArmOpcode::RADDHNT,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnb z.s, z.d, z.d — SVE2 rounding add narrow high bottom 64→32",
        result_opcode: ArmOpcode::RADDHNB,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "raddhnt z.s, z.d, z.d — SVE2 rounding add narrow high top 64→32",
        result_opcode: ArmOpcode::RADDHNT,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Pairwise Integer — ADDP/SMAXP/UMAXP/SMINP/UMINP
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addp z.b, p/m, z.b, z.b — SVE2 add pairwise 8-bit",
        result_opcode: ArmOpcode::ADDP_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addp z.h, p/m, z.h, z.h — SVE2 add pairwise 16-bit",
        result_opcode: ArmOpcode::ADDP_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addp z.s, p/m, z.s, z.s — SVE2 add pairwise 32-bit",
        result_opcode: ArmOpcode::ADDP_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Add,
        description: "addp z.d, p/m, z.d, z.d — SVE2 add pairwise 64-bit",
        result_opcode: ArmOpcode::ADDP_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smaxp z.b, p/m, z.b, z.b — SVE2 signed max pairwise 8-bit",
        result_opcode: ArmOpcode::SMAXP_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smaxp z.h, p/m, z.h, z.h — SVE2 signed max pairwise 16-bit",
        result_opcode: ArmOpcode::SMAXP_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smaxp z.s, p/m, z.s, z.s — SVE2 signed max pairwise 32-bit",
        result_opcode: ArmOpcode::SMAXP_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "smaxp z.d, p/m, z.d, z.d — SVE2 signed max pairwise 64-bit",
        result_opcode: ArmOpcode::SMAXP_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umaxp z.b, p/m, z.b, z.b — SVE2 unsigned max pairwise 8-bit",
        result_opcode: ArmOpcode::UMAXP_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umaxp z.h, p/m, z.h, z.h — SVE2 unsigned max pairwise 16-bit",
        result_opcode: ArmOpcode::UMAXP_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umaxp z.s, p/m, z.s, z.s — SVE2 unsigned max pairwise 32-bit",
        result_opcode: ArmOpcode::UMAXP_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "umaxp z.d, p/m, z.d, z.d — SVE2 unsigned max pairwise 64-bit",
        result_opcode: ArmOpcode::UMAXP_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sminp z.b, p/m, z.b, z.b — SVE2 signed min pairwise 8-bit",
        result_opcode: ArmOpcode::SMINP_Z,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sminp z.h, p/m, z.h, z.h — SVE2 signed min pairwise 16-bit",
        result_opcode: ArmOpcode::SMINP_Z,
        priority: 109,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sminp z.s, p/m, z.s, z.s — SVE2 signed min pairwise 32-bit",
        result_opcode: ArmOpcode::SMINP_Z,
        priority: 110,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "sminp z.d, p/m, z.d, z.d — SVE2 signed min pairwise 64-bit",
        result_opcode: ArmOpcode::SMINP_Z,
        priority: 111,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uminp z.b, p/m, z.b, z.b — SVE2 unsigned min pairwise 8-bit",
        result_opcode: ArmOpcode::UMINP_Z,
        priority: 112,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uminp z.h, p/m, z.h, z.h — SVE2 unsigned min pairwise 16-bit",
        result_opcode: ArmOpcode::UMINP_Z,
        priority: 113,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uminp z.s, p/m, z.s, z.s — SVE2 unsigned min pairwise 32-bit",
        result_opcode: ArmOpcode::UMINP_Z,
        priority: 114,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Mul,
        description: "uminp z.d, p/m, z.d, z.d — SVE2 unsigned min pairwise 64-bit",
        result_opcode: ArmOpcode::UMINP_Z,
        priority: 115,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Pairwise Floating-Point — FADDP/FMAXP/FMINP/FMAXNMP/FMINNMP
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::FAdd,
        description: "faddp z.h, p/m, z.h, z.h — SVE2 FP add pairwise 16-bit",
        result_opcode: ArmOpcode::FADDP_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FAdd,
        description: "faddp z.s, p/m, z.s, z.s — SVE2 FP add pairwise 32-bit",
        result_opcode: ArmOpcode::FADDP_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FAdd,
        description: "faddp z.d, p/m, z.d, z.d — SVE2 FP add pairwise 64-bit",
        result_opcode: ArmOpcode::FADDP_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxp z.h, p/m, z.h, z.h — SVE2 FP max pairwise 16-bit",
        result_opcode: ArmOpcode::FMAXP_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxp z.s, p/m, z.s, z.s — SVE2 FP max pairwise 32-bit",
        result_opcode: ArmOpcode::FMAXP_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxp z.d, p/m, z.d, z.d — SVE2 FP max pairwise 64-bit",
        result_opcode: ArmOpcode::FMAXP_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminp z.h, p/m, z.h, z.h — SVE2 FP min pairwise 16-bit",
        result_opcode: ArmOpcode::FMINP_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminp z.s, p/m, z.s, z.s — SVE2 FP min pairwise 32-bit",
        result_opcode: ArmOpcode::FMINP_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminp z.d, p/m, z.d, z.d — SVE2 FP min pairwise 64-bit",
        result_opcode: ArmOpcode::FMINP_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxnmp z.h, p/m, z.h, z.h — SVE2 FP max-num pairwise 16-bit",
        result_opcode: ArmOpcode::FMAXNMP_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxnmp z.s, p/m, z.s, z.s — SVE2 FP max-num pairwise 32-bit",
        result_opcode: ArmOpcode::FMAXNMP_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fmaxnmp z.d, p/m, z.d, z.d — SVE2 FP max-num pairwise 64-bit",
        result_opcode: ArmOpcode::FMAXNMP_Z,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminnmp z.h, p/m, z.h, z.h — SVE2 FP min-num pairwise 16-bit",
        result_opcode: ArmOpcode::FMINNMP_Z,
        priority: 109,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminnmp z.s, p/m, z.s, z.s — SVE2 FP min-num pairwise 32-bit",
        result_opcode: ArmOpcode::FMINNMP_Z,
        priority: 110,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::FSub,
        description: "fminnmp z.d, p/m, z.d, z.d — SVE2 FP min-num pairwise 64-bit",
        result_opcode: ArmOpcode::FMINNMP_Z,
        priority: 111,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Bitwise Select/Insert/Clear — BSL/BIT/BIF
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Or,
        description: "bsl z.d, z.d, z.d, z.d — SVE2 bitwise select 64-bit",
        result_opcode: ArmOpcode::BSL_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Or,
        description: "bit z.d, z.d, z.d, z.d — SVE2 bitwise insert-if-true 64-bit",
        result_opcode: ArmOpcode::BIT_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Or,
        description: "bif z.d, z.d, z.d, z.d — SVE2 bitwise insert-if-false 64-bit",
        result_opcode: ArmOpcode::BIF_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 3-input XOR and Clear — EOR3/BCAX
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "eor3 z.d, z.d, z.d, z.d — SVE2 3-input XOR 64-bit",
        result_opcode: ArmOpcode::EOR3,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "bcax z.d, z.d, z.d, z.d — SVE2 bitwise clear-and-XOR 64-bit",
        result_opcode: ArmOpcode::BCAX,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Bitwise Rotate with XOR — XAR
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "xar z.d, z.d, z.d, #imm — SVE2 XOR-and-rotate 64-bit",
        result_opcode: ArmOpcode::XAR,
        priority: 100,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsShiftAmount64),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Histogram — HISTCNT (count in bins)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "histcnt z.s, p/z, z.s, z.s — SVE2 count in bins 32-bit",
        result_opcode: ArmOpcode::HISTCNT_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "histcnt z.d, p/z, z.d, z.d — SVE2 count in bins 64-bit",
        result_opcode: ArmOpcode::HISTCNT_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Histogram Segment — HISTSEG
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "histseg z.b, z.b — SVE2 histogram segment 8-bit",
        result_opcode: ArmOpcode::HISTSEG_Z,
        priority: 100,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Character Match — MATCH/NMATCH
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "match p.b, p/z, z.b, z.b — SVE2 character match 8-bit",
        result_opcode: ArmOpcode::MATCH_Z,
        priority: 100,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "match p.h, p/z, z.h, z.h — SVE2 character match 16-bit",
        result_opcode: ArmOpcode::MATCH_Z,
        priority: 101,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "nmatch p.b, p/z, z.b, z.b — SVE2 character no-match 8-bit",
        result_opcode: ArmOpcode::NMATCH_Z,
        priority: 102,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "nmatch p.h, p/z, z.h, z.h — SVE2 character no-match 16-bit",
        result_opcode: ArmOpcode::NMATCH_Z,
        priority: 103,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Compare Less-or-Equal with Zero — CMLE
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "cmle p.b, p/z, z.b, #0 — SVE2 compare signed <= zero 8-bit",
        result_opcode: ArmOpcode::CMLE_Z,
        priority: 100,
        num_operands: 2,
        imm_constraint: Some(ImmConstraint::IsZero),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "cmle p.h, p/z, z.h, #0 — SVE2 compare signed <= zero 16-bit",
        result_opcode: ArmOpcode::CMLE_Z,
        priority: 101,
        num_operands: 2,
        imm_constraint: Some(ImmConstraint::IsZero),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "cmle p.s, p/z, z.s, #0 — SVE2 compare signed <= zero 32-bit",
        result_opcode: ArmOpcode::CMLE_Z,
        priority: 102,
        num_operands: 2,
        imm_constraint: Some(ImmConstraint::IsZero),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::ICmp,
        description: "cmle p.d, p/z, z.d, #0 — SVE2 compare signed <= zero 64-bit",
        result_opcode: ArmOpcode::CMLE_Z,
        priority: 103,
        num_operands: 2,
        imm_constraint: Some(ImmConstraint::IsZero),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Crypto — SM4 Encryption
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sm4e z.s, z.s — SVE2 SM4 encryption 32-bit",
        result_opcode: ArmOpcode::SM4E_Z,
        priority: 100,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sm4ekey z.s, z.s, z.s — SVE2 SM4 key schedule 32-bit",
        result_opcode: ArmOpcode::SM4EKEY_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Crypto — SHA-256 Acceleration
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha256h z.s, z.s, z.s — SVE2 SHA-256 hash update 32-bit",
        result_opcode: ArmOpcode::SHA256H_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha256h2 z.s, z.s, z.s — SVE2 SHA-256 hash update part 2 32-bit",
        result_opcode: ArmOpcode::SHA256H2_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha256su0 z.s, z.s — SVE2 SHA-256 schedule update 0 32-bit",
        result_opcode: ArmOpcode::SHA256SU0_Z,
        priority: 102,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha256su1 z.s, z.s, z.s — SVE2 SHA-256 schedule update 1 32-bit",
        result_opcode: ArmOpcode::SHA256SU1_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Crypto — SHA-512 Acceleration
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha512h z.d, z.d, z.d — SVE2 SHA-512 hash update 64-bit",
        result_opcode: ArmOpcode::SHA512H_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha512h2 z.d, z.d, z.d — SVE2 SHA-512 hash update part 2 64-bit",
        result_opcode: ArmOpcode::SHA512H2_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha512su0 z.d, z.d — SVE2 SHA-512 schedule update 0 64-bit",
        result_opcode: ArmOpcode::SHA512SU0_Z,
        priority: 102,
        num_operands: 2,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Xor,
        description: "sha512su1 z.d, z.d, z.d — SVE2 SHA-512 schedule update 1 64-bit",
        result_opcode: ArmOpcode::SHA512SU1_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Table Lookup — TBL (multi-register table lookup)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbl z.b, {z.b, z.b}, z.b — SVE2 table lookup 2-reg 8-bit",
        result_opcode: ArmOpcode::TBL_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbl z.h, {z.h, z.h}, z.h — SVE2 table lookup 2-reg 16-bit",
        result_opcode: ArmOpcode::TBL_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbl z.s, {z.s, z.s}, z.s — SVE2 table lookup 2-reg 32-bit",
        result_opcode: ArmOpcode::TBL_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbl z.d, {z.d, z.d}, z.d — SVE2 table lookup 2-reg 64-bit",
        result_opcode: ArmOpcode::TBL_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Table Lookup Extension — TBX
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbx z.b, {z.b, z.b}, z.b — SVE2 table lookup extension 2-reg 8-bit",
        result_opcode: ArmOpcode::TBX_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbx z.h, {z.h, z.h}, z.h — SVE2 table lookup extension 2-reg 16-bit",
        result_opcode: ArmOpcode::TBX_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbx z.s, {z.s, z.s}, z.s — SVE2 table lookup extension 2-reg 32-bit",
        result_opcode: ArmOpcode::TBX_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Load,
        description: "tbx z.d, {z.d, z.d}, z.d — SVE2 table lookup extension 2-reg 64-bit",
        result_opcode: ArmOpcode::TBX_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Permute — ZIP1/ZIP2 (interleave)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip1 z.b, z.b, z.b — SVE2 interleave lower half 8-bit",
        result_opcode: ArmOpcode::ZIP1_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip1 z.h, z.h, z.h — SVE2 interleave lower half 16-bit",
        result_opcode: ArmOpcode::ZIP1_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip1 z.s, z.s, z.s — SVE2 interleave lower half 32-bit",
        result_opcode: ArmOpcode::ZIP1_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip1 z.d, z.d, z.d — SVE2 interleave lower half 64-bit",
        result_opcode: ArmOpcode::ZIP1_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip2 z.b, z.b, z.b — SVE2 interleave upper half 8-bit",
        result_opcode: ArmOpcode::ZIP2_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip2 z.h, z.h, z.h — SVE2 interleave upper half 16-bit",
        result_opcode: ArmOpcode::ZIP2_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip2 z.s, z.s, z.s — SVE2 interleave upper half 32-bit",
        result_opcode: ArmOpcode::ZIP2_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "zip2 z.d, z.d, z.d — SVE2 interleave upper half 64-bit",
        result_opcode: ArmOpcode::ZIP2_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Permute — UZP1/UZP2 (deinterleave)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp1 z.b, z.b, z.b — SVE2 deinterleave even elements 8-bit",
        result_opcode: ArmOpcode::UZP1_Z,
        priority: 108,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp1 z.h, z.h, z.h — SVE2 deinterleave even elements 16-bit",
        result_opcode: ArmOpcode::UZP1_Z,
        priority: 109,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp1 z.s, z.s, z.s — SVE2 deinterleave even elements 32-bit",
        result_opcode: ArmOpcode::UZP1_Z,
        priority: 110,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp1 z.d, z.d, z.d — SVE2 deinterleave even elements 64-bit",
        result_opcode: ArmOpcode::UZP1_Z,
        priority: 111,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp2 z.b, z.b, z.b — SVE2 deinterleave odd elements 8-bit",
        result_opcode: ArmOpcode::UZP2_Z,
        priority: 112,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp2 z.h, z.h, z.h — SVE2 deinterleave odd elements 16-bit",
        result_opcode: ArmOpcode::UZP2_Z,
        priority: 113,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp2 z.s, z.s, z.s — SVE2 deinterleave odd elements 32-bit",
        result_opcode: ArmOpcode::UZP2_Z,
        priority: 114,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "uzp2 z.d, z.d, z.d — SVE2 deinterleave odd elements 64-bit",
        result_opcode: ArmOpcode::UZP2_Z,
        priority: 115,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Permute — TRN1/TRN2 (transpose)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn1 z.b, z.b, z.b — SVE2 transpose even elements 8-bit",
        result_opcode: ArmOpcode::TRN1_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn1 z.h, z.h, z.h — SVE2 transpose even elements 16-bit",
        result_opcode: ArmOpcode::TRN1_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn1 z.s, z.s, z.s — SVE2 transpose even elements 32-bit",
        result_opcode: ArmOpcode::TRN1_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn1 z.d, z.d, z.d — SVE2 transpose even elements 64-bit",
        result_opcode: ArmOpcode::TRN1_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn2 z.b, z.b, z.b — SVE2 transpose odd elements 8-bit",
        result_opcode: ArmOpcode::TRN2_Z,
        priority: 104,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn2 z.h, z.h, z.h — SVE2 transpose odd elements 16-bit",
        result_opcode: ArmOpcode::TRN2_Z,
        priority: 105,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn2 z.s, z.s, z.s — SVE2 transpose odd elements 32-bit",
        result_opcode: ArmOpcode::TRN2_Z,
        priority: 106,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "trn2 z.d, z.d, z.d — SVE2 transpose odd elements 64-bit",
        result_opcode: ArmOpcode::TRN2_Z,
        priority: 107,
        num_operands: 3,
        imm_constraint: None,
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    // ================================================================
    // SVE2 Permute — EXT (extract)
    // ================================================================
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "ext z.b, z.b, z.b, #imm — SVE2 extract vector 8-bit",
        result_opcode: ArmOpcode::EXT_Z,
        priority: 100,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsImm8),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "ext z.h, z.h, z.h, #imm — SVE2 extract vector 16-bit",
        result_opcode: ArmOpcode::EXT_Z,
        priority: 101,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsImm8),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "ext z.s, z.s, z.s, #imm — SVE2 extract vector 32-bit",
        result_opcode: ArmOpcode::EXT_Z,
        priority: 102,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsImm8),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });
    table.push(IselPattern {
        ir_opcode: Opcode::Call,
        description: "ext z.d, z.d, z.d, #imm — SVE2 extract vector 64-bit",
        result_opcode: ArmOpcode::EXT_Z,
        priority: 103,
        num_operands: 3,
        imm_constraint: Some(ImmConstraint::IsImm8),
        is_two_address: false,
        required_feature: Some("sve2"),
        cond: None,
    });

    table
}

// ============================================================================
// SVE2 ISel Pattern Matching Engine
// ============================================================================

/// SVE2 ISel matching engine.
pub struct SVE2IselEngine {
    /// All SVE2 ISel patterns.
    pub patterns: Vec<IselPattern>,
    /// Target has SVE2.
    pub has_sve2: bool,
    /// ISel statistics.
    pub stats: IselStats,
}

impl SVE2IselEngine {
    /// Create a new SVE2 ISel engine.
    pub fn new(has_sve2: bool) -> Self {
        let mut patterns = sve2_isel_table();
        patterns.sort_by_key(|p| p.priority);
        Self {
            patterns,
            has_sve2,
            stats: IselStats::new(),
        }
    }

    /// Look up the best-matching SVE2 pattern for an IR opcode.
    pub fn lookup(
        &mut self,
        ir_opcode: Opcode,
        _operands: &[IselOperand],
        _imm_value: Option<i64>,
    ) -> Option<(ArmOpcode, &IselPattern)> {
        let opcode_id = ir_opcode as u32;

        for pattern in &self.patterns {
            if pattern.ir_opcode == ir_opcode {
                // Check SVE2 feature availability
                if let Some(feat) = pattern.required_feature {
                    if feat == "sve2" && !self.has_sve2 {
                        continue;
                    }
                }

                // Check imm constraint
                if let Some(constraint) = &pattern.imm_constraint {
                    if let Some(val) = _imm_value {
                        if !super::arm_isel_table::evaluate_imm_constraint(constraint, val, true) {
                            continue;
                        }
                    } else {
                        continue;
                    }
                }

                self.stats.record_match(opcode_id);
                return Some((pattern.result_opcode, pattern));
            }
        }

        self.stats.record_miss(opcode_id);
        None
    }

    /// Get all SVE2 patterns for a given opcode.
    pub fn patterns_for(&self, ir_opcode: Opcode) -> Vec<&IselPattern> {
        self.patterns
            .iter()
            .filter(|p| p.ir_opcode == ir_opcode)
            .collect()
    }

    /// Get the number of patterns in the engine.
    pub fn pattern_count(&self) -> usize {
        self.patterns.len()
    }

    /// Get patterns grouped by category for analysis.
    pub fn patterns_by_feature(&self) -> HashMap<&str, usize> {
        let mut counts: HashMap<&str, usize> = HashMap::new();
        for p in &self.patterns {
            if let Some(feat) = p.required_feature {
                *counts.entry(feat).or_insert(0) += 1;
            }
        }
        counts
    }

    /// Coverage report for SVE2 ISel.
    pub fn coverage_report(&self, all_opcodes: &[Opcode]) -> String {
        let covered: std::collections::HashSet<_> =
            self.patterns.iter().map(|p| p.ir_opcode as u32).collect();
        let uncovered: Vec<_> = all_opcodes
            .iter()
            .filter(|op| !covered.contains(&(**op as u32)))
            .collect();
        format!(
            "SVE2 ISel Coverage: {}/{} opcodes covered ({} uncovered: {:?})",
            covered.len(),
            all_opcodes.len(),
            uncovered.len(),
            uncovered
        )
    }

    /// Detailed statistics including pattern count by IR opcode.
    pub fn detailed_stats(&self) -> String {
        let mut op_counts: HashMap<u32, usize> = HashMap::new();
        for p in &self.patterns {
            *op_counts.entry(p.ir_opcode as u32).or_insert(0) += 1;
        }
        let feat_counts = self.patterns_by_feature();
        format!(
            "SVE2 ISel: {} total patterns, {} unique IR opcodes, features: {:?}",
            self.patterns.len(),
            op_counts.len(),
            feat_counts
        )
    }
}

impl Default for SVE2IselEngine {
    fn default() -> Self {
        Self::new(false)
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_sve2_table_not_empty() {
        let table = sve2_isel_table();
        assert!(!table.is_empty());
        assert!(table.len() >= 100, "Expected at least 100 SVE2 patterns");
    }

    #[test]
    fn test_sve2_lookup_saturating_add() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Add, &[], None);
        assert!(result.is_some(), "SVE2 should match saturating Add");
    }

    #[test]
    fn test_sve2_lookup_cadd() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Add, &[], None);
        assert!(result.is_some());
    }

    #[test]
    fn test_sve2_lookup_cmla() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Mul, &[], None);
        assert!(result.is_some());
    }

    #[test]
    fn test_sve2_lookup_pairwise_fadd() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::FAdd, &[], None);
        assert!(result.is_some());
    }

    #[test]
    fn test_sve2_lookup_eor3() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Xor, &[], None);
        assert!(result.is_some());
    }

    #[test]
    fn test_sve2_lookup_histogram() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::ICmp, &[], None);
        assert!(result.is_some(), "SVE2 should match HISTCNT via ICmp");
    }

    #[test]
    fn test_sve2_lookup_crypto_sm4() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Xor, &[], None);
        assert!(result.is_some(), "SM4E should be found");
    }

    #[test]
    fn test_sve2_lookup_sha256() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Xor, &[], None);
        assert!(result.is_some(), "SHA-256 should be found");
    }

    #[test]
    fn test_sve2_lookup_permute_zip() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Call, &[], None);
        assert!(result.is_some(), "ZIP/UZP/TRN patterns should match Call");
    }

    #[test]
    fn test_sve2_feature_guard() {
        let mut engine = SVE2IselEngine::new(false);
        let result = engine.lookup(Opcode::Add, &[], None);
        // Without SVE2 enabled, no SVE2-specific patterns should match
        assert!(result.is_none());
    }

    #[test]
    fn test_sve2_pattern_count() {
        let engine = SVE2IselEngine::new(true);
        assert!(
            engine.pattern_count() >= 100,
            "Expected {} patterns, got {}",
            100,
            engine.pattern_count()
        );
    }

    #[test]
    fn test_sve2_patterns_by_feature() {
        let engine = SVE2IselEngine::new(true);
        let counts = engine.patterns_by_feature();
        assert!(counts.contains_key("sve2"), "Should have sve2 patterns");
        assert!(
            counts.get("sve2").copied().unwrap_or(0) >= 100,
            "SVE2 feature should have many patterns"
        );
    }

    #[test]
    fn test_sve2_coverage_report() {
        let engine = SVE2IselEngine::new(true);
        let all_ops = &[
            Opcode::Add,
            Opcode::Sub,
            Opcode::Mul,
            Opcode::FAdd,
            Opcode::FSub,
            Opcode::FMul,
            Opcode::Xor,
            Opcode::Or,
            Opcode::AShr,
            Opcode::ICmp,
            Opcode::Load,
            Opcode::Call,
        ];
        let report = engine.coverage_report(all_ops);
        assert!(report.contains("SVE2 ISel Coverage"));
    }

    #[test]
    fn test_sve2_detailed_stats() {
        let engine = SVE2IselEngine::new(true);
        let stats = engine.detailed_stats();
        assert!(stats.contains("SVE2 ISel"));
        assert!(stats.contains("patterns"));
    }

    #[test]
    fn test_sve2_lookup_sqrdmlah() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Mul, &[], None);
        assert!(result.is_some());
    }

    #[test]
    fn test_sve2_lookup_narrowing() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::AShr, &[], None);
        assert!(result.is_some(), "Narrowing shifts should match AShr");
    }

    #[test]
    fn test_sve2_lookup_tbl() {
        let mut engine = SVE2IselEngine::new(true);
        let result = engine.lookup(Opcode::Load, &[], None);
        assert!(result.is_some(), "TBL/TBX should match Load");
    }
}