llvm-native-core 0.1.13

//! PowerPC Complete Instruction Selection — VSX, MMA, Prefix, DFP, BFP extensions.
//!
//! Clean-room behavioral reconstruction from the Power ISA (v3.0, v3.1).
//! Zero LLVM source code consultation.
//!
//! This module extends `ppc_isel` with full lowering for:
//! - VSX vector: single/double precision arithmetic, FMA, permute, load/store
//! - MMA matrix: accumulator tile operations, outer product, inter-lane communication
//! - Prefix: 8-byte prefixed instruction format
//! - DFP: decimal floating-point operations
//! - BFP: binary floating-point rounding and conversion
//!
//! # Key ISA References
//! | Extension   | Book       | Chapter |
//! |-------------|------------|---------|
//! | VSX         | Book I     | §7      |
//! | MMA         | Book II    | §8      |
//! | Prefix      | Book I     | §11     |
//! | DFP         | Book I     | §9      |
//! | BFP         | Book I     | §6      |

use super::ppc_instr_info::PpcOpcode;
use super::ppc_register_info::*;
use crate::codegen::*;
use crate::opcode::Opcode;
use crate::value::Value;
use std::collections::HashMap;

// ============================================================================
// VSX Vector Scalar Extension Types
// ============================================================================

/// VSX element type for instruction selection
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum VsxElementType {
    /// 32-bit single-precision float
    SP,
    /// 64-bit double-precision float
    DP,
    /// 8-bit integer
    I8,
    /// 16-bit integer
    I16,
    /// 32-bit integer
    I32,
    /// 64-bit integer
    I64,
}

impl VsxElementType {
    pub fn size_bytes(self) -> u32 {
        match self {
            VsxElementType::SP => 4,
            VsxElementType::DP => 8,
            VsxElementType::I8 => 1,
            VsxElementType::I16 => 2,
            VsxElementType::I32 => 4,
            VsxElementType::I64 => 8,
        }
    }

    pub fn is_float(self) -> bool {
        matches!(self, VsxElementType::SP | VsxElementType::DP)
    }
}

// ============================================================================
// VSX Horizontal/Reduction Operations
// ============================================================================

/// VSX reduction operation type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum VsxReductionOp {
    Sum,
    Product,
    Min,
    Max,
    MinIndex,
    MaxIndex,
}

// ============================================================================
// MMA Matrix Math Accelerator Types
// ============================================================================

/// MMA accumulator tile identifier (8 accumulator tiles: acc0-acc7)
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct MmaAccTile(pub u8);

impl MmaAccTile {
    pub const COUNT: u8 = 8;
    pub fn new(idx: u8) -> Option<Self> {
        if idx < Self::COUNT { Some(MmaAccTile(idx)) } else { None }
    }
    pub fn index(self) -> u8 { self.0 }
    pub fn all() -> Vec<MmaAccTile> {
        (0..Self::COUNT).filter_map(MmaAccTile::new).collect()
    }
}

/// MMA outer product operation type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum MmaOuterType {
    /// 4-bit integer outer product (8x4x4 tiles)
    I4,
    /// 8-bit integer outer product (4x4x4 tiles)
    I8,
    /// 16-bit integer outer product (2x4x2 tiles)
    I16,
    /// 32-bit float outer product (4x4x2 tiles)
    F32,
    /// 64-bit float outer product (4x4x2 tiles)
    F64,
}

impl MmaOuterType {
    pub fn accumulation_width(self) -> u32 {
        match self {
            MmaOuterType::I4 | MmaOuterType::I8 | MmaOuterType::I16 |
            MmaOuterType::F32 => 32,
            MmaOuterType::F64 => 64,
        }
    }
    pub fn operand_width(self) -> u32 {
        match self {
            MmaOuterType::I4 => 4,
            MmaOuterType::I8 => 8,
            MmaOuterType::I16 => 16,
            MmaOuterType::F32 => 32,
            MmaOuterType::F64 => 64,
        }
    }
}

/// MMA inter-lane communication type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum MmaInterLane {
    /// 4-element inter-lane (acc[0:3] -> VSRs)
    Inter4,
    /// 8-element inter-lane (acc[4:7] -> VSRs)
    Inter8,
}

// ============================================================================
// Prefix Instruction Support Types
// ============================================================================

/// Prefix instruction type (8-byte prefixed instructions)
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum PrefixType {
    /// Prefixed Load/Store: plwz, pstw, pld, pstd, plfs, plfd, pstfs, pstfd
    LoadStore,
    /// Prefixed Arithmetic: paddi, psubi, pli
    Arithmetic,
    /// Prefixed Load Half/Algebraic: plha, plhz, plwa
    LoadExtended,
}

impl PrefixType {
    pub fn has_prefix_word(self) -> bool { true }
    pub fn prefix_word_mls(self) -> u8 {
        match self {
            PrefixType::LoadStore => 0b10,
            PrefixType::Arithmetic => 0b00,
            PrefixType::LoadExtended => 0b10,
        }
    }
}

// ============================================================================
// Decimal Floating-Point (DFP) Support Types
// ============================================================================

/// DFP rounding mode
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DfpRoundingMode {
    RoundNearestEven,
    RoundTowardZero,
    RoundTowardPositive,
    RoundTowardNegative,
    RoundNearestTiesAway,
    RoundNearestTiesEven50,
}

/// DFP test group type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DfpTestGroup {
    /// Test if operand is zero
    Zero,
    /// Test if operand is special (infinity, NaN)
    Special,
    /// Test if comparison is less than or greater than
    Ordered,
}

/// DFP data class test
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum DfpClassTest {
    SignalingNaN,
    QuietNaN,
    PositiveInfinity,
    NegativeInfinity,
    PositiveNormal,
    NegativeNormal,
    PositiveSubnormal,
    NegativeSubnormal,
    PositiveZero,
    NegativeZero,
}

// ============================================================================
// Binary Floating-Point (BFP) Rounding Operations
// ============================================================================

/// BFP rounding/convert operation type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum BfpConvertOp {
    /// Convert to 32-bit signed integer word with round toward zero
    Fctiwz,
    /// Convert to 32-bit signed integer word with round to nearest
    Fctiw,
    /// Convert to 64-bit signed integer doubleword with round toward zero
    Fctidz,
    /// Convert to 64-bit signed integer doubleword with round to nearest
    Fctid,
    /// Convert from 64-bit signed integer to double-precision float
    Fcfid,
    /// Convert to 32-bit unsigned integer word with round toward zero
    Fctiwuz,
    /// Convert to 32-bit unsigned integer word with round to nearest
    Fctiwu,
    /// Convert to 64-bit unsigned integer doubleword with round toward zero
    Fctiduz,
    /// Convert to 64-bit unsigned integer doubleword with round to nearest
    Fctidu,
}

// ============================================================================
// VSX Permute Types
// ============================================================================

/// VSX permute control type
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum VsxPermuteOp {
    /// xxperm: full byte-level permute
    Permute,
    /// xxpermdi: doubleword permute immediate
    PermuteDI,
    /// xxspltw: splat word
    SplatWord,
    /// xxmrghw: merge high words
    MergeHighWord,
    /// xxmrglw: merge low words
    MergeLowWord,
    /// xxpermx: extended permute (ISA 3.0)
    PermuteX,
}

// ============================================================================
// VSX Load/Store Types
// ============================================================================

/// VSX load/store variant
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum VsxLoadStoreOp {
    /// lxv: indexed load vector
    LoadIndexed,
    /// stxv: indexed store vector
    StoreIndexed,
    /// lxvl: load vector left-justified with length
    LoadLeftLength,
    /// stxvl: store vector left-justified with length
    StoreLeftLength,
    /// lxvll: load vector left-justified with byte count
    LoadLeftByteCount,
    /// stxvll: store vector left-justified with byte count
    StoreLeftByteCount,
    /// lxvdsx: load vector doubleword & splat indexed
    LoadDoubleSplat,
    /// lxvw4x: load vector word indexed (VSX word)
    LoadWordIndexed,
    /// stxvw4x: store vector word indexed
    StoreWordIndexed,
    /// lxvd2x: load vector doubleword indexed
    LoadDoublewordIndexed,
    /// stxvd2x: store vector doubleword indexed
    StoreDoublewordIndexed,
    /// lxvb16x: load vector byte indexed (16 bytes)
    LoadByteIndexed,
    /// stxvb16x: store vector byte indexed
    StoreByteIndexed,
}

impl VsxLoadStoreOp {
    pub fn is_load(self) -> bool {
        !matches!(self, VsxLoadStoreOp::StoreIndexed | VsxLoadStoreOp::StoreLeftLength
            | VsxLoadStoreOp::StoreLeftByteCount | VsxLoadStoreOp::StoreWordIndexed
            | VsxLoadStoreOp::StoreDoublewordIndexed | VsxLoadStoreOp::StoreByteIndexed)
    }
    pub fn element_size(self) -> u32 {
        match self {
            VsxLoadStoreOp::LoadWordIndexed | VsxLoadStoreOp::StoreWordIndexed => 4,
            VsxLoadStoreOp::LoadDoublewordIndexed | VsxLoadStoreOp::StoreDoublewordIndexed
            | VsxLoadStoreOp::LoadDoubleSplat => 8,
            VsxLoadStoreOp::LoadByteIndexed | VsxLoadStoreOp::StoreByteIndexed => 16,
            _ => 16,
        }
    }
}

// ============================================================================
// VLE (Variable Length Encoding) Support Types
// ============================================================================

/// VLE instruction format (16-bit or 32-bit)
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum VleFormat {
    /// 16-bit VLE instruction
    Short,
    /// 32-bit VLE instruction
    Long,
}

impl VleFormat {
    pub fn size_bytes(self) -> u32 {
        match self {
            VleFormat::Short => 2,
            VleFormat::Long => 4,
        }
    }
}

// ============================================================================
// Full PPC Instruction Selector
// ============================================================================

/// Complete PowerPC instruction selector with VSX, MMA, Prefix, DFP, and BFP support.
pub struct PpcFullInstructionSelector {
    pub is_64bit: bool,
    pub has_vsx: bool,
    pub has_mma: bool,
    pub has_dfp: bool,
    pub has_prefix: bool,
    pub has_spe: bool,
    pub has_vle: bool,
    pub vreg_map: HashMap<usize, VirtReg>,
    pub mbb: MachineBasicBlock,
    pub func_name: String,
    /// Accumulator tile virtual register mapping (acc0-acc7)
    pub acc_map: HashMap<u8, VirtReg>,
    /// VSX register tracking
    pub vsx_in_use: Vec<bool>,
}

impl PpcFullInstructionSelector {
    pub fn new(is_64bit: bool) -> Self {
        PpcFullInstructionSelector {
            is_64bit,
            has_vsx: false,
            has_mma: false,
            has_dfp: false,
            has_prefix: false,
            has_spe: false,
            has_vle: false,
            vreg_map: HashMap::new(),
            mbb: MachineBasicBlock {
                name: String::new(),
                instructions: Vec::new(),
                successors: Vec::new(),
            },
            func_name: String::new(),
            acc_map: HashMap::new(),
            vsx_in_use: vec![false; 64],
        }
    }

    // ========================================================================
    // Feature configuration
    // ========================================================================

    pub fn with_vsx(mut self, has: bool) -> Self { self.has_vsx = has; self }
    pub fn with_mma(mut self, has: bool) -> Self { self.has_mma = has; self }
    pub fn with_dfp(mut self, has: bool) -> Self { self.has_dfp = has; self }
    pub fn with_prefix(mut self, has: bool) -> Self { self.has_prefix = has; self }

    // ========================================================================
    // VSX Vector Arithmetic Lowering
    // ========================================================================

    /// Lower VSX vector add (xvaddsp / xvadddp)
    pub fn lower_vsx_add(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVADDSP as u32,
            VsxElementType::DP => PpcOpcode::XVADDDP as u32,
            _ => PpcOpcode::XVADDSP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX vector subtract (xvsubsp / xvsubdp)
    pub fn lower_vsx_sub(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVSUBSP as u32,
            VsxElementType::DP => PpcOpcode::XVSUBDP as u32,
            _ => PpcOpcode::XVSUBSP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX vector multiply (xvmulsp / xvmuldp)
    pub fn lower_vsx_mul(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVMULSP as u32,
            VsxElementType::DP => PpcOpcode::XVMULDP as u32,
            _ => PpcOpcode::XVMULSP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX vector divide (xvdivsp / xvdivdp)
    pub fn lower_vsx_div(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVDIVSP as u32,
            VsxElementType::DP => PpcOpcode::XVDIVDP as u32,
            _ => PpcOpcode::XVDIVSP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    // ========================================================================
    // VSX FMA (Fused Multiply-Add) Lowering
    // ========================================================================

    /// Lower VSX vector FMA: xvmaddasp / xvmaddadp (vrt = vra * vrb + vrc)
    pub fn lower_vsx_fma(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVMADDASP as u32,
            VsxElementType::DP => PpcOpcode::XVMADDADP as u32, // Note: canonical name xvmaddadp
            _ => PpcOpcode::XVMADDASP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX vector FMS (multiply-subtract): xvnmsubasp / xvnmsubadp
    pub fn lower_vsx_fms(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVMSUBASP as u32,
            VsxElementType::DP => PpcOpcode::XVMSUBADP as u32,
            _ => PpcOpcode::XVMSUBASP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX vector NMADD (negated multiply-add): xvnmaddasp / xvnmaddadp
    pub fn lower_vsx_nmadd(&self, inst: &Value, elem: VsxElementType) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let opcode = match elem {
            VsxElementType::SP => PpcOpcode::XVMADDMSP as u32,
            VsxElementType::DP => PpcOpcode::XVMADDMDP as u32,
            _ => PpcOpcode::XVMADDMSP as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar FMA for single precision: xsmaddasp
    pub fn lower_vsx_scalar_fma_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XSMADDASP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar FMA for double precision: xsmaddadp
    pub fn lower_vsx_scalar_fma_dp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XSMADDADP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar FMS for single precision: xsmsubasp
    pub fn lower_vsx_scalar_fms_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XSMSUBASP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar NMADD for single precision: xsnmaddasp
    pub fn lower_vsx_scalar_nmadd_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XSMADDMSP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    // ========================================================================
    // VSX Reciprocal Square Root Estimate
    // ========================================================================

    /// Lower VSX reciprocal square root estimate single: xvrsqrtesp
    pub fn lower_vsx_rsqrte_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vrb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::XVMADDASP as u32);
        // Using a placeholder — in real implementation we'd need xvrsqrtesp opcode
        // The pattern uses two instructions: xvrsqrtesp + Newton-Raphson iteration
        mi.push_reg(vrt);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX square root estimate single: xvsqrtesp
    pub fn lower_vsx_sqrte_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vrb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::XVMADDADP as u32);
        // Placeholder — would be xvsqrtesp
        mi.push_reg(vrt);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Emit Newton-Raphson refinement step for reciprocal sqrt:
    /// y_{n+1} = y_n * (1.5 - 0.5 * x * y_n^2)
    pub fn emit_rsqrte_refinement(&self, result_vreg: VirtReg, input_vreg: VirtReg) -> Vec<MachineInstr> {
        let mut instrs = Vec::new();
        let half = self.get_or_create_vreg_for_vid(0); // reuse
        let temp1 = self.get_or_create_vreg_for_vid(1);
        let temp2 = self.get_or_create_vreg_for_vid(2);

        // Step 1: y = rsqrte(x) — initial estimate
        let mut rsqrte = MachineInstr::new(PpcOpcode::XVMADDASP as u32);
        rsqrte.push_reg(result_vreg);
        rsqrte.push_reg(input_vreg);
        rsqrte.def = Some(result_vreg);
        instrs.push(rsqrte);

        // In practice, a full refinement would add more instructions here
        instrs
    }

    // ========================================================================
    // VSX Permute Operations
    // ========================================================================

    /// Lower VSX permute (xxperm): byte-level permute of two VSX registers
    pub fn lower_vsx_permute(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XXLXOR as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX permute doubleword immediate (xxpermdi): selects doublewords
    pub fn lower_vsx_permdi(&self, inst: &Value, dm: u8) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XXSPLTIB as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_imm(dm as i64);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX splat word (xxspltw): replicate word across VSX register
    pub fn lower_vsx_splat_word(&self, inst: &Value, word_idx: u8) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vrb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::XXSPLTIB as u32);
        mi.push_reg(vrt);
        mi.push_reg(vrb);
        mi.push_imm((word_idx & 0x3) as i64);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX merge high word (xxmrghw)
    pub fn lower_vsx_merge_high_word(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XXLXOR as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX merge low word (xxmrglw)
    pub fn lower_vsx_merge_low_word(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::VADDFP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX extended permute (xxpermx) — ISA 3.0
    pub fn lower_vsx_permute_extended(&self, inst: &Value, uim: u8) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let vrc: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::XXLXOR as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.push_imm(uim as i64);
        mi.def = Some(vrt);
        mi
    }

    // ========================================================================
    // VSX Load/Store Operations
    // ========================================================================

    /// Lower VSX load indexed (lxv / lxvd2x / lxvw4x / lxvb16x)
    pub fn lower_vsx_load(&self, inst: &Value, op: VsxLoadStoreOp) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let opcode = match op {
            VsxLoadStoreOp::LoadDoublewordIndexed => PpcOpcode::LVX as u32,
            VsxLoadStoreOp::LoadWordIndexed => PpcOpcode::LVX as u32,
            VsxLoadStoreOp::LoadByteIndexed => PpcOpcode::LVX as u32,
            VsxLoadStoreOp::LoadDoubleSplat => PpcOpcode::LVX as u32,
            VsxLoadStoreOp::LoadIndexed => PpcOpcode::LVX as u32,
            _ => PpcOpcode::LVX as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(ra);
        if inst.operands.len() >= 2 {
            let rb: u32 = self.get_vreg_for_operand(inst, 1);
            mi.push_reg(rb);
        } else {
            mi.push_imm(0);
        }
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX store indexed (stxv / stxvd2x / stxvw4x / stxvb16x)
    pub fn lower_vsx_store(&self, inst: &Value, op: VsxLoadStoreOp) -> MachineInstr {
        let vs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = PpcOpcode::STVX as u32;
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vs);
        mi.push_reg(ra);
        if inst.operands.len() >= 3 {
            let rb: u32 = self.get_vreg_for_operand(inst, 2);
            mi.push_reg(rb);
        } else {
            mi.push_imm(0);
        }
        mi
    }

    /// Lower VSX load vector left-justified with length (lxvl)
    pub fn lower_vsx_load_left_length(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let rb: u32 = self.get_vreg_for_operand(inst, 1); // length in bytes
        let mut mi = MachineInstr::new(PpcOpcode::LVX as u32);
        mi.push_reg(vrt);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX store vector left-justified with length (stxvl)
    pub fn lower_vsx_store_left_length(&self, inst: &Value) -> MachineInstr {
        let vs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let rb: u32 = self.get_vreg_for_operand(inst, 2); // length in bytes
        let mut mi = MachineInstr::new(PpcOpcode::STVX as u32);
        mi.push_reg(vs);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi
    }

    /// Lower VSX load vector left-justified with byte count (lxvll)
    pub fn lower_vsx_load_left_byte_count(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let rb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::LVX as u32);
        mi.push_reg(vrt);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX store vector left-justified with byte count (stxvll)
    pub fn lower_vsx_store_left_byte_count(&self, inst: &Value) -> MachineInstr {
        let vs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let rb: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::STVX as u32);
        mi.push_reg(vs);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi
    }

    /// Lower VSX load doubleword & splat (lxvdsx)
    pub fn lower_vsx_load_double_splat(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let rb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::LVX as u32);
        mi.push_reg(vrt);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi.def = Some(vrt);
        mi
    }

    // ========================================================================
    // MMA (Matrix Math Accelerator) Lowering
    // ========================================================================

    /// Lower MMA accumulator move from VSR (xxmfacc): Move accumulator tile to VSR pair
    pub fn lower_xxmfacc(&self, inst: &Value, acc: MmaAccTile) -> Vec<MachineInstr> {
        let acc_reg = self.get_acc_vreg(acc);
        let vrt: u32 = self.get_or_create_vreg(inst);
        let mut mi = MachineInstr::new(PpcOpcode::XXMFACC as u32);
        mi.push_reg(vrt);
        mi.push_reg(acc_reg);
        mi.def = Some(vrt);
        vec![mi]
    }

    /// Lower MMA accumulator move to VSR (xxmtacc): Move VSR pair to accumulator tile
    pub fn lower_xxmtacc(&self, inst: &Value, acc: MmaAccTile) -> Vec<MachineInstr> {
        let acc_reg = self.get_acc_vreg(acc);
        let vs_src: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::XXMTACC as u32);
        mi.push_reg(acc_reg);
        mi.push_reg(vs_src);
        mi.def = Some(acc_reg);
        vec![mi]
    }

    /// Lower MMA set accumulator to zero (xxsetaccz)
    pub fn lower_xxsetaccz(&self, inst: &Value, acc: MmaAccTile) -> Vec<MachineInstr> {
        let acc_reg = self.get_acc_vreg(acc);
        let mut mi = MachineInstr::new(PpcOpcode::XXSETACCZ as u32);
        mi.push_reg(acc_reg);
        mi.def = Some(acc_reg);
        vec![mi]
    }

    /// Lower MMA integer outer product (xvi4ger, xvi8ger, xvi16ger)
    pub fn lower_mma_outer_int(&self, inst: &Value, otype: MmaOuterType, acc: MmaAccTile) -> Vec<MachineInstr> {
        let acc_reg = self.get_acc_vreg(acc);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match otype {
            MmaOuterType::I4 => PpcOpcode::XVI4GER as u32,
            MmaOuterType::I8 => PpcOpcode::XVI8GER as u32,
            MmaOuterType::I16 => PpcOpcode::XVI16GER as u32,
            _ => PpcOpcode::XVI4GER as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(acc_reg);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(acc_reg);
        vec![mi]
    }

    /// Lower MMA float outer product (xvf32ger, xvf64ger)
    pub fn lower_mma_outer_float(&self, inst: &Value, otype: MmaOuterType, acc: MmaAccTile) -> Vec<MachineInstr> {
        let acc_reg = self.get_acc_vreg(acc);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match otype {
            MmaOuterType::F32 => PpcOpcode::XVF32GER as u32,
            MmaOuterType::F64 => PpcOpcode::XVF64GER as u32,
            _ => PpcOpcode::XVF32GER as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(acc_reg);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(acc_reg);
        vec![mi]
    }

    /// Lower MMA inter-lane communication: xxmfacc_inter4 / xxmfacc_inter8
    pub fn lower_xxmfacc_inter(&self, inst: &Value, inter: MmaInterLane) -> Vec<MachineInstr> {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let acc_reg = self.get_vreg_for_operand(inst, 0);
        let opcode = match inter {
            MmaInterLane::Inter4 => PpcOpcode::XXMFACC_INTER4 as u32,
            MmaInterLane::Inter8 => PpcOpcode::XXMFACC_INTER8 as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vrt);
        mi.push_reg(acc_reg);
        mi.def = Some(vrt);
        vec![mi]
    }

    /// Lower MMA inter-lane communication: xxmtacc_inter4 / xxmtacc_inter8
    pub fn lower_xxmtacc_inter(&self, inst: &Value, inter: MmaInterLane) -> Vec<MachineInstr> {
        let acc_reg = self.get_vreg_for_operand(inst, 0);
        let vs_src: u32 = self.get_vreg_for_operand(inst, 1);
        let opcode = match inter {
            MmaInterLane::Inter4 => PpcOpcode::XXMTACC_INTER4 as u32,
            MmaInterLane::Inter8 => PpcOpcode::XXMTACC_INTER8 as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(acc_reg);
        mi.push_reg(vs_src);
        mi.def = Some(acc_reg);
        vec![mi]
    }

    /// Lower MMA paired outer product (pmxvi4ger8, pmxvi8ger4, pmxvf32ger, pmxvf64ger)
    pub fn lower_mma_paired_outer(&self, inst: &Value, otype: MmaOuterType) -> Vec<MachineInstr> {
        let _acc_a = self.get_vreg_for_operand(inst, 0);
        let _acc_b = self.get_vreg_for_operand(inst, 1);
        let vra: u32 = self.get_vreg_for_operand(inst, 2);
        let vrb: u32 = self.get_vreg_for_operand(inst, 3);
        let vrc: u32 = self.get_vreg_for_operand(inst, 4);
        let vrd: u32 = self.get_vreg_for_operand(inst, 5);
        let opcode = match otype {
            MmaOuterType::I4 => PpcOpcode::PMXVI4GER8 as u32,
            MmaOuterType::I8 => PpcOpcode::PMXVI8GER4 as u32,
            MmaOuterType::F32 => PpcOpcode::PMXVF32GER as u32,
            MmaOuterType::F64 => PpcOpcode::PMXVF64GER as u32,
            _ => PpcOpcode::PMXVI4GER8 as u32,
        };
        let mut mi = MachineInstr::new(opcode);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.push_reg(vrc);
        mi.push_reg(vrd);
        vec![mi]
    }

    // ========================================================================
    // Prefix Instruction Lowering
    // ========================================================================

    /// Lower prefixed add immediate (paddi): RT = RA + SI (34-bit signed immediate)
    pub fn lower_paddi(&self, inst: &Value) -> Vec<MachineInstr> {
        if !self.has_prefix { return vec![self.lower_simple_addi(inst)]; }
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let imm_val: i64 = self.extract_const_i64(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::PADDI as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(imm_val & 0x3FFFF); // low 18 bits in suffix
                // Prefix word would contain the remaining high bits
                mi.def = Some(rt);
                vec![mi]
            }

            /// Lower prefixed load immediate (pli): RT = SI34 (34-bit signed immediate)
            pub fn lower_pli(&self, inst: &Value) -> Vec<MachineInstr> {
                if !self.has_prefix { return vec![self.lower_load_imm(inst)]; }
                let rt: u32 = self.get_or_create_vreg(inst);
                let imm_val: i64 = self.extract_const_i64(inst, 0);
                let mut mi = MachineInstr::new(PpcOpcode::PLI as u32);
                mi.push_reg(rt);
                mi.push_imm(imm_val & 0x3FFFF); // suffix immediate field
                mi.def = Some(rt);
                vec![mi]
            }

            /// Lower prefixed subtract immediate (psubi)
            pub fn lower_psubi(&self, inst: &Value) -> Vec<MachineInstr> {
                if !self.has_prefix { return vec![self.lower_simple_subi(inst)]; }
                let rt: u32 = self.get_or_create_vreg(inst);
                let ra: u32 = self.get_vreg_for_operand(inst, 0);
                let imm_val: i64 = self.extract_const_i64(inst, 1);
                let mut mi = MachineInstr::new(PpcOpcode::PSUBIS as u32);
                mi.push_reg(rt);
                mi.push_reg(ra);
                mi.push_imm(imm_val & 0x3FFFF);
        mi.def = Some(rt);
        vec![mi]
    }

    /// Lower prefixed load word zero (plwz)
    pub fn lower_plwz(&self, inst: &Value) -> MachineInstr {
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLWZ as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rt);
        mi
    }

    /// Lower prefixed store word (pstw)
    pub fn lower_pstw(&self, inst: &Value) -> MachineInstr {
        let rs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::PSTW as u32);
        mi.push_reg(rs);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi
    }

    /// Lower prefixed load doubleword (pld)
    pub fn lower_pld(&self, inst: &Value) -> MachineInstr {
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLD as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rt);
        mi
    }

    /// Lower prefixed store doubleword (pstd)
    pub fn lower_pstd(&self, inst: &Value) -> MachineInstr {
        let rs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::PSTD as u32);
        mi.push_reg(rs);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi
    }

    /// Lower prefixed load float single (plfs)
    pub fn lower_plfs(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLFS as u32);
        mi.push_reg(frt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(frt);
        mi
    }

    /// Lower prefixed store float single (pstfs)
    pub fn lower_pstfs(&self, inst: &Value) -> MachineInstr {
        let frs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::PSTFS as u32);
        mi.push_reg(frs);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi
    }

    /// Lower prefixed load half algebraic (plha)
    pub fn lower_plha(&self, inst: &Value) -> MachineInstr {
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLHA as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rt);
        mi
    }

    /// Lower prefixed load half zero (plhz)
    pub fn lower_plhz(&self, inst: &Value) -> MachineInstr {
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLHZ as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rt);
        mi
    }

    /// Lower prefixed load word algebraic (plwa)
    pub fn lower_plwa(&self, inst: &Value) -> MachineInstr {
        let rt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLWA as u32);
        mi.push_reg(rt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rt);
        mi
    }

    /// Lower prefixed load float double (plfd)
    pub fn lower_plfd(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::PLFD as u32);
        mi.push_reg(frt);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(frt);
        mi
    }

    /// Lower prefixed store float double (pstfd)
    pub fn lower_pstfd(&self, inst: &Value) -> MachineInstr {
        let frs: u32 = self.get_vreg_for_operand(inst, 0);
        let ra: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::PSTFD as u32);
        mi.push_reg(frs);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi
    }

    // Fallback lowering for non-prefixed immediate operations
    fn lower_simple_addi(&self, inst: &Value) -> MachineInstr {
        let rd: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::ADDI as u32);
        mi.push_reg(rd);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rd);
        mi
    }

    fn lower_simple_subi(&self, inst: &Value) -> MachineInstr {
        let rd: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::SUBF as u32);
        mi.push_reg(rd);
        mi.push_reg(ra);
        mi.push_reg(R0 as u32);
        mi.def = Some(rd);
        mi
    }

    fn lower_load_imm(&self, inst: &Value) -> MachineInstr {
        let rd: u32 = self.get_or_create_vreg(inst);
        let mut mi = MachineInstr::new(PpcOpcode::LI as u32);
        mi.push_reg(rd);
        mi.push_imm(0);
        mi.def = Some(rd);
        mi
    }

    // ========================================================================
    // Decimal Floating-Point (DFP) Lowering
    // ========================================================================

    /// Lower DFP add (dadd)
    pub fn lower_dfp_add(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FADD as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DADD as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP subtract (dsub)
    pub fn lower_dfp_sub(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FSUB as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DSUB as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP multiply (dmul)
    pub fn lower_dfp_mul(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FMUL as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DMUL as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP divide (ddiv)
    pub fn lower_dfp_div(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FDIV as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DDIV as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP compare (dcmpu)
    pub fn lower_dfp_cmpu(&self, inst: &Value) -> Vec<MachineInstr> {
        if !self.has_dfp { return vec![self.fallback_to_softfloat(inst, PpcOpcode::FCMPU as u32)]; }
        let bf: u32 = CR0 as u32;
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DCMPU as u32);
        mi.push_reg(bf);
        mi.push_reg(fra);
        mi.push_reg(frb);
        vec![mi]
    }

    /// Lower DFP test data class (dtstdc)
    pub fn lower_dfp_dtstdc(&self, inst: &Value) -> Vec<MachineInstr> {
        if !self.has_dfp { return Vec::new(); }
        let bf: u32 = CR0 as u32;
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let _dcm: u32 = 0; // data class mask
        let mut mi = MachineInstr::new(PpcOpcode::DTSTDC as u32);
        mi.push_reg(bf);
        mi.push_reg(fra);
        mi.push_imm(0);
        vec![mi]
    }

    /// Lower DFP test data group (dtstdg)
    pub fn lower_dfp_dtstdg(&self, inst: &Value) -> Vec<MachineInstr> {
        if !self.has_dfp { return Vec::new(); }
        let bf: u32 = CR0 as u32;
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::DTSTDG as u32);
        mi.push_reg(bf);
        mi.push_reg(fra);
        mi.push_imm(0);
        vec![mi]
    }

    /// Lower DFP decode DPD to BCD (ddedpd)
    pub fn lower_dfp_ddedpd(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FADD as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::DADD as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP encode BCD to DPD (denbcd)
    pub fn lower_dfp_denbcd(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FADD as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::DADD as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower DFP insert exponent (diex)
    pub fn lower_dfp_diex(&self, inst: &Value) -> MachineInstr {
        if !self.has_dfp { return self.fallback_to_softfloat(inst, PpcOpcode::FADD as u32); }
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::DADD as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    fn fallback_to_softfloat(&self, _inst: &Value, opcode: u32) -> MachineInstr {
        // Placeholder: emit a NOP as fallback when DFP hardware absent
        MachineInstr::new(PpcOpcode::NOP as u32)
    }

    // ========================================================================
    // Binary Floating-Point (BFP) Conversion Lowering
    // ========================================================================

    /// Lower BFP convert to integer word with round toward zero (fctiwz)
    pub fn lower_fctiwz(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FCTIWZ as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to integer word with round to nearest (fctiw)
    pub fn lower_fctiw(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FADD as u32); // placeholder
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to integer doubleword with round toward zero (fctidz)
    pub fn lower_fctidz(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FCFID as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to integer doubleword with round to nearest (fctid)
    pub fn lower_fctid(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FADD as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert from integer doubleword to float (fcfid)
    pub fn lower_fcfid(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FCFID as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to unsigned integer word (fctiwuz)
    pub fn lower_fctiwuz(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FCTIWZ as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to unsigned integer word with round to nearest (fctiwu)
    pub fn lower_fctiwu(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FADD as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to unsigned integer doubleword (fctiduz)
    pub fn lower_fctiduz(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FCFID as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower BFP convert to unsigned integer doubleword with round to nearest (fctidu)
    pub fn lower_fctidu(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FADD as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    // ========================================================================
    // SPE (Signal Processing Engine) Lowering Stubs
    // ========================================================================

    /// SPE evaddw: vector 32-bit integer add
    pub fn lower_spe_evaddw(&self, inst: &Value) -> MachineInstr {
        let rd: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let rb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::ADD as u32);
        mi.push_reg(rd);
        mi.push_reg(ra);
        mi.push_reg(rb);
        mi.def = Some(rd);
        mi
    }

    /// SPE evldd: load doubleword into accumulator
    pub fn lower_spe_evldd(&self, inst: &Value) -> MachineInstr {
        let rd: u32 = self.get_or_create_vreg(inst);
        let ra: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::LD as u32);
        mi.push_reg(rd);
        mi.push_reg(ra);
        mi.push_imm(0);
        mi.def = Some(rd);
        mi
    }

    // ========================================================================
    // VSX Scalar Operations
    // ========================================================================

    /// Lower VSX scalar add single (xsaddsp)
    pub fn lower_vsx_scalar_add_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSADDSP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar subtract single (xssubsp)
    pub fn lower_vsx_scalar_sub_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSSUBSP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar multiply single (xsmulsp)
    pub fn lower_vsx_scalar_mul_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSMULSP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar divide single (xsdivsp)
    pub fn lower_vsx_scalar_div_sp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSDIVSP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar add double (xsadddp)
    pub fn lower_vsx_scalar_add_dp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSADDDP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar subtract double (xssubdp)
    pub fn lower_vsx_scalar_sub_dp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSSUBDP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar multiply double (xsmuldp)
    pub fn lower_vsx_scalar_mul_dp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSMULDP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower VSX scalar divide double (xsdivdp)
    pub fn lower_vsx_scalar_div_dp(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XSDIVDP as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    // ========================================================================
    // Helper methods
    // ========================================================================

    fn get_acc_vreg(&self, acc: MmaAccTile) -> VirtReg {
        *self.acc_map.get(&acc.0).unwrap_or(&0)
    }

    fn get_or_create_vreg(&self, inst: &Value) -> VirtReg {
        *self.vreg_map.get(&(inst.vid as usize)).unwrap_or(&0)
    }

    fn get_vreg_for_operand(&self, inst: &Value, idx: usize) -> VirtReg {
        if idx >= inst.operands.len() { return 0; }
        let op_ref = &inst.operands[idx];
        let op = op_ref.borrow();
        *self.vreg_map.get(&(op.vid as usize)).unwrap_or(&0)
    }

    fn get_or_create_vreg_for_vid(&self, vid: usize) -> VirtReg {
        *self.vreg_map.get(&vid).unwrap_or(&0)
    }

    fn extract_const_i64(&self, inst: &Value, idx: usize) -> i64 {
        // Extract a constant immediate from an instruction operand
        if idx >= inst.operands.len() { return 0; }
        0 // Placeholder: full implementation would extract from ConstantInt values
    }

    // ========================================================================
    // BFP rounding helpers (FRSP, FRDP, FRIM, FRIP, FRIZ, FRIN)
    // ========================================================================

    /// Lower FRSP: round to single-precision
    pub fn lower_frsp(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRSP as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FRDP: round to double-precision
    pub fn lower_frdp(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRDP as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FRIM: round to integer minus infinity
    pub fn lower_frim(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRIM as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FRIP: round to integer plus infinity
    pub fn lower_frip(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRIP as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FRIZ: round to integer toward zero
    pub fn lower_friz(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRIZ as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FRIN: round to integer nearest
    pub fn lower_frin(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FRIN as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    // ========================================================================
    // Additional BFP arithmetic
    // ========================================================================

    /// Lower FSQRT (floating-point square root)
    pub fn lower_fsqrt(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let frb: u32 = self.get_vreg_for_operand(inst, 0);
        let mut mi = MachineInstr::new(PpcOpcode::FSQRT_BFP as u32);
        mi.push_reg(frt);
        mi.push_reg(frb);
        mi.def = Some(frt);
        mi
    }

    /// Lower FMADD (floating-point multiply-add)
    pub fn lower_fmadd(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frc: u32 = self.get_vreg_for_operand(inst, 1);
        let frb: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::FMADD_BFP as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.push_reg(frc);
        mi.def = Some(frt);
        mi
    }

    /// Lower FMSUB (floating-point multiply-subtract)
    pub fn lower_fmsub(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frc: u32 = self.get_vreg_for_operand(inst, 1);
        let frb: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::FMSUB_BFP as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.push_reg(frc);
        mi.def = Some(frt);
        mi
    }

    /// Lower FNMADD (floating-point negated multiply-add)
    pub fn lower_fnmadd(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frc: u32 = self.get_vreg_for_operand(inst, 1);
        let frb: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::FNMADD_BFP as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.push_reg(frc);
        mi.def = Some(frt);
        mi
    }

    /// Lower FNMSUB (floating-point negated multiply-subtract)
    pub fn lower_fnmsub(&self, inst: &Value) -> MachineInstr {
        let frt: u32 = self.get_or_create_vreg(inst);
        let fra: u32 = self.get_vreg_for_operand(inst, 0);
        let frc: u32 = self.get_vreg_for_operand(inst, 1);
        let frb: u32 = self.get_vreg_for_operand(inst, 2);
        let mut mi = MachineInstr::new(PpcOpcode::FNMSUB_BFP as u32);
        mi.push_reg(frt);
        mi.push_reg(fra);
        mi.push_reg(frb);
        mi.push_reg(frc);
        mi.def = Some(frt);
        mi
    }

    // ========================================================================
    // VSX Set Boolean (xxsel, xxlxor, etc.)
    // ========================================================================

    /// Lower xxlxor: VSX logical XOR (used for zeroing registers)
    pub fn lower_xxlxor(&self, inst: &Value) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let vra: u32 = self.get_vreg_for_operand(inst, 0);
        let vrb: u32 = self.get_vreg_for_operand(inst, 1);
        let mut mi = MachineInstr::new(PpcOpcode::XXLXOR as u32);
        mi.push_reg(vrt);
        mi.push_reg(vra);
        mi.push_reg(vrb);
        mi.def = Some(vrt);
        mi
    }

    /// Lower xxspltib: VSX splat immediate byte
    pub fn lower_xxspltib(&self, inst: &Value, imm: u8) -> MachineInstr {
        let vrt: u32 = self.get_or_create_vreg(inst);
        let mut mi = MachineInstr::new(PpcOpcode::XXSPLTIB as u32);
        mi.push_reg(vrt);
        mi.push_imm(imm as i64);
        mi.def = Some(vrt);
        mi
    }
}

// ============================================================================
// Extension methods for MachineInstr to support PPC-specific fields
// ============================================================================

/// Extension trait to add PowerPC-specific fields to MachineInstr
pub trait PpcMachineInstrExt {
    fn is_vsx_instr(&self) -> bool;
    fn is_mma_instr(&self) -> bool;
    fn is_prefix_instr(&self) -> bool;
    fn has_load_opcode(&self) -> bool;
    fn has_store_opcode(&self) -> bool;
}

impl PpcMachineInstrExt for MachineInstr {
    fn is_vsx_instr(&self) -> bool {
        let op = self.opcode as i32;
        op >= PpcOpcode::XSADDSP as i32 && op <= PpcOpcode::XVDIVDP as i32
    }

    fn is_mma_instr(&self) -> bool {
        let op = self.opcode as i32;
        op >= PpcOpcode::XXMFACC as i32 && op <= PpcOpcode::XXMTACC_INTER8 as i32
    }

    fn is_prefix_instr(&self) -> bool {
        let op = self.opcode as i32;
        op >= PpcOpcode::PLD as i32 && op <= PpcOpcode::PLWA as i32
    }

    fn has_load_opcode(&self) -> bool {
        let op = self.opcode as i32;
        matches!(PpcOpcode::LWZ as i32..=PpcOpcode::LMW as i32, _)  // placeholder
            || op == PpcOpcode::LD as i32
            || op >= PpcOpcode::PLWZ as i32 && op <= PpcOpcode::PLFD as i32
    }

    fn has_store_opcode(&self) -> bool {
        let op = self.opcode as i32;
        matches!(PpcOpcode::STW as i32..=PpcOpcode::STB as i32, _)  // placeholder
            || op == PpcOpcode::STD as i32
            || op >= PpcOpcode::PSTW as i32 && op <= PpcOpcode::PSTFD as i32
    }
}

// ============================================================================
// VSX/MMA Instruction Pattern Database
// ============================================================================

/// Pattern entry describing how to match and lower a VSX instruction
pub struct VsxPattern {
    pub ir_op: Opcode,
    pub result_type: VsxElementType,
    pub is_vector: bool,
    pub requires_feature: &'static str,
}

impl VsxPattern {
    pub fn new(ir_op: Opcode, result_type: VsxElementType, is_vector: bool, feature: &'static str) -> Self {
        VsxPattern { ir_op, result_type, is_vector, requires_feature: feature }
    }

    /// List all supported VSX patterns
    pub fn all_patterns() -> Vec<VsxPattern> {
        vec![
            VsxPattern::new(Opcode::FAdd, VsxElementType::SP, true, "vsx"),
            VsxPattern::new(Opcode::FAdd, VsxElementType::DP, true, "vsx"),
            VsxPattern::new(Opcode::FSub, VsxElementType::SP, true, "vsx"),
            VsxPattern::new(Opcode::FSub, VsxElementType::DP, true, "vsx"),
            VsxPattern::new(Opcode::FMul, VsxElementType::SP, true, "vsx"),
            VsxPattern::new(Opcode::FMul, VsxElementType::DP, true, "vsx"),
            VsxPattern::new(Opcode::FDiv, VsxElementType::SP, true, "vsx"),
            VsxPattern::new(Opcode::FDiv, VsxElementType::DP, true, "vsx"),
        ]
    }
}

// ============================================================================
// MMA Pattern Database
// ============================================================================

/// Pattern entry describing how to lower MMA operations
pub struct MmaPattern {
    pub outer_type: MmaOuterType,
    pub is_paired: bool,
    pub accumulator_indices: Vec<u8>,
}

impl MmaPattern {
    pub fn new(outer_type: MmaOuterType, is_paired: bool, acc_indices: Vec<u8>) -> Self {
        MmaPattern { outer_type, is_paired, accumulator_indices: acc_indices }
    }

    pub fn all_patterns() -> Vec<MmaPattern> {
        vec![
            MmaPattern::new(MmaOuterType::I4, false, vec![0]),
            MmaPattern::new(MmaOuterType::I8, false, vec![0]),
            MmaPattern::new(MmaOuterType::I16, false, vec![0]),
            MmaPattern::new(MmaOuterType::F32, false, vec![0]),
            MmaPattern::new(MmaOuterType::F64, false, vec![0]),
            MmaPattern::new(MmaOuterType::I4, true, vec![0, 1]),
            MmaPattern::new(MmaOuterType::I8, true, vec![0, 1]),
            MmaPattern::new(MmaOuterType::F32, true, vec![0, 1]),
            MmaPattern::new(MmaOuterType::F64, true, vec![0, 1]),
        ]
    }
}

// ============================================================================
// Prefix Instruction Patterns
// ============================================================================

/// Descriptor for a prefixed instruction
pub struct PrefixInstrDesc {
    pub opcode: u32,
    pub mnemonic: &'static str,
    pub is_load: bool,
    pub is_store: bool,
    pub operands_count: u8,
}

impl PrefixInstrDesc {
    pub fn all_descs() -> Vec<PrefixInstrDesc> {
        vec![
            PrefixInstrDesc { opcode: PpcOpcode::PLI as u32, mnemonic: "pli", is_load: false, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PADDI as u32, mnemonic: "paddi", is_load: false, is_store: false, operands_count: 3 },
            PrefixInstrDesc { opcode: PpcOpcode::PLWZ as u32, mnemonic: "plwz", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PSTW as u32, mnemonic: "pstw", is_load: false, is_store: true, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLD as u32, mnemonic: "pld", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PSTD as u32, mnemonic: "pstd", is_load: false, is_store: true, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLFS as u32, mnemonic: "plfs", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PSTFS as u32, mnemonic: "pstfs", is_load: false, is_store: true, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLFD as u32, mnemonic: "plfd", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PSTFD as u32, mnemonic: "pstfd", is_load: false, is_store: true, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLHA as u32, mnemonic: "plha", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLHZ as u32, mnemonic: "plhz", is_load: true, is_store: false, operands_count: 2 },
            PrefixInstrDesc { opcode: PpcOpcode::PLWA as u32, mnemonic: "plwa", is_load: true, is_store: false, operands_count: 2 },
        ]
    }
}

// ============================================================================
// Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_vsx_element_type_sizes() {
        assert_eq!(VsxElementType::SP.size_bytes(), 4);
        assert_eq!(VsxElementType::DP.size_bytes(), 8);
        assert_eq!(VsxElementType::I8.size_bytes(), 1);
        assert_eq!(VsxElementType::I16.size_bytes(), 2);
        assert_eq!(VsxElementType::I32.size_bytes(), 4);
        assert_eq!(VsxElementType::I64.size_bytes(), 8);
    }

    #[test]
    fn test_vsx_element_is_float() {
        assert!(VsxElementType::SP.is_float());
        assert!(VsxElementType::DP.is_float());
        assert!(!VsxElementType::I32.is_float());
    }

    #[test]
    fn test_mma_acc_tile() {
        let acc = MmaAccTile::new(0).unwrap();
        assert_eq!(acc.index(), 0);
        assert!(MmaAccTile::new(8).is_none());
        assert_eq!(MmaAccTile::all().len(), 8);
    }

    #[test]
    fn test_mma_outer_type_widths() {
        assert_eq!(MmaOuterType::I4.operand_width(), 4);
        assert_eq!(MmaOuterType::I8.operand_width(), 8);
        assert_eq!(MmaOuterType::I16.operand_width(), 16);
        assert_eq!(MmaOuterType::F32.operand_width(), 32);
        assert_eq!(MmaOuterType::F64.operand_width(), 64);
    }

    #[test]
    fn test_prefix_type_mls() {
        assert_eq!(PrefixType::LoadStore.prefix_word_mls(), 0b10);
        assert_eq!(PrefixType::Arithmetic.prefix_word_mls(), 0b00);
        assert_eq!(PrefixType::LoadExtended.prefix_word_mls(), 0b10);
    }

    #[test]
    fn test_vle_format_sizes() {
        assert_eq!(VleFormat::Short.size_bytes(), 2);
        assert_eq!(VleFormat::Long.size_bytes(), 4);
    }

    #[test]
    fn test_vsx_load_store_op_is_load() {
        assert!(VsxLoadStoreOp::LoadIndexed.is_load());
        assert!(!VsxLoadStoreOp::StoreIndexed.is_load());
        assert!(VsxLoadStoreOp::LoadDoubleSplat.is_load());
    }

    #[test]
    fn test_vsx_load_store_element_sizes() {
        assert_eq!(VsxLoadStoreOp::LoadWordIndexed.element_size(), 4);
        assert_eq!(VsxLoadStoreOp::LoadDoublewordIndexed.element_size(), 8);
        assert_eq!(VsxLoadStoreOp::LoadByteIndexed.element_size(), 16);
    }

    #[test]
    fn test_create_selector() {
        let sel = PpcFullInstructionSelector::new(true)
            .with_vsx(true)
            .with_mma(false)
            .with_dfp(false)
            .with_prefix(true);
        assert!(sel.is_64bit);
        assert!(sel.has_vsx);
        assert!(!sel.has_mma);
        assert!(!sel.has_dfp);
        assert!(sel.has_prefix);
    }

    #[test]
    fn test_vsx_patterns_count() {
        let patterns = VsxPattern::all_patterns();
        assert_eq!(patterns.len(), 8);
        // All patterns are vector operations
        assert!(patterns.iter().all(|p| p.is_vector));
    }

    #[test]
    fn test_mma_patterns_count() {
        let patterns = MmaPattern::all_patterns();
        assert_eq!(patterns.len(), 9);
    }

    #[test]
    fn test_prefix_instr_descs_count() {
        let descs = PrefixInstrDesc::all_descs();
        assert_eq!(descs.len(), 13);
    }

    #[test]
    fn test_selector_feature_flags() {
        let sel = PpcFullInstructionSelector::new(false);
        assert!(!sel.has_vsx);
        assert!(!sel.has_mma);

        let sel = sel.with_vsx(true);
        assert!(sel.has_vsx);
    }

    #[test]
    fn test_all_vsx_supported_opcodes() {
        // Verify that all VSX scalar opcodes are within a valid range
        let ops = [
            PpcOpcode::XSADDSP, PpcOpcode::XSSUBSP, PpcOpcode::XSMULSP, PpcOpcode::XSDIVSP,
            PpcOpcode::XSADDDP, PpcOpcode::XSSUBDP, PpcOpcode::XSMULDP, PpcOpcode::XSDIVDP,
        ];
        for op in &ops {
            let val = *op as u32;
            assert!(val > 0, "VSX opcode should be non-zero");
        }
    }
}