llvm-native-core 0.1.10

//! RISC-V Target Backend — complete register information,
//! instruction set metadata, calling convention implementation,
//! instruction selection, register allocation, frame lowering,
//! MC encoding/decoding, and assembly printer for the RISC-V
//! architecture family.
//!
//! Clean-room behavioral reconstruction from the RISC-V ISA Manual,
//! Volume I: Unprivileged Architecture, Volume II: Privileged
//! Architecture, and the RISC-V ELF psABI specification.
//! Zero LLVM source code consultation.
//!
//! Architecture coverage:
//! - RV64I: 64-bit base integer instruction set
//! - RV32I: 32-bit base integer instruction set
//! - Extensions: M (multiply/divide), A (atomics), F (single-precision
//!   float), D (double-precision float), C (compressed)
//! - ABIs: LP64, LP64D, LP64F, ILP32, ILP32D, ILP32F
//!
//! Modules:
//! - riscv_register_info: Complete register definitions (GPRs + FPRs)
//! - riscv_instr_info: Full instruction descriptor table covering RV32I,
//!   RV64I, M, A, F, D, and C extensions including pseudo-instructions
//! - riscv_calling_convention: psABI-compliant calling convention
//!   implementations for all LP64/ILP32 variants

pub mod riscv_asm_printer;
pub mod riscv_bitmanip_isel;
pub mod riscv_calling_convention;
pub mod riscv_crypto_isel;
pub mod riscv_deep;
pub mod riscv_frame_lowering;
pub mod riscv_hypervisor_isel;
pub mod riscv_instr_info;
pub mod riscv_isel;
pub mod riscv_mc_decoder;
pub mod riscv_mc_encoder;
pub mod riscv_optimize;
pub mod riscv_register_info;
pub mod riscv_subtarget;
pub mod riscv_target_machine;
pub mod riscv_vector_isel;
pub mod riscv_x86_bridge;

// Re-export key types for convenience
pub use riscv_asm_printer::RiscVAsmPrinter;
pub use riscv_bitmanip_isel::{
    riscv_bitmanip_isel_table, BitmanipPattern, RiscVBitmanipIselEngine, RiscVBitmanipIselTable,
};
pub use riscv_calling_convention::{
    RiscVArgClass, RiscVArgInfo, RiscVCallFrame, RiscVCallingConvention, RiscVTypeInfo,
};
pub use riscv_crypto_isel::{
    build_riscv_crypto_isel_table, CryptoOperation, RiscVCryptoFeatures, RiscVCryptoIselEngine,
    RiscVCryptoIselTable, RiscVCryptoPattern,
};
pub use riscv_hypervisor_isel::{
    build_riscv_hypervisor_isel_table, hypervisor_csrs, RiscVHypervisorFeatures,
    RiscVHypervisorIselEngine, RiscVHypervisorIselTable, RiscVHypervisorPattern,
};
pub use riscv_instr_info::{RiscVInstrDesc, RiscVInstrInfo, RiscVOpcode, RiscVOperandType};
pub use riscv_isel::RiscVInstructionSelector;
pub use riscv_mc_decoder::RiscVMCDecoder;
pub use riscv_mc_encoder::RiscVMCEncoder;
pub use riscv_optimize::{RiscVOptStats, RiscVPeepholeOptimizer};
pub use riscv_register_info::{
    RiscVRegClass, RiscVRegisterInfo, FPR_BASE, GPR_BASE, RV_FPR_COUNT, RV_GPR_COUNT, RV_MAX_REG_ID,
};
pub use riscv_subtarget::RiscVSubtarget;
pub use riscv_target_machine::{CodeModel, OptimizationLevel, RelocModel, RiscVTargetMachine};
pub use riscv_vector_isel::{
    RVVAsmEmitter, RVVConfig, RiscVVectorISel, RiscVVectorOpcode, RVVLMUL, RVVSEW,
};
pub use riscv_x86_bridge::{
    build_riscv_to_x86_map, build_x86_to_riscv_map, compare_instruction_cost, riscv_opcode_cost,
    x86_opcode_cost, AliasRelation, AllocationStrategy, ArgPassingClass, BranchComparison,
    BridgeConfig, BridgeInstruction, BridgeRISCVCallingConvention, BridgeRISCVFrameLowering,
    BridgeRISCVInstrInfo, BridgeRISCVTargetMachine, BridgeRISCvRegisterInfo, BridgeStats,
    CodeSizeComparison, ComparisonMetrics, ConstraintType, CostComparison,
    CrossTargetBranchAnalyzer, CrossTargetConstMaterializer, CrossTargetFrameLowering,
    CrossTargetLowering, CrossTargetOptResult, CrossTargetRISCV, CrossTargetRegisterAlloc,
    ExtensionFlags, ISetComparison, LiveInterval, LoweringRule, OptimizationComparison,
    PatternCategory, PerformanceComparison, RISCVX86Bridge, RegisterAlias, ReplacementStep,
    RiscVABI, SharedFrameLoweringContext, SharedISelMatch, SharedISelPatterns, SharedPattern,
    SharedRegClass, SharedRegisterAllocContext, SpillSlotInfo, TargetArch, TargetFeatureSet,
    X86RISCVComparisons, RV32_DATA_LAYOUT, RV64_DATA_LAYOUT, RV_FPR_NAMES, RV_GPR_NAMES,
    RV_VR_NAMES,
};

/// RISC-V endianness is little-endian.
pub const RISCV_ENDIANNESS: &str = "little";

/// RISC-V stack alignment for RV32 and RV64 (16 bytes per psABI).
pub const RISCV_STACK_ALIGNMENT: u32 = 16;

/// RISC-V red zone size (none defined by psABI).
pub const RISCV_RED_ZONE_SIZE: u32 = 0;

/// Default RISC-V page size (4 KiB).
pub const RISCV_PAGE_SIZE: u32 = 4096;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_riscv_constants() {
        assert_eq!(RISCV_ENDIANNESS, "little");
        assert_eq!(RISCV_STACK_ALIGNMENT, 16);
        assert_eq!(RISCV_RED_ZONE_SIZE, 0);
        assert_eq!(RISCV_PAGE_SIZE, 4096);
    }
}