llvm-native-core 0.1.10

//! NVPTX Target Backend — NVIDIA CUDA PTX virtual ISA.
//!
//! Clean-room behavioral reconstruction from the NVIDIA PTX ISA
//! Reference Manual and CUDA Toolkit documentation.
//! Zero LLVM source code consultation.
//!
//! PTX is a virtual ISA for NVIDIA GPUs. It uses unlimited virtual
//! registers in SSA form with no fixed physical register file.
//! Instructions use a 3-operand format.
//!
//! Modules:
//! - nvptx_register_info: Virtual registers, special registers,
//!   predicate registers
//! - nvptx_instr_info: Full PTX instruction descriptor table
//! - nvptx_isel: Instruction selection from LLVM IR to PTX
//! - nvptx_mc_encoder: PTX assembly text encoder (PTX is text-based)
//! - nvptx_asm_printer: PTX assembly printer

pub mod nvptx_asm_printer;
pub mod nvptx_instr_info;
pub mod nvptx_isel;
pub mod nvptx_isel_full;
pub mod nvptx_mc_encoder;
pub mod nvptx_register_info;
pub mod nvptx_target_machine;
pub mod nvptx_x86_bridge;

pub use nvptx_asm_printer::NvptxAsmPrinter;
pub use nvptx_instr_info::{NvptxInstrDesc, NvptxInstrInfo, NvptxOpcode, NvptxOperandType};
pub use nvptx_isel::NvptxInstructionSelector;
pub use nvptx_isel_full::{
    CcPattern, ComputeCapability, NvptxFullInstructionSelector, PtxAddrSpace, PtxAtomicOp, PtxType,
};
pub use nvptx_mc_encoder::NvptxMCEncoder;
pub use nvptx_register_info::{NvptxRegClass, NvptxRegisterInfo};
pub use nvptx_target_machine::NvptxTargetMachine;

/// PTX address size in bits (32 or 64).
pub const NVPTX_ADDRESS_SIZE: u32 = 64;

/// PTX warp size (always 32 threads per warp).
pub const NVPTX_WARP_SIZE: u32 = 32;

/// Maximum number of threads per block.
pub const NVPTX_MAX_THREADS_PER_BLOCK: u32 = 1024;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_nvptx_constants() {
        assert_eq!(NVPTX_ADDRESS_SIZE, 64);
        assert_eq!(NVPTX_WARP_SIZE, 32);
        assert_eq!(NVPTX_MAX_THREADS_PER_BLOCK, 1024);
    }
}