llvm-native-core 0.1.10

//! MSP430 ↔ X86 Bridge Module — shared codegen abstractions,
//! cross-target optimization infrastructure, MSP430 backend foundation
//! classes, and X86/MSP430 comparative analysis tooling.
//!
//! This module serves as the bridge between the mature X86 backend
//! and the MSP430 backend, enabling:
//!
//! - Shared instruction selection patterns between MSP430 and X86
//! - Target-independent lowering rules that apply to both architectures
//! - Common register allocation framework abstractions
//! - Shared frame lowering abstractions and stack layout conventions
//! - Cross-target code size and performance analysis
//! - MSP430 target machine construction and configuration
//!
//! Architecture coverage:
//! - MSP430: 16-bit core, 27 core instructions + 24 emulated
//! - MSP430X: 20-bit extensions (MOVA, CALLA, PUSHM, POPM, etc.)
//! - X86-64 and IA-32 counterparts for all comparisons
//!
//! Clean-room design: all behavior reconstructed from MSP430x1xx
//! Family User's Guide, MSP430 ABI, Intel/AMD architecture manuals,
//! and System V AMD64 ABI. Zero LLVM source code consultation.

// ============================================================================
// §1: MSP430X86Bridge — Main Bridge Struct
// ============================================================================

use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet};
use std::fmt;

use super::msp430_instr_info::{Msp430InstrDesc, Msp430InstrInfo, Msp430Opcode, Msp430OperandType};
use super::msp430_register_info::{
    Msp430RegClass, Msp430RegisterInfo, MSP430_GPR_BASE, MSP430_GPR_COUNT, MSP430_MAX_REG_ID,
};
use crate::x86::x86_calling_convention::{X86CallFrame, X86CallingConvention};
use crate::x86::x86_frame_lowering::{X86FrameInfo, X86FrameLowering};
use crate::x86::x86_instr_info::{X86InstrDesc, X86InstrInfo, X86Opcode};
use crate::x86::x86_register_info::{X86RegisterInfo, X86_32_REG_COUNT, X86_64_REG_COUNT};
use crate::x86::x86_target_machine::X86TargetMachine;
use crate::x86::X86PeepholeOptimizer;

/// Main bridge coordinator between MSP430 and X86 backends.
///
/// Provides cross-target instruction selection pattern sharing,
/// register allocation strategy alignment, and optimization
/// transfer between the two architectures.
pub struct MSP430X86Bridge {
    /// MSP430 instruction info
    pub msp430_instr_info: Msp430InstrInfo,
    /// X86 instruction info
    pub x86_instr_info: X86InstrInfo,
    /// MSP430 register info
    pub msp430_reg_info: Msp430RegisterInfo,
    /// X86 register info
    pub x86_reg_info: X86RegisterInfo,
    /// Shared instruction selection patterns
    pub shared_isel_patterns: SharedISelPatterns,
    /// Cross-target lowering rules
    pub cross_target_rules: CrossTargetLowering,
    /// Shared register allocation context
    pub shared_ra_context: SharedRegisterAllocContext,
    /// Shared frame lowering context
    pub shared_frame_context: SharedFrameLoweringContext,
    /// Bridge configuration
    pub config: BridgeConfig,
    /// Statistics for cross-target operations
    pub stats: BridgeStats,
}

/// Configuration for the MSP430 ↔ X86 bridge.
#[derive(Debug, Clone)]
pub struct BridgeConfig {
    /// Whether to enable shared ISel patterns
    pub enable_shared_isel: bool,
    /// Whether to enable cross-target optimization
    pub enable_cross_target_opt: bool,
    /// Whether to enable shared register allocation
    pub enable_shared_ra: bool,
    /// Whether to enable shared frame lowering
    pub enable_shared_frame: bool,
    /// Maximum shared ISel pattern depth
    pub max_pattern_depth: usize,
    /// Optimization transfer threshold (cost ratio)
    pub opt_transfer_threshold: f64,
    /// Whether to collect statistics
    pub collect_stats: bool,
    /// Verbose logging
    pub verbose: bool,
    /// Target variant: "msp430" or "msp430x"
    pub target_variant: String,
}

impl Default for BridgeConfig {
    fn default() -> Self {
        Self {
            enable_shared_isel: true,
            enable_cross_target_opt: true,
            enable_shared_ra: true,
            enable_shared_frame: true,
            max_pattern_depth: 6,
            opt_transfer_threshold: 1.5,
            collect_stats: true,
            verbose: false,
            target_variant: "msp430".into(),
        }
    }
}

/// Bridge operation statistics.
#[derive(Debug, Default, Clone)]
pub struct BridgeStats {
    /// Number of shared ISel patterns matched
    pub shared_isel_matches: u64,
    /// Number of cross-target optimizations applied
    pub cross_target_opts: u64,
    /// Number of shared RA decisions
    pub shared_ra_decisions: u64,
    /// Number of shared frame operations
    pub shared_frame_ops: u64,
    /// Number of pattern translations
    pub pattern_translations: u64,
    /// Total time in microseconds (estimated)
    pub total_time_us: u64,
    /// Number of successful cross-target transfers
    pub successful_transfers: u64,
    /// Number of failed cross-target transfers
    pub failed_transfers: u64,
}

impl fmt::Display for BridgeStats {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        writeln!(f, "MSP430 ↔ X86 Bridge Statistics:")?;
        writeln!(
            f,
            "  Shared ISel matches:       {}",
            self.shared_isel_matches
        )?;
        writeln!(
            f,
            "  Cross-target optimizations: {}",
            self.cross_target_opts
        )?;
        writeln!(
            f,
            "  Shared RA decisions:       {}",
            self.shared_ra_decisions
        )?;
        writeln!(f, "  Shared frame operations:   {}", self.shared_frame_ops)?;
        writeln!(
            f,
            "  Pattern translations:      {}",
            self.pattern_translations
        )?;
        writeln!(
            f,
            "  Successful transfers:      {}",
            self.successful_transfers
        )?;
        writeln!(f, "  Failed transfers:          {}", self.failed_transfers)?;
        write!(f, "  Total time (est):          {} µs", self.total_time_us)
    }
}

impl MSP430X86Bridge {
    /// Create a new MSP430 ↔ X86 bridge.
    pub fn new() -> Self {
        Self {
            msp430_instr_info: Msp430InstrInfo::new(),
            x86_instr_info: X86InstrInfo::new(),
            msp430_reg_info: Msp430RegisterInfo,
            x86_reg_info: X86RegisterInfo,
            shared_isel_patterns: SharedISelPatterns::new(),
            cross_target_rules: CrossTargetLowering::new(),
            shared_ra_context: SharedRegisterAllocContext::new(),
            shared_frame_context: SharedFrameLoweringContext::new(),
            config: BridgeConfig::default(),
            stats: BridgeStats::default(),
        }
    }

    /// Create a bridge with custom configuration.
    pub fn with_config(config: BridgeConfig) -> Self {
        let mut bridge = Self::new();
        bridge.config = config;
        bridge
    }

    /// Initialize the bridge, loading all shared patterns and rules.
    pub fn initialize(&mut self) {
        if self.config.verbose {
            self.log("Initializing MSP430 ↔ X86 bridge...");
        }
        self.shared_isel_patterns.load_patterns();
        self.cross_target_rules.load_rules();
        self.shared_ra_context.initialize();
        self.shared_frame_context.initialize();
        if self.config.verbose {
            self.log("Bridge initialization complete.");
        }
    }

    /// Translate an X86 instruction opcode to its MSP430 equivalent.
    pub fn translate_x86_to_msp430(&mut self, x86_opcode: &X86Opcode) -> Option<BridgeInstruction> {
        self.stats.pattern_translations += 1;
        match x86_opcode {
            // Arithmetic
            X86Opcode::ADD => Some(BridgeInstruction::DirectMap(Msp430Opcode::ADD)),
            X86Opcode::ADC => Some(BridgeInstruction::DirectMap(Msp430Opcode::ADDC)),
            X86Opcode::SUB => Some(BridgeInstruction::DirectMap(Msp430Opcode::SUB)),
            X86Opcode::SBB => Some(BridgeInstruction::DirectMap(Msp430Opcode::SUBC)),
            X86Opcode::AND => Some(BridgeInstruction::DirectMap(Msp430Opcode::AND)),
            X86Opcode::OR => Some(BridgeInstruction::DirectMap(Msp430Opcode::BIS)),
            X86Opcode::XOR => Some(BridgeInstruction::DirectMap(Msp430Opcode::XOR)),
            X86Opcode::NOT => Some(BridgeInstruction::DirectMap(Msp430Opcode::INV)),
            X86Opcode::NEG => Some(BridgeInstruction::Expanded(vec![
                Msp430Opcode::INV,
                Msp430Opcode::INC,
            ])),
            X86Opcode::INC => Some(BridgeInstruction::DirectMap(Msp430Opcode::ADD)), // ADD #1
            X86Opcode::DEC => Some(BridgeInstruction::DirectMap(Msp430Opcode::SUB)), // SUB #1
            // Compare
            X86Opcode::CMP => Some(BridgeInstruction::DirectMap(Msp430Opcode::CMP)),
            X86Opcode::TEST => Some(BridgeInstruction::DirectMap(Msp430Opcode::BIT)),
            // Moves
            X86Opcode::MOV => Some(BridgeInstruction::DirectMap(Msp430Opcode::MOV)),
            X86Opcode::PUSH => Some(BridgeInstruction::DirectMap(Msp430Opcode::PUSH)),
            X86Opcode::POP => Some(BridgeInstruction::DirectMap(Msp430Opcode::POP)),
            X86Opcode::XCHG => Some(BridgeInstruction::Expanded(vec![
                Msp430Opcode::MOV,
                Msp430Opcode::MOV,
                Msp430Opcode::MOV,
            ])),
            // Shifts
            X86Opcode::SHL => Some(BridgeInstruction::DirectMap(Msp430Opcode::RLA)),
            X86Opcode::SHR => Some(BridgeInstruction::DirectMap(Msp430Opcode::RRC)), // with CLRC
            X86Opcode::SAR => Some(BridgeInstruction::DirectMap(Msp430Opcode::RRA)),
            X86Opcode::ROL => Some(BridgeInstruction::DirectMap(Msp430Opcode::RLC)),
            X86Opcode::ROR => Some(BridgeInstruction::DirectMap(Msp430Opcode::RRC)),
            // Control Flow
            X86Opcode::JMP => Some(BridgeInstruction::DirectMap(Msp430Opcode::JMP)),
            X86Opcode::JE => Some(BridgeInstruction::DirectMap(Msp430Opcode::JEQ)),
            X86Opcode::JNE => Some(BridgeInstruction::DirectMap(Msp430Opcode::JNE)),
            X86Opcode::JB => Some(BridgeInstruction::DirectMap(Msp430Opcode::JC)),
            X86Opcode::JAE => Some(BridgeInstruction::DirectMap(Msp430Opcode::JNC)),
            X86Opcode::JL => Some(BridgeInstruction::DirectMap(Msp430Opcode::JL)),
            X86Opcode::JGE => Some(BridgeInstruction::DirectMap(Msp430Opcode::JGE)),
            X86Opcode::JS => Some(BridgeInstruction::DirectMap(Msp430Opcode::JN)),
            X86Opcode::CALL => Some(BridgeInstruction::DirectMap(Msp430Opcode::CALL)),
            X86Opcode::RET => Some(BridgeInstruction::DirectMap(Msp430Opcode::RET)),
            X86Opcode::NOP => Some(BridgeInstruction::DirectMap(Msp430Opcode::NOP)),
            _ => {
                self.stats.failed_transfers += 1;
                None
            }
        }
    }

    /// Translate an MSP430 instruction opcode to its X86 equivalent.
    pub fn translate_msp430_to_x86(
        &mut self,
        msp430_opcode: &Msp430Opcode,
    ) -> Option<BridgeInstruction> {
        self.stats.pattern_translations += 1;
        match msp430_opcode {
            // Arithmetic (double-operand)
            Msp430Opcode::MOV => Some(BridgeInstruction::DirectMapX86(X86Opcode::MOV)),
            Msp430Opcode::ADD => Some(BridgeInstruction::DirectMapX86(X86Opcode::ADD)),
            Msp430Opcode::ADDC => Some(BridgeInstruction::DirectMapX86(X86Opcode::ADC)),
            Msp430Opcode::SUBC => Some(BridgeInstruction::DirectMapX86(X86Opcode::SBB)),
            Msp430Opcode::SUB => Some(BridgeInstruction::DirectMapX86(X86Opcode::SUB)),
            Msp430Opcode::CMP => Some(BridgeInstruction::DirectMapX86(X86Opcode::CMP)),
            Msp430Opcode::DADD => Some(BridgeInstruction::ExpandedX86(vec![
                X86Opcode::ADD,
                X86Opcode::ADC,
            ])),
            Msp430Opcode::BIT => Some(BridgeInstruction::DirectMapX86(X86Opcode::TEST)),
            Msp430Opcode::BIC => Some(BridgeInstruction::ExpandedX86(vec![
                X86Opcode::NOT,
                X86Opcode::AND,
            ])),
            Msp430Opcode::BIS => Some(BridgeInstruction::DirectMapX86(X86Opcode::OR)),
            Msp430Opcode::XOR => Some(BridgeInstruction::DirectMapX86(X86Opcode::XOR)),
            Msp430Opcode::AND => Some(BridgeInstruction::DirectMapX86(X86Opcode::AND)),
            // Single-operand
            Msp430Opcode::RRC => Some(BridgeInstruction::DirectMapX86(X86Opcode::ROR)),
            Msp430Opcode::SWPB => Some(BridgeInstruction::DirectMapX86(X86Opcode::BSWAP)),
            Msp430Opcode::RRA => Some(BridgeInstruction::DirectMapX86(X86Opcode::SAR)),
            Msp430Opcode::SXT => Some(BridgeInstruction::DirectMapX86(X86Opcode::MOVSX)),
            Msp430Opcode::PUSH => Some(BridgeInstruction::DirectMapX86(X86Opcode::PUSH)),
            Msp430Opcode::POP => Some(BridgeInstruction::DirectMapX86(X86Opcode::POP)),
            Msp430Opcode::CALL => Some(BridgeInstruction::DirectMapX86(X86Opcode::CALL)),
            Msp430Opcode::RETI => Some(BridgeInstruction::DirectMapX86(X86Opcode::RET)),
            // Jumps
            Msp430Opcode::JNE => Some(BridgeInstruction::DirectMapX86(X86Opcode::JNE)),
            Msp430Opcode::JEQ => Some(BridgeInstruction::DirectMapX86(X86Opcode::JE)),
            Msp430Opcode::JNC => Some(BridgeInstruction::DirectMapX86(X86Opcode::JAE)),
            Msp430Opcode::JC => Some(BridgeInstruction::DirectMapX86(X86Opcode::JB)),
            Msp430Opcode::JN => Some(BridgeInstruction::DirectMapX86(X86Opcode::JS)),
            Msp430Opcode::JGE => Some(BridgeInstruction::DirectMapX86(X86Opcode::JGE)),
            Msp430Opcode::JL => Some(BridgeInstruction::DirectMapX86(X86Opcode::JL)),
            Msp430Opcode::JMP => Some(BridgeInstruction::DirectMapX86(X86Opcode::JMP)),
            // Emulated
            Msp430Opcode::CLR => Some(BridgeInstruction::DirectMapX86(X86Opcode::XOR)),
            Msp430Opcode::CLRC => Some(BridgeInstruction::ExpandedX86(vec![
                X86Opcode::AND,
                X86Opcode::NOT,
            ])),
            Msp430Opcode::SETC => Some(BridgeInstruction::DirectMapX86(X86Opcode::OR)),
            Msp430Opcode::CLRZ => Some(BridgeInstruction::ExpandedX86(vec![
                X86Opcode::AND,
                X86Opcode::NOT,
            ])),
            Msp430Opcode::SETZ => Some(BridgeInstruction::DirectMapX86(X86Opcode::OR)),
            Msp430Opcode::NOP => Some(BridgeInstruction::DirectMapX86(X86Opcode::NOP)),
            Msp430Opcode::BR => Some(BridgeInstruction::DirectMapX86(X86Opcode::JMP)),
            Msp430Opcode::RET => Some(BridgeInstruction::DirectMapX86(X86Opcode::RET)),
            Msp430Opcode::TST => Some(BridgeInstruction::DirectMapX86(X86Opcode::TEST)),
            Msp430Opcode::INV => Some(BridgeInstruction::DirectMapX86(X86Opcode::NOT)),
            Msp430Opcode::RLA => Some(BridgeInstruction::DirectMapX86(X86Opcode::SHL)),
            Msp430Opcode::RLC => Some(BridgeInstruction::DirectMapX86(X86Opcode::ROL)),
            Msp430Opcode::ADC => Some(BridgeInstruction::DirectMapX86(X86Opcode::ADC)),
            Msp430Opcode::DADC => Some(BridgeInstruction::ExpandedX86(vec![
                X86Opcode::ADC,
                X86Opcode::ADC,
            ])),
            _ => {
                self.stats.failed_transfers += 1;
                None
            }
        }
    }

    /// Match a shared ISel pattern for a given operation.
    pub fn match_shared_isel(&mut self, op_name: &str, is_msp430: bool) -> Option<SharedISelMatch> {
        if self.config.collect_stats {
            self.stats.shared_isel_matches += 1;
        }
        self.shared_isel_patterns.find(op_name, is_msp430)
    }

    /// Apply cross-target optimization rules.
    pub fn apply_cross_target_opt(&mut self, ir_sequence: &[&str]) -> Vec<CrossTargetOptResult> {
        self.stats.cross_target_opts += 1;
        self.cross_target_rules.apply(ir_sequence)
    }

    /// Get the shared register allocation context.
    pub fn get_shared_ra_context(&self) -> &SharedRegisterAllocContext {
        &self.shared_ra_context
    }

    /// Get the mutable shared register allocation context.
    pub fn get_shared_ra_context_mut(&mut self) -> &mut SharedRegisterAllocContext {
        &mut self.shared_ra_context
    }

    /// Get the shared frame lowering context.
    pub fn get_shared_frame_context(&self) -> &SharedFrameLoweringContext {
        &self.shared_frame_context
    }

    /// Get mutable shared frame lowering context.
    pub fn get_shared_frame_context_mut(&mut self) -> &mut SharedFrameLoweringContext {
        &mut self.shared_frame_context
    }

    /// Reset statistics.
    pub fn reset_stats(&mut self) {
        self.stats = BridgeStats::default();
    }

    fn log(&self, msg: &str) {
        if self.config.verbose {
            eprintln!("[MSP430-X86-Bridge] {}", msg);
        }
    }
}

impl Default for MSP430X86Bridge {
    fn default() -> Self {
        Self::new()
    }
}

impl fmt::Debug for MSP430X86Bridge {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        f.debug_struct("MSP430X86Bridge")
            .field("config", &self.config)
            .field("stats", &self.stats)
            .finish()
    }
}

/// Result of translating an instruction between architectures.
#[derive(Debug, Clone)]
pub enum BridgeInstruction {
    /// One-to-one direct mapping to MSP430
    DirectMap(Msp430Opcode),
    /// Direct mapping for X86 target.
    DirectMapX86(X86Opcode),
    /// Requires multiple MSP430 instructions to express.
    Expanded(Vec<Msp430Opcode>),
    /// Requires multiple X86 instructions to express.
    ExpandedX86(Vec<X86Opcode>),
    /// Comparison-specific mapping (MSP430 has CMP, X86 has CMP + SETcc)
    CompareMapX86 { cmp: X86Opcode, set: X86Opcode },
    /// Memory operand expansion.
    MemoryExpand(Vec<Msp430Opcode>),
}

// ============================================================================
// §2: CrossTargetMSP430 — Cross-Target Infrastructure
// ============================================================================

/// Complete cross-target infrastructure for MSP430 code generation
/// that leverages X86 backend knowledge and patterns.
pub struct CrossTargetMSP430 {
    /// Shared instruction selection patterns
    pub isel_patterns: SharedISelPatterns,
    /// Target-independent lowering rules
    pub lowering_rules: CrossTargetLowering,
    /// Shared register allocation framework
    pub regalloc_framework: CrossTargetRegisterAlloc,
    /// Shared frame lowering abstractions
    pub frame_abstractions: CrossTargetFrameLowering,
    /// Cross-target constant materialization
    pub const_materializer: CrossTargetConstMaterializer,
    /// Cross-target branch analysis
    pub branch_analyzer: CrossTargetBranchAnalyzer,
    /// Feature set for the target
    pub features: MSP430FeatureSet,
}

impl CrossTargetMSP430 {
    /// Create a new cross-target MSP430 infrastructure.
    pub fn new() -> Self {
        Self {
            isel_patterns: SharedISelPatterns::new(),
            lowering_rules: CrossTargetLowering::new(),
            regalloc_framework: CrossTargetRegisterAlloc::new(),
            frame_abstractions: CrossTargetFrameLowering::new(),
            const_materializer: CrossTargetConstMaterializer::new(),
            branch_analyzer: CrossTargetBranchAnalyzer::new(),
            features: MSP430FeatureSet::default(),
        }
    }

    /// Create with a specific feature set.
    pub fn with_features(features: MSP430FeatureSet) -> Self {
        let mut ctx = Self::new();
        ctx.features = features;
        ctx
    }
}

impl Default for CrossTargetMSP430 {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// §2.1: Shared Instruction Selection Patterns
// ============================================================================

/// Collection of shared ISel patterns that apply to both MSP430 and X86.
pub struct SharedISelPatterns {
    /// Patterns indexed by operation name
    patterns: HashMap<String, SharedPattern>,
    /// MSP430-specific variants
    msp430_variants: HashMap<String, Vec<Msp430Opcode>>,
    /// X86-specific variants
    x86_variants: HashMap<String, Vec<X86Opcode>>,
    /// Pattern categories
    categories: HashMap<PatternCategory, Vec<String>>,
}

/// A shared instruction selection pattern.
#[derive(Debug, Clone)]
pub struct SharedPattern {
    /// Human-readable name
    pub name: String,
    /// The category of this pattern
    pub category: PatternCategory,
    /// MSP430 opcode sequence
    pub msp430_seq: Vec<Msp430Opcode>,
    /// X86 opcode sequence
    pub x86_seq: Vec<X86Opcode>,
    /// Cost on MSP430 (cycles, approximate)
    pub msp430_cost: u32,
    /// Cost on X86 (cycles, approximate)
    pub x86_cost: u32,
    /// Whether this pattern is commutative
    pub is_commutative: bool,
    /// Minimum operand count
    pub min_operands: usize,
    /// Maximum operand count
    pub max_operands: usize,
}

/// Categories of shared ISel patterns.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum PatternCategory {
    /// Integer arithmetic
    IntegerArithmetic,
    /// Integer comparison
    IntegerComparison,
    /// Logical operations
    Logical,
    /// Shift operations
    Shift,
    /// Memory access
    MemoryAccess,
    /// Control flow
    ControlFlow,
    /// Bit manipulation
    BitManipulation,
    /// Byte manipulation
    ByteManipulation,
    /// Constant materialization
    ConstantMaterialization,
}

impl fmt::Display for PatternCategory {
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Self::IntegerArithmetic => write!(f, "IntegerArithmetic"),
            Self::IntegerComparison => write!(f, "IntegerComparison"),
            Self::Logical => write!(f, "Logical"),
            Self::Shift => write!(f, "Shift"),
            Self::MemoryAccess => write!(f, "MemoryAccess"),
            Self::ControlFlow => write!(f, "ControlFlow"),
            Self::BitManipulation => write!(f, "BitManipulation"),
            Self::ByteManipulation => write!(f, "ByteManipulation"),
            Self::ConstantMaterialization => write!(f, "ConstantMaterialization"),
        }
    }
}

impl SharedISelPatterns {
    /// Create an empty pattern collection.
    pub fn new() -> Self {
        Self {
            patterns: HashMap::new(),
            msp430_variants: HashMap::new(),
            x86_variants: HashMap::new(),
            categories: HashMap::new(),
        }
    }

    /// Load all predefined shared patterns.
    pub fn load_patterns(&mut self) {
        self.load_integer_arithmetic_patterns();
        self.load_integer_comparison_patterns();
        self.load_logical_patterns();
        self.load_shift_patterns();
        self.load_memory_access_patterns();
        self.load_control_flow_patterns();
        self.load_bit_manipulation_patterns();
        self.load_byte_manipulation_patterns();
        self.load_constant_patterns();
    }

    fn add_pattern(&mut self, pattern: SharedPattern) {
        let name = pattern.name.clone();
        let cat = pattern.category;
        self.patterns.insert(name, pattern.clone());
        self.categories
            .entry(cat)
            .or_insert_with(Vec::new)
            .push(pattern.name);
    }

    fn load_integer_arithmetic_patterns(&mut self) {
        // Add 16-bit — direct match
        self.add_pattern(SharedPattern {
            name: "add_16bit".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::ADD],
            x86_seq: vec![X86Opcode::ADD],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // Subtract 16-bit
        self.add_pattern(SharedPattern {
            name: "sub_16bit".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::SUB],
            x86_seq: vec![X86Opcode::SUB],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Add with carry (multi-word arithmetic)
        self.add_pattern(SharedPattern {
            name: "add_with_carry".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::ADDC],
            x86_seq: vec![X86Opcode::ADC],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // Subtract with borrow
        self.add_pattern(SharedPattern {
            name: "sub_with_borrow".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::SUBC],
            x86_seq: vec![X86Opcode::SBB],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // BCD add (DADD on MSP430 is unique; X86 uses DAA after ADD)
        self.add_pattern(SharedPattern {
            name: "decimal_add".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::DADD],
            x86_seq: vec![X86Opcode::ADD],
            msp430_cost: 1,
            x86_cost: 2,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // Negate (INV + INC on MSP430, NEG on X86)
        self.add_pattern(SharedPattern {
            name: "negate_16bit".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::INV, Msp430Opcode::ADD],
            x86_seq: vec![X86Opcode::NEG],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Increment (ADD #1)
        self.add_pattern(SharedPattern {
            name: "increment".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::ADD],
            x86_seq: vec![X86Opcode::INC],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Decrement (SUB #1)
        self.add_pattern(SharedPattern {
            name: "decrement".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::SUB],
            x86_seq: vec![X86Opcode::DEC],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Sign extend byte to word (SXT on MSP430 = MOVSX on X86)
        self.add_pattern(SharedPattern {
            name: "sign_extend_byte".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::SXT],
            x86_seq: vec![X86Opcode::MOVSX],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // 16-bit multiply — MSP430 has no MUL in basic ISA, X86 has MUL/IMUL
        self.add_pattern(SharedPattern {
            name: "multiply_16bit".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![
                Msp430Opcode::MOV,
                Msp430Opcode::MOV,
                Msp430Opcode::AND,
                Msp430Opcode::ADD,
                Msp430Opcode::RLA,
                Msp430Opcode::JC,
                Msp430Opcode::ADD,
            ],
            x86_seq: vec![X86Opcode::IMUL],
            msp430_cost: 60,
            x86_cost: 3,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // Clear register (MOV #0 is CLR on MSP430, XOR reg,reg on X86)
        self.add_pattern(SharedPattern {
            name: "clear_register".into(),
            category: PatternCategory::IntegerArithmetic,
            msp430_seq: vec![Msp430Opcode::CLR],
            x86_seq: vec![X86Opcode::XOR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });
    }

    fn load_integer_comparison_patterns(&mut self) {
        // Compare (CMP on both)
        self.add_pattern(SharedPattern {
            name: "compare_16bit".into(),
            category: PatternCategory::IntegerComparison,
            msp430_seq: vec![Msp430Opcode::CMP],
            x86_seq: vec![X86Opcode::CMP],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Bit test
        self.add_pattern(SharedPattern {
            name: "bit_test".into(),
            category: PatternCategory::IntegerComparison,
            msp430_seq: vec![Msp430Opcode::BIT],
            x86_seq: vec![X86Opcode::TEST],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // Test if register is zero (TST on MSP430, TEST on X86)
        self.add_pattern(SharedPattern {
            name: "test_zero".into(),
            category: PatternCategory::IntegerComparison,
            msp430_seq: vec![Msp430Opcode::TST],
            x86_seq: vec![X86Opcode::TEST],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Set if less than (CMP + JL vs CMP + SETL)
        self.add_pattern(SharedPattern {
            name: "set_if_less_than".into(),
            category: PatternCategory::IntegerComparison,
            msp430_seq: vec![Msp430Opcode::CMP, Msp430Opcode::JL],
            x86_seq: vec![X86Opcode::CMP, X86Opcode::SETL],
            msp430_cost: 2,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Set if equal
        self.add_pattern(SharedPattern {
            name: "set_if_equal".into(),
            category: PatternCategory::IntegerComparison,
            msp430_seq: vec![Msp430Opcode::CMP, Msp430Opcode::JEQ],
            x86_seq: vec![X86Opcode::CMP, X86Opcode::SETE],
            msp430_cost: 2,
            x86_cost: 2,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });
    }

    fn load_logical_patterns(&mut self) {
        // AND
        self.add_pattern(SharedPattern {
            name: "logical_and".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::AND],
            x86_seq: vec![X86Opcode::AND],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // OR (BIS on MSP430 is OR on X86)
        self.add_pattern(SharedPattern {
            name: "logical_or".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::BIS],
            x86_seq: vec![X86Opcode::OR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // XOR
        self.add_pattern(SharedPattern {
            name: "logical_xor".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::XOR],
            x86_seq: vec![X86Opcode::XOR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });

        // NOT (INV on MSP430)
        self.add_pattern(SharedPattern {
            name: "logical_not".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::INV],
            x86_seq: vec![X86Opcode::NOT],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Bit Clear (BIC = AND NOT)
        self.add_pattern(SharedPattern {
            name: "bit_clear".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::BIC],
            x86_seq: vec![X86Opcode::NOT, X86Opcode::AND],
            msp430_cost: 1,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Bit Set (BIS)
        self.add_pattern(SharedPattern {
            name: "bit_set".into(),
            category: PatternCategory::Logical,
            msp430_seq: vec![Msp430Opcode::BIS],
            x86_seq: vec![X86Opcode::OR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: true,
            min_operands: 2,
            max_operands: 2,
        });
    }

    fn load_shift_patterns(&mut self) {
        // Rotate right through carry
        self.add_pattern(SharedPattern {
            name: "rotate_right_carry".into(),
            category: PatternCategory::Shift,
            msp430_seq: vec![Msp430Opcode::RRC],
            x86_seq: vec![X86Opcode::RCR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Rotate left through carry
        self.add_pattern(SharedPattern {
            name: "rotate_left_carry".into(),
            category: PatternCategory::Shift,
            msp430_seq: vec![Msp430Opcode::RLC],
            x86_seq: vec![X86Opcode::RCL],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Arithmetic shift right
        self.add_pattern(SharedPattern {
            name: "arithmetic_shift_right".into(),
            category: PatternCategory::Shift,
            msp430_seq: vec![Msp430Opcode::RRA],
            x86_seq: vec![X86Opcode::SAR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Shift left (emulated via RLA = ADD on MSP430)
        self.add_pattern(SharedPattern {
            name: "shift_left".into(),
            category: PatternCategory::Shift,
            msp430_seq: vec![Msp430Opcode::RLA],
            x86_seq: vec![X86Opcode::SHL],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Multi-bit shift left via loop
        self.add_pattern(SharedPattern {
            name: "multi_shift_left".into(),
            category: PatternCategory::Shift,
            msp430_seq: vec![Msp430Opcode::RLA, Msp430Opcode::RLA, Msp430Opcode::RLA],
            x86_seq: vec![X86Opcode::SHL],
            msp430_cost: 3,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });
    }

    fn load_memory_access_patterns(&mut self) {
        // Load word (MOV @src, dst)
        self.add_pattern(SharedPattern {
            name: "load_word".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::MOV],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Store word
        self.add_pattern(SharedPattern {
            name: "store_word".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::MOV],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Push
        self.add_pattern(SharedPattern {
            name: "push".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::PUSH],
            x86_seq: vec![X86Opcode::PUSH],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Pop
        self.add_pattern(SharedPattern {
            name: "pop".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::POP],
            x86_seq: vec![X86Opcode::POP],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Indirect load (MOV @Rn, Rm)
        self.add_pattern(SharedPattern {
            name: "indirect_load".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::MOV],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Indexed load (MOV X(Rn), Rm)
        self.add_pattern(SharedPattern {
            name: "indexed_load".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::MOV],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 3,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 2,
            max_operands: 2,
        });

        // Byte swap (SWPB on MSP430 = BSWAP on X86, but SWPB swaps bytes within 16-bit word)
        self.add_pattern(SharedPattern {
            name: "byte_swap".into(),
            category: PatternCategory::MemoryAccess,
            msp430_seq: vec![Msp430Opcode::SWPB],
            x86_seq: vec![X86Opcode::MOV, X86Opcode::BSWAP, X86Opcode::SHR],
            msp430_cost: 1,
            x86_cost: 3,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });
    }

    fn load_control_flow_patterns(&mut self) {
        // Unconditional jump
        self.add_pattern(SharedPattern {
            name: "unconditional_jump".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JMP],
            x86_seq: vec![X86Opcode::JMP],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if equal
        self.add_pattern(SharedPattern {
            name: "branch_if_equal".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JEQ],
            x86_seq: vec![X86Opcode::JE],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if not equal
        self.add_pattern(SharedPattern {
            name: "branch_if_not_equal".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JNE],
            x86_seq: vec![X86Opcode::JNE],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if carry set (JC => JB)
        self.add_pattern(SharedPattern {
            name: "branch_if_carry".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JC],
            x86_seq: vec![X86Opcode::JB],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if no carry (JNC => JAE)
        self.add_pattern(SharedPattern {
            name: "branch_if_no_carry".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JNC],
            x86_seq: vec![X86Opcode::JAE],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if negative
        self.add_pattern(SharedPattern {
            name: "branch_if_negative".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JN],
            x86_seq: vec![X86Opcode::JS],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if greater or equal
        self.add_pattern(SharedPattern {
            name: "branch_if_ge".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JGE],
            x86_seq: vec![X86Opcode::JGE],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Branch if less
        self.add_pattern(SharedPattern {
            name: "branch_if_less".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::JL],
            x86_seq: vec![X86Opcode::JL],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Function call
        self.add_pattern(SharedPattern {
            name: "function_call".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::CALL],
            x86_seq: vec![X86Opcode::CALL],
            msp430_cost: 4,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Function return
        self.add_pattern(SharedPattern {
            name: "function_return".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::RET],
            x86_seq: vec![X86Opcode::RET],
            msp430_cost: 3,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Return from interrupt
        self.add_pattern(SharedPattern {
            name: "return_from_interrupt".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::RETI],
            x86_seq: vec![X86Opcode::RET],
            msp430_cost: 5,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // NOP
        self.add_pattern(SharedPattern {
            name: "nop".into(),
            category: PatternCategory::ControlFlow,
            msp430_seq: vec![Msp430Opcode::NOP],
            x86_seq: vec![X86Opcode::NOP],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });
    }

    fn load_bit_manipulation_patterns(&mut self) {
        // Set carry flag
        self.add_pattern(SharedPattern {
            name: "set_carry".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::SETC],
            x86_seq: vec![X86Opcode::STC],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Clear carry flag
        self.add_pattern(SharedPattern {
            name: "clear_carry".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::CLRC],
            x86_seq: vec![X86Opcode::CLC],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Set zero flag
        self.add_pattern(SharedPattern {
            name: "set_zero".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::SETZ],
            x86_seq: vec![X86Opcode::XOR, X86Opcode::CMP],
            msp430_cost: 1,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Enable interrupts (EINT on MSP430 = STI on X86)
        self.add_pattern(SharedPattern {
            name: "enable_interrupts".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::EINT],
            x86_seq: vec![X86Opcode::STI],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Disable interrupts (DINT = CLI)
        self.add_pattern(SharedPattern {
            name: "disable_interrupts".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::DINT],
            x86_seq: vec![X86Opcode::CLI],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Set negative flag
        self.add_pattern(SharedPattern {
            name: "set_negative".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::SETN],
            x86_seq: vec![X86Opcode::OR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });

        // Clear negative flag
        self.add_pattern(SharedPattern {
            name: "clear_negative".into(),
            category: PatternCategory::BitManipulation,
            msp430_seq: vec![Msp430Opcode::CLRN],
            x86_seq: vec![X86Opcode::AND, X86Opcode::NOT],
            msp430_cost: 1,
            x86_cost: 2,
            is_commutative: false,
            min_operands: 0,
            max_operands: 0,
        });
    }

    fn load_byte_manipulation_patterns(&mut self) {
        // Swap bytes within word
        self.add_pattern(SharedPattern {
            name: "swap_bytes_word".into(),
            category: PatternCategory::ByteManipulation,
            msp430_seq: vec![Msp430Opcode::SWPB],
            x86_seq: vec![X86Opcode::ROR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });
    }

    fn load_constant_patterns(&mut self) {
        // Load constant using constant generator (CG1=2, CG2=4, CG3=8, CG4=-1)
        // On MSP430, constants 0,1,2,4,8,-1 are free with CG registers
        self.add_pattern(SharedPattern {
            name: "load_constant_zero".into(),
            category: PatternCategory::ConstantMaterialization,
            msp430_seq: vec![Msp430Opcode::CLR],
            x86_seq: vec![X86Opcode::XOR],
            msp430_cost: 1,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Load 16-bit immediate (MOV #imm, Rn)
        self.add_pattern(SharedPattern {
            name: "load_16bit_immediate".into(),
            category: PatternCategory::ConstantMaterialization,
            msp430_seq: vec![Msp430Opcode::MOV],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 2,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });

        // Load 20-bit immediate (MSP430X MOVA)
        self.add_pattern(SharedPattern {
            name: "load_20bit_immediate".into(),
            category: PatternCategory::ConstantMaterialization,
            msp430_seq: vec![Msp430Opcode::MOVA],
            x86_seq: vec![X86Opcode::MOV],
            msp430_cost: 3,
            x86_cost: 1,
            is_commutative: false,
            min_operands: 1,
            max_operands: 1,
        });
    }

    /// Find a shared ISel pattern by name.
    pub fn find(&self, op_name: &str, _is_msp430: bool) -> Option<SharedISelMatch> {
        self.patterns.get(op_name).map(|p| SharedISelMatch {
            pattern: p.clone(),
            msp430_sequence: p.msp430_seq.clone(),
            x86_sequence: p.x86_seq.clone(),
            estimated_msp430_cost: p.msp430_cost,
            estimated_x86_cost: p.x86_cost,
        })
    }

    /// List all pattern names.
    pub fn list_patterns(&self) -> Vec<&String> {
        self.patterns.keys().collect()
    }

    /// List patterns by category.
    pub fn list_patterns_by_category(&self, category: PatternCategory) -> Vec<&String> {
        self.categories
            .get(&category)
            .map(|v| v.iter().collect())
            .unwrap_or_default()
    }

    /// Get total number of patterns.
    pub fn pattern_count(&self) -> usize {
        self.patterns.len()
    }
}

impl Default for SharedISelPatterns {
    fn default() -> Self {
        let mut patterns = Self::new();
        patterns.load_patterns();
        patterns
    }
}

/// A match result from shared ISel pattern lookup.
#[derive(Debug, Clone)]
pub struct SharedISelMatch {
    /// The matched pattern
    pub pattern: SharedPattern,
    /// MSP430 instruction sequence
    pub msp430_sequence: Vec<Msp430Opcode>,
    /// X86 instruction sequence
    pub x86_sequence: Vec<X86Opcode>,
    /// Estimated cost on MSP430
    pub estimated_msp430_cost: u32,
    /// Estimated cost on X86
    pub estimated_x86_cost: u32,
}

// ============================================================================
// §2.2: Cross-Target Lowering Rules
// ============================================================================

/// Target-independent lowering rules that work across architectures.
pub struct CrossTargetLowering {
    /// List of lowering rules
    rules: Vec<LoweringRule>,
    /// Rule index by name
    rule_index: HashMap<String, usize>,
}

/// A single lowering rule.
#[derive(Debug, Clone)]
pub struct LoweringRule {
    /// Unique name
    pub name: String,
    /// Target architectures this rule applies to
    pub targets: Vec<EmbeddedTarget>,
    /// Pattern to match in IR
    pub match_pattern: Vec<String>,
    /// Replacement sequence (target-independent pseudocode)
    pub replacement: Vec<ReplacementStep>,
    /// Priority (higher = applied first)
    pub priority: u32,
    /// Whether this is an optimization
    pub is_optimization: bool,
}

/// Embedded target architecture identifier for lowering rules.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum EmbeddedTarget {
    MSP430,
    MSP430X,
    AVR,
    ARC,
    X86,
    X86_64,
    All,
}

/// A single step in a lowering replacement sequence.
#[derive(Debug, Clone)]
pub struct ReplacementStep {
    /// Operation name
    pub operation: String,
    /// Input operands (by index into match pattern)
    pub inputs: Vec<usize>,
    /// Output name
    pub output: String,
    /// Additional metadata
    pub metadata: HashMap<String, String>,
}

impl CrossTargetLowering {
    /// Create a new lowering rules collection.
    pub fn new() -> Self {
        Self {
            rules: Vec::new(),
            rule_index: HashMap::new(),
        }
    }

    /// Load all predefined lowering rules.
    pub fn load_rules(&mut self) {
        // Rule: combine MOV+MOV into SWPB for byte swap pattern
        self.add_rule(LoweringRule {
            name: "combine_mov_mov_to_swpb".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["shl".into(), "shr".into(), "or".into()],
            replacement: vec![ReplacementStep {
                operation: "swpb".into(),
                inputs: vec![0],
                output: "result".into(),
                metadata: HashMap::new(),
            }],
            priority: 90,
            is_optimization: true,
        });

        // Rule: lower 16-bit multiply to shift-add sequence on MSP430
        self.add_rule(LoweringRule {
            name: "lower_16bit_mul_to_shift_add".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["mul".into(), "a".into(), "b".into()],
            replacement: vec![ReplacementStep {
                operation: "msp430_mul_expand".into(),
                inputs: vec![1, 2],
                output: "result".into(),
                metadata: HashMap::new(),
            }],
            priority: 80,
            is_optimization: false,
        });

        // Rule: lower memcpy to MOV loop for MSP430
        self.add_rule(LoweringRule {
            name: "lower_memcpy_to_mov_loop".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["memcpy".into(), "dest".into(), "src".into(), "size".into()],
            replacement: vec![ReplacementStep {
                operation: "memcpy_expand_msp430".into(),
                inputs: vec![1, 2, 3],
                output: "".into(),
                metadata: HashMap::new(),
            }],
            priority: 70,
            is_optimization: false,
        });

        // Rule: lower memset to MOV loop for MSP430
        self.add_rule(LoweringRule {
            name: "lower_memset_to_mov_loop".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec![
                "memset".into(),
                "dest".into(),
                "value".into(),
                "size".into(),
            ],
            replacement: vec![ReplacementStep {
                operation: "memset_expand_msp430".into(),
                inputs: vec![1, 2, 3],
                output: "".into(),
                metadata: HashMap::new(),
            }],
            priority: 70,
            is_optimization: false,
        });

        // Rule: use constant generator for common constants (0, 1, 2, 4, 8, -1)
        self.add_rule(LoweringRule {
            name: "use_constant_generator".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["mov".into(), "const".into()],
            replacement: vec![ReplacementStep {
                operation: "mov_cg".into(),
                inputs: vec![1],
                output: "result".into(),
                metadata: {
                    let mut m = HashMap::new();
                    m.insert("cg_values".into(), "0,1,2,4,8,-1".into());
                    m
                },
            }],
            priority: 95,
            is_optimization: true,
        });

        // Rule: combine CMP+Jcc into single Jcc pattern
        self.add_rule(LoweringRule {
            name: "combine_cmp_jcc".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["cmp".into(), "jmp".into()],
            replacement: vec![ReplacementStep {
                operation: "jcc".into(),
                inputs: vec![0, 1],
                output: "".into(),
                metadata: HashMap::new(),
            }],
            priority: 85,
            is_optimization: true,
        });

        // Rule: combine BIT+JZ into single pattern
        self.add_rule(LoweringRule {
            name: "combine_bit_jz".into(),
            targets: vec![EmbeddedTarget::MSP430, EmbeddedTarget::MSP430X],
            match_pattern: vec!["bit".into(), "jz".into()],
            replacement: vec![ReplacementStep {
                operation: "bit_branch".into(),
                inputs: vec![0, 1],
                output: "".into(),
                metadata: HashMap::new(),
            }],
            priority: 85,
            is_optimization: true,
        });

        // Rule: eliminate redundant PUSH/POP pairs
        self.add_rule(LoweringRule {
            name: "eliminate_push_pop_pair".into(),
            targets: vec![
                EmbeddedTarget::MSP430,
                EmbeddedTarget::MSP430X,
                EmbeddedTarget::X86,
                EmbeddedTarget::X86_64,
            ],
            match_pattern: vec!["push".into(), "pop".into()],
            replacement: vec![ReplacementStep {
                operation: "mov".into(),
                inputs: vec![0],
                output: "eliminated".into(),
                metadata: HashMap::new(),
            }],
            priority: 90,
            is_optimization: true,
        });

        // Rule: use PUSHM/POPM for multiple register save/restore (MSP430X)
        self.add_rule(LoweringRule {
            name: "use_pushm_popm".into(),
            targets: vec![EmbeddedTarget::MSP430X],
            match_pattern: vec!["push".into(), "push".into(), "push".into()],
            replacement: vec![ReplacementStep {
                operation: "pushm".into(),
                inputs: vec![0, 1, 2],
                output: "".into(),
                metadata: HashMap::new(),
            }],
            priority: 92,
            is_optimization: true,
        });
    }

    fn add_rule(&mut self, rule: LoweringRule) {
        let name = rule.name.clone();
        let idx = self.rules.len();
        self.rule_index.insert(name, idx);
        self.rules.push(rule);
    }

    /// Apply lowering rules to an IR sequence.
    pub fn apply(&self, ir_sequence: &[&str]) -> Vec<CrossTargetOptResult> {
        let mut results = Vec::new();
        for rule in &self.rules {
            if let Some(repl) = self.try_match_rule(rule, ir_sequence) {
                results.push(CrossTargetOptResult {
                    rule_name: rule.name.clone(),
                    matched: true,
                    replacement: Some(repl),
                    targets: rule.targets.clone(),
                    is_optimization: rule.is_optimization,
                });
            }
        }
        results
    }

    fn try_match_rule(&self, rule: &LoweringRule, ir_sequence: &[&str]) -> Option<String> {
        if rule.match_pattern.len() > ir_sequence.len() {
            return None;
        }
        for i in 0..=ir_sequence.len() - rule.match_pattern.len() {
            let mut matched = true;
            for (j, pat) in rule.match_pattern.iter().enumerate() {
                if pat != "const" && ir_sequence[i + j] != pat.as_str() {
                    matched = false;
                    break;
                }
            }
            if matched {
                let desc = rule
                    .replacement
                    .iter()
                    .map(|s| s.operation.clone())
                    .collect::<Vec<_>>()
                    .join(", ");
                return Some(desc);
            }
        }
        None
    }

    /// Get a rule by name.
    pub fn get_rule(&self, name: &str) -> Option<&LoweringRule> {
        self.rule_index.get(name).map(|&idx| &self.rules[idx])
    }

    /// List all rule names.
    pub fn list_rules(&self) -> Vec<&String> {
        self.rules.iter().map(|r| &r.name).collect()
    }

    /// Count the number of loaded rules.
    pub fn rule_count(&self) -> usize {
        self.rules.len()
    }
}

impl Default for CrossTargetLowering {
    fn default() -> Self {
        let mut rules = Self::new();
        rules.load_rules();
        rules
    }
}

/// Result of applying cross-target optimization rules.
#[derive(Debug, Clone)]
pub struct CrossTargetOptResult {
    /// Name of the rule
    pub rule_name: String,
    /// Whether the rule matched
    pub matched: bool,
    /// Replacement description (if matched)
    pub replacement: Option<String>,
    /// Target architectures this applies to
    pub targets: Vec<EmbeddedTarget>,
    /// Whether this was an optimization
    pub is_optimization: bool,
}

// ============================================================================
// §2.3: Shared Register Allocation Framework
// ============================================================================

/// Shared register allocation context that works across targets.
pub struct SharedRegisterAllocContext {
    /// MSP430 register classes and their properties
    pub msp430_classes: Vec<SharedRegClass>,
    /// X86 register classes and their properties
    pub x86_classes: Vec<SharedRegClass>,
    /// Mapping from virtual to physical registers
    pub virt_to_phys: HashMap<u32, u32>,
    /// Register pressure tracking
    pub reg_pressure: HashMap<u32, u32>,
    /// Live intervals
    pub live_intervals: Vec<LiveInterval>,
    /// Allocation strategy
    pub strategy: AllocationStrategy,
    /// Spill slots assigned
    pub spill_slots: HashMap<u32, SpillSlotInfo>,
    /// Allocated register set
    pub allocated: BTreeSet<u32>,
}

/// A shared register class definition.
#[derive(Debug, Clone)]
pub struct SharedRegClass {
    /// Class ID
    pub id: u32,
    /// Human-readable name
    pub name: String,
    /// Register IDs in this class
    pub registers: Vec<u32>,
    /// Alignment requirement
    pub alignment: u32,
    /// Size in bits
    pub size_bits: u32,
    /// Whether this class contains allocatable registers
    pub is_allocatable: bool,
    /// Copy cost between registers in this class
    pub copy_cost: u32,
}

/// A live interval for register allocation.
#[derive(Debug, Clone)]
pub struct LiveInterval {
    /// Virtual register ID
    pub vreg: u32,
    /// Start instruction index
    pub start: usize,
    /// End instruction index
    pub end: usize,
    /// Register class
    pub reg_class: u32,
    /// Spill weight (cost of spilling)
    pub spill_weight: f64,
}

/// Information about a spill slot.
#[derive(Debug, Clone)]
pub struct SpillSlotInfo {
    /// Slot index
    pub slot: u32,
    /// Offset from frame pointer
    pub offset: i32,
    /// Size in bytes
    pub size: u32,
    /// Alignment
    pub alignment: u32,
}

/// Register allocation strategy.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum AllocationStrategy {
    /// Linear scan
    LinearScan,
    /// Greedy with backtracking
    Greedy,
    /// Fast (simple, for -O0)
    Fast,
}

impl AllocationStrategy {
    pub fn as_str(&self) -> &str {
        match self {
            Self::LinearScan => "linear-scan",
            Self::Greedy => "greedy",
            Self::Fast => "fast",
        }
    }
}

impl SharedRegisterAllocContext {
    /// Create a new empty RA context.
    pub fn new() -> Self {
        Self {
            msp430_classes: Vec::new(),
            x86_classes: Vec::new(),
            virt_to_phys: HashMap::new(),
            reg_pressure: HashMap::new(),
            live_intervals: Vec::new(),
            strategy: AllocationStrategy::Greedy,
            spill_slots: HashMap::new(),
            allocated: BTreeSet::new(),
        }
    }

    /// Initialize with default register classes for both targets.
    pub fn initialize(&mut self) {
        // MSP430 GPR16 class (16 registers: R0/PC, R1/SP, R2/SR, R3/CG, R4-R15)
        // Registers R4-R12 are allocatable general-purpose
        self.msp430_classes.push(SharedRegClass {
            id: 0,
            name: "GPR16".into(),
            registers: vec![8004, 8005, 8006, 8007, 8008, 8009, 8010, 8011, 8012],
            alignment: 2,
            size_bits: 16,
            is_allocatable: true,
            copy_cost: 1,
        });
        // MSP430 reserved registers (PC, SP, SR, CG)
        self.msp430_classes.push(SharedRegClass {
            id: 1,
            name: "Special".into(),
            registers: vec![8000, 8001, 8002, 8003],
            alignment: 2,
            size_bits: 16,
            is_allocatable: false,
            copy_cost: 0,
        });
        // Call-saved registers (R4-R10 callee-saved per MSP430 ABI)
        self.msp430_classes.push(SharedRegClass {
            id: 2,
            name: "CalleeSaved".into(),
            registers: vec![8004, 8005, 8006, 8007, 8008, 8009, 8010],
            alignment: 2,
            size_bits: 16,
            is_allocatable: true,
            copy_cost: 1,
        });
        // Caller-saved registers (R11-R15)
        self.msp430_classes.push(SharedRegClass {
            id: 3,
            name: "CallerSaved".into(),
            registers: vec![8011, 8012, 8013, 8014, 8015],
            alignment: 2,
            size_bits: 16,
            is_allocatable: true,
            copy_cost: 1,
        });

        // X86 GPR32 class (8 registers in 32-bit mode)
        self.x86_classes.push(SharedRegClass {
            id: 0,
            name: "GPR32".into(),
            registers: (0..8).collect(),
            alignment: 4,
            size_bits: 32,
            is_allocatable: true,
            copy_cost: 1,
        });
        // X86 GPR64 class (16 registers in 64-bit mode)
        self.x86_classes.push(SharedRegClass {
            id: 1,
            name: "GPR64".into(),
            registers: (0..16).collect(),
            alignment: 8,
            size_bits: 64,
            is_allocatable: true,
            copy_cost: 1,
        });
    }

    /// Compute spill weight for a live interval.
    pub fn compute_spill_weight(&self, interval: &LiveInterval) -> f64 {
        let length = (interval.end - interval.start) as f64;
        if length <= 0.0 {
            return 0.0;
        }
        length.ln() * 2.0
    }

    /// Check if a register is available.
    pub fn is_register_available(&self, reg: u32) -> bool {
        !self.allocated.contains(&reg)
    }

    /// Mark a register as allocated.
    pub fn allocate_register(&mut self, vreg: u32, phys: u32) {
        self.virt_to_phys.insert(vreg, phys);
        self.allocated.insert(phys);
    }

    /// Free a register.
    pub fn free_register(&mut self, phys: u32) {
        self.allocated.remove(&phys);
        self.virt_to_phys.retain(|_, v| *v != phys);
    }

    /// Add a spill slot.
    pub fn add_spill_slot(&mut self, vreg: u32, size: u32, alignment: u32) -> u32 {
        let slot = self.spill_slots.len() as u32;
        self.spill_slots.insert(
            vreg,
            SpillSlotInfo {
                slot,
                offset: -(slot as i32 + 1) * 2,
                size,
                alignment,
            },
        );
        slot
    }

    /// Get the physical register assigned to a virtual register.
    pub fn get_physical_reg(&self, vreg: u32) -> Option<u32> {
        self.virt_to_phys.get(&vreg).copied()
    }

    /// Check if a virtual register has been spilled.
    pub fn is_spilled(&self, vreg: u32) -> bool {
        self.spill_slots.contains_key(&vreg)
    }

    /// Get the spill slot for a virtual register.
    pub fn get_spill_slot(&self, vreg: u32) -> Option<&SpillSlotInfo> {
        self.spill_slots.get(&vreg)
    }

    /// Build MSP430 calling convention register constraints.
    pub fn build_msp430_cc_constraints(&self) -> Vec<RegisterConstraint> {
        vec![
            RegisterConstraint {
                reg: 8000,
                constraint_type: ConstraintType::Reserved,
                reason: "Program Counter (PC)".into(),
            },
            RegisterConstraint {
                reg: 8001,
                constraint_type: ConstraintType::FixedAssignment,
                reason: "Stack Pointer (SP)".into(),
            },
            RegisterConstraint {
                reg: 8002,
                constraint_type: ConstraintType::Reserved,
                reason: "Status Register (SR)".into(),
            },
            RegisterConstraint {
                reg: 8003,
                constraint_type: ConstraintType::Reserved,
                reason: "Constant Generator (CG2)".into(),
            },
            RegisterConstraint {
                reg: 8012,
                constraint_type: ConstraintType::FixedAssignment,
                reason: "Return value (R12)".into(),
            },
            RegisterConstraint {
                reg: 8013,
                constraint_type: ConstraintType::FixedAssignment,
                reason: "Second return value (R13)".into(),
            },
            RegisterConstraint {
                reg: 8014,
                constraint_type: ConstraintType::FixedAssignment,
                reason: "Frame pointer / Link register (R14)".into(),
            },
            RegisterConstraint {
                reg: 8015,
                constraint_type: ConstraintType::FixedAssignment,
                reason: "Return address / Call register (R15)".into(),
            },
        ]
    }
}

impl Default for SharedRegisterAllocContext {
    fn default() -> Self {
        let mut ctx = Self::new();
        ctx.initialize();
        ctx
    }
}

/// Cross-target register allocation framework.
#[derive(Debug)]
pub struct CrossTargetRegisterAlloc {
    /// The shared context
    pub context: SharedRegisterAllocContext,
    /// MSP430-specific register constraints
    pub msp430_constraints: Vec<RegisterConstraint>,
    /// X86-specific register constraints
    pub x86_constraints: Vec<RegisterConstraint>,
    /// Register alias information
    pub aliases: Vec<RegisterAlias>,
}

/// A register constraint (e.g., "must use R12 for return value").
#[derive(Debug, Clone)]
pub struct RegisterConstraint {
    /// Register ID
    pub reg: u32,
    /// Constraint type
    pub constraint_type: ConstraintType,
    /// Reason for the constraint
    pub reason: String,
}

/// Types of register constraints.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ConstraintType {
    /// Register is reserved
    Reserved,
    /// Register must be used for specific purpose
    FixedAssignment,
    /// Register is caller-saved
    CallerSaved,
    /// Register is callee-saved
    CalleeSaved,
    /// Register has alignment constraint
    AlignmentRequired,
}

/// Register alias information.
#[derive(Debug, Clone)]
pub struct RegisterAlias {
    /// Primary register
    pub primary: u32,
    /// Alias register (sub/super register)
    pub alias: u32,
    /// Relationship
    pub relation: AliasRelation,
}

/// Register alias relationship.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum AliasRelation {
    /// Alias is a sub-register (e.g., AL is sub-register of AX)
    SubRegister,
    /// Alias is a super-register
    SuperRegister,
    /// Alias is a different view of the same register
    Equivalent,
}

impl CrossTargetRegisterAlloc {
    /// Create a new cross-target RA framework.
    pub fn new() -> Self {
        Self {
            context: SharedRegisterAllocContext::new(),
            msp430_constraints: Vec::new(),
            x86_constraints: Vec::new(),
            aliases: Vec::new(),
        }
    }
}

impl Default for CrossTargetRegisterAlloc {
    fn default() -> Self {
        let mut ra = Self::new();
        ra.context.initialize();
        ra
    }
}

// ============================================================================
// §2.4: Shared Frame Lowering Abstractions
// ============================================================================

/// Cross-target frame lowering abstractions.
#[derive(Debug)]
pub struct CrossTargetFrameLowering {
    /// Stack alignment
    pub stack_alignment: u32,
    /// Red zone size
    pub red_zone_size: u32,
    /// Maximum call frame size
    pub max_call_frame_size: u32,
    /// Whether to use frame pointer
    pub use_frame_pointer: bool,
    /// Whether local area is at fixed offset
    pub local_area_offset_fixed: bool,
}

impl CrossTargetFrameLowering {
    /// Create new cross-target frame lowering.
    pub fn new() -> Self {
        Self {
            stack_alignment: 2,
            red_zone_size: 0,
            max_call_frame_size: 0,
            use_frame_pointer: true,
            local_area_offset_fixed: false,
        }
    }
}

impl Default for CrossTargetFrameLowering {
    fn default() -> Self {
        Self::new()
    }
}

/// Shared frame lowering context.
#[derive(Debug, Clone)]
pub struct SharedFrameLoweringContext {
    /// Stack frame size
    pub frame_size: u32,
    /// Saved registers offset from SP
    pub saved_regs_offset: i32,
    /// Local area offset from FP
    pub local_area_offset: i32,
    /// Callee-saved register slots
    pub callee_saved_slots: Vec<(u32, i32)>,
    /// Whether frame pointer is used
    pub has_frame_pointer: bool,
    /// Whether the function has calls
    pub has_calls: bool,
    /// Stack alignment
    pub stack_alignment: u32,
    /// Is MSP430X (20-bit) target
    pub is_msp430x: bool,
}

impl SharedFrameLoweringContext {
    /// Create a new empty frame lowering context.
    pub fn new() -> Self {
        Self {
            frame_size: 0,
            saved_regs_offset: 0,
            local_area_offset: 0,
            callee_saved_slots: Vec::new(),
            has_frame_pointer: false,
            has_calls: false,
            stack_alignment: 2,
            is_msp430x: false,
        }
    }

    /// Initialize with defaults.
    pub fn initialize(&mut self) {
        self.frame_size = 0;
        self.saved_regs_offset = 0;
        self.local_area_offset = 0;
        self.callee_saved_slots.clear();
        self.has_frame_pointer = false;
        self.has_calls = false;
    }

    /// Register a callee-saved register with its spill slot offset.
    pub fn add_callee_saved_slot(&mut self, reg: u32, offset: i32) {
        self.callee_saved_slots.push((reg, offset));
    }

    /// Get offset for a callee-saved register.
    pub fn get_callee_saved_offset(&self, reg: u32) -> Option<i32> {
        self.callee_saved_slots
            .iter()
            .find(|(r, _)| *r == reg)
            .map(|(_, o)| *o)
    }

    /// Compute typical MSP430 prologue size (in instructions).
    pub fn compute_prologue_size(&self) -> u32 {
        let mut size = 0u32;
        // PUSH R14 (frame pointer) if used
        if self.has_frame_pointer {
            size += 1;
            // MOV SP, R14
            size += 1;
        }
        // SUB #frame_size, SP
        if self.frame_size > 0 {
            size += 1;
        }
        // Callee-saved pushes
        size += self.callee_saved_slots.len() as u32;
        size
    }

    /// Sort callee-saved slots by offset.
    pub fn sort_callee_saved_slots(&mut self) {
        self.callee_saved_slots.sort_by_key(|(_, o)| *o);
    }
}

impl Default for SharedFrameLoweringContext {
    fn default() -> Self {
        let mut ctx = Self::new();
        ctx.initialize();
        ctx
    }
}

// ============================================================================
// §2.5: Cross-Target Constant Materialization
// ============================================================================

/// Cross-target constant materialization helper.
pub struct CrossTargetConstMaterializer {
    /// Whether target is MSP430X (20-bit)
    pub is_msp430x: bool,
    /// Maximum 16-bit signed immediate
    pub max_immediate: i32,
}

impl CrossTargetConstMaterializer {
    /// Create a new constant materializer.
    pub fn new() -> Self {
        Self {
            is_msp430x: false,
            max_immediate: 65535,
        }
    }

    /// Materialize a constant on MSP430, returning the sequence of opcodes needed.
    pub fn materialize_msp430(&self, value: i32) -> Vec<Msp430Opcode> {
        match value {
            0 => vec![Msp430Opcode::CLR],
            1 => vec![Msp430Opcode::MOV], // MOV #1; can use CG1 for 2,4,8 or CG2 for 4
            2 => vec![Msp430Opcode::MOV],
            4 => vec![Msp430Opcode::MOV],
            8 => vec![Msp430Opcode::MOV],
            -1 => vec![Msp430Opcode::MOV],
            _ if value >= 0 && value <= 65535 => vec![Msp430Opcode::MOV],
            _ if self.is_msp430x && value >= 0 && value <= 0xFFFFF => {
                vec![Msp430Opcode::MOVA]
            }
            _ => vec![Msp430Opcode::MOV, Msp430Opcode::MOV],
        }
    }

    /// Materialize a constant on X86, returning number of instructions needed.
    pub fn materialize_x86_cost(&self, value: i32) -> u32 {
        if value == 0 {
            return 1; // XOR reg, reg
        }
        1 // MOV reg, imm32
    }
}

impl Default for CrossTargetConstMaterializer {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// §2.6: Cross-Target Branch Analysis
// ============================================================================

/// Cross-target branch analysis for comparing branch behavior.
pub struct CrossTargetBranchAnalyzer {
    /// Collected branch statistics
    pub branch_stats: BranchStats,
    /// Branch prediction hints
    pub hints: Vec<BranchHint>,
}

/// Branch statistics for cross-target comparison.
#[derive(Debug, Default, Clone)]
pub struct BranchStats {
    /// Total number of branches
    pub total_branches: u64,
    /// Number of conditional branches
    pub conditional_branches: u64,
    /// Number of unconditional branches
    pub unconditional_branches: u64,
    /// Number of backward branches (likely loops)
    pub backward_branches: u64,
    /// Number of forward branches
    pub forward_branches: u64,
    /// Average branch distance
    pub avg_branch_distance: f64,
    /// Number of indirect branches
    pub indirect_branches: u64,
}

/// A branch prediction hint for an instruction.
#[derive(Debug, Clone)]
pub struct BranchHint {
    /// Instruction index
    pub instr_idx: usize,
    /// Likely outcome: true = taken, false = not taken
    pub likely_taken: bool,
    /// Confidence (0.0 to 1.0)
    pub confidence: f64,
}

impl CrossTargetBranchAnalyzer {
    /// Create a new branch analyzer.
    pub fn new() -> Self {
        Self {
            branch_stats: BranchStats::default(),
            hints: Vec::new(),
        }
    }

    /// Analyze branch behavior of an instruction sequence.
    pub fn analyze(&mut self, instrs: &[&str]) {
        self.branch_stats.total_branches = 0;
        self.branch_stats.conditional_branches = 0;
        self.branch_stats.unconditional_branches = 0;
        self.branch_stats.backward_branches = 0;
        self.branch_stats.forward_branches = 0;
        self.branch_stats.indirect_branches = 0;

        for instr in instrs.iter() {
            let lower = instr.to_lowercase();
            if lower.starts_with('j') || lower.starts_with('b') || lower.contains("call") {
                self.branch_stats.total_branches += 1;
                if lower == "jmp" || lower == "br" || lower == "bra" {
                    self.branch_stats.unconditional_branches += 1;
                } else if lower.contains("call") {
                    self.branch_stats.unconditional_branches += 1;
                } else {
                    self.branch_stats.conditional_branches += 1;
                }
            }
        }
    }

    /// Compare branch behavior between MSP430 and X86 code.
    pub fn compare(&self, msp430_branches: u64, x86_branches: u64) -> BranchComparison {
        let ratio = if x86_branches > 0 {
            msp430_branches as f64 / x86_branches as f64
        } else {
            f64::INFINITY
        };
        BranchComparison {
            msp430_branch_count: msp430_branches,
            x86_branch_count: x86_branches,
            ratio,
            assessment: if ratio < 0.9 {
                "MSP430 uses fewer branches".into()
            } else if ratio > 1.1 {
                "X86 uses fewer branches".into()
            } else {
                "Similar branch counts".into()
            },
        }
    }
}

/// Result of comparing branch behavior between architectures.
#[derive(Debug, Clone)]
pub struct BranchComparison {
    /// Branch count on MSP430
    pub msp430_branch_count: u64,
    /// Branch count on X86
    pub x86_branch_count: u64,
    /// Ratio (msp430 / x86)
    pub ratio: f64,
    /// Human-readable assessment
    pub assessment: String,
}

impl Default for CrossTargetBranchAnalyzer {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// §3: MSP430FeatureSet — Target Feature Configuration
// ============================================================================

/// Set of target features for MSP430 cross-target optimization.
#[derive(Debug, Clone, Default)]
pub struct MSP430FeatureSet {
    /// Features enabled
    pub enabled: HashSet<String>,
    /// Features disabled
    pub disabled: HashSet<String>,
}

impl MSP430FeatureSet {
    /// Create a new empty feature set.
    pub fn new() -> Self {
        Self {
            enabled: HashSet::new(),
            disabled: HashSet::new(),
        }
    }

    /// Enable a feature.
    pub fn enable(&mut self, feature: &str) {
        self.disabled.remove(feature);
        self.enabled.insert(feature.to_string());
    }

    /// Disable a feature.
    pub fn disable(&mut self, feature: &str) {
        self.enabled.remove(feature);
        self.disabled.insert(feature.to_string());
    }

    /// Check if a feature is enabled.
    pub fn has(&self, feature: &str) -> bool {
        self.enabled.contains(feature)
    }

    /// Check if a feature is explicitly disabled.
    pub fn is_disabled(&self, feature: &str) -> bool {
        self.disabled.contains(feature)
    }

    /// Create a default MSP430 feature set.
    pub fn msp430_default() -> Self {
        let mut fs = Self::new();
        fs.enable("16bit");
        fs
    }

    /// Create a default MSP430X feature set.
    pub fn msp430x_default() -> Self {
        let mut fs = Self::new();
        fs.enable("16bit");
        fs.enable("20bit");
        fs.enable("msp430x");
        fs.enable("mova");
        fs.enable("pushm");
        fs.enable("popm");
        fs
    }
}

// ============================================================================
// §4: MSP430 Target Machine Configuration
// ============================================================================

/// MSP430 target machine configuration for the bridge.
#[derive(Debug, Clone)]
pub struct BridgeMSP430TargetMachine {
    /// Target triple string (e.g., "msp430-unknown-elf")
    pub triple: String,
    /// CPU name (e.g., "msp430", "msp430x")
    pub cpu: String,
    /// Feature flags string
    pub features: String,
    /// Whether this is an MSP430X (20-bit) target
    pub is_msp430x: bool,
    /// Data layout string
    pub data_layout: String,
    /// Stack alignment
    pub stack_alignment: u32,
    /// Pointer size in bytes
    pub pointer_size: u32,
    /// Feature set
    pub feature_set: MSP430FeatureSet,
}

/// Default data layout for MSP430.
pub const MSP430_DATA_LAYOUT: &str = "e-m:e-p:16:16-i32:16:32-a:0:16-n16";

/// Default data layout for MSP430X (20-bit pointers).
pub const MSP430X_DATA_LAYOUT: &str = "e-m:e-p:20:16-i32:16:32-a:0:16-n16";

impl BridgeMSP430TargetMachine {
    /// Create a new MSP430 target machine.
    pub fn new(triple: &str) -> Self {
        let lower = triple.to_lowercase();
        let is_msp430x = lower.contains("msp430x") || lower.contains("430x");

        let data_layout = if is_msp430x {
            MSP430X_DATA_LAYOUT.to_string()
        } else {
            MSP430_DATA_LAYOUT.to_string()
        };

        let feature_set = if is_msp430x {
            MSP430FeatureSet::msp430x_default()
        } else {
            MSP430FeatureSet::msp430_default()
        };

        Self {
            triple: triple.to_string(),
            cpu: if is_msp430x {
                "msp430x".to_string()
            } else {
                "msp430".to_string()
            },
            features: if is_msp430x {
                "+msp430x,+mova,+20bit".to_string()
            } else {
                "+16bit".to_string()
            },
            is_msp430x,
            data_layout,
            stack_alignment: 2,
            pointer_size: if is_msp430x { 4 } else { 2 },
            feature_set,
        }
    }

    /// Create for MSP430 only.
    pub fn new_msp430() -> Self {
        Self::new("msp430-unknown-elf")
    }

    /// Create for MSP430X.
    pub fn new_msp430x() -> Self {
        Self::new("msp430x-unknown-elf")
    }

    /// Get the target triple.
    pub fn get_triple(&self) -> &str {
        &self.triple
    }

    /// Get the data layout.
    pub fn get_data_layout(&self) -> &str {
        &self.data_layout
    }

    /// Check if target is MSP430X.
    pub fn is_msp430x(&self) -> bool {
        self.is_msp430x
    }

    /// Describe the target machine configuration.
    pub fn describe(&self) -> String {
        format!(
            "MSP430 Target Machine:\n  Triple: {}\n  CPU: {}\n  Features: {}\n  MSP430X: {}\n  Data Layout: {}\n  Stack Alignment: {}\n  Pointer Size: {}",
            self.triple,
            self.cpu,
            self.features,
            self.is_msp430x,
            self.data_layout,
            self.stack_alignment,
            self.pointer_size,
        )
    }

    /// Get target machine name.
    pub fn get_target_name(&self) -> &str {
        if self.is_msp430x {
            "msp430x"
        } else {
            "msp430"
        }
    }
}

// ============================================================================
// §5: MSP430 Register Bridge Enumeration
// ============================================================================

/// Complete MSP430 register enumeration for bridge usage.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum Msp430BridgeReg {
    PC,
    SP,
    SR,
    CG2,
    R4,
    R5,
    R6,
    R7,
    R8,
    R9,
    R10,
    R11,
    R12,
    R13,
    R14,
    R15,
}

impl Msp430BridgeReg {
    /// Get register ID.
    pub fn id(&self) -> u16 {
        match self {
            Self::PC => MSP430_GPR_BASE,
            Self::SP => MSP430_GPR_BASE + 1,
            Self::SR => MSP430_GPR_BASE + 2,
            Self::CG2 => MSP430_GPR_BASE + 3,
            Self::R4 => MSP430_GPR_BASE + 4,
            Self::R5 => MSP430_GPR_BASE + 5,
            Self::R6 => MSP430_GPR_BASE + 6,
            Self::R7 => MSP430_GPR_BASE + 7,
            Self::R8 => MSP430_GPR_BASE + 8,
            Self::R9 => MSP430_GPR_BASE + 9,
            Self::R10 => MSP430_GPR_BASE + 10,
            Self::R11 => MSP430_GPR_BASE + 11,
            Self::R12 => MSP430_GPR_BASE + 12,
            Self::R13 => MSP430_GPR_BASE + 13,
            Self::R14 => MSP430_GPR_BASE + 14,
            Self::R15 => MSP430_GPR_BASE + 15,
        }
    }

    /// Get ABI name.
    pub fn abi_name(&self) -> &str {
        match self {
            Self::PC => "pc",
            Self::SP => "sp",
            Self::SR => "sr",
            Self::CG2 => "cg2",
            Self::R4 => "r4",
            Self::R5 => "r5",
            Self::R6 => "r6",
            Self::R7 => "r7",
            Self::R8 => "r8",
            Self::R9 => "r9",
            Self::R10 => "r10",
            Self::R11 => "r11",
            Self::R12 => "r12",
            Self::R13 => "r13",
            Self::R14 => "r14",
            Self::R15 => "r15",
        }
    }

    /// Check if register is special-purpose.
    pub fn is_special(&self) -> bool {
        matches!(self, Self::PC | Self::SP | Self::SR | Self::CG2)
    }

    /// Check if register is callee-saved.
    pub fn is_callee_saved(&self) -> bool {
        matches!(
            self,
            Self::R4 | Self::R5 | Self::R6 | Self::R7 | Self::R8 | Self::R9 | Self::R10
        )
    }

    /// Check if register is caller-saved (argument/scratch).
    pub fn is_caller_saved(&self) -> bool {
        matches!(
            self,
            Self::R11 | Self::R12 | Self::R13 | Self::R14 | Self::R15
        )
    }

    /// List all allocatable general-purpose registers.
    pub fn allocatable_regs() -> Vec<Msp430BridgeReg> {
        vec![
            Self::R4,
            Self::R5,
            Self::R6,
            Self::R7,
            Self::R8,
            Self::R9,
            Self::R10,
            Self::R11,
            Self::R12,
            Self::R13,
            Self::R14,
            Self::R15,
        ]
    }

    /// From register ID.
    pub fn from_id(id: u16) -> Option<Self> {
        match id {
            8000 => Some(Self::PC),
            8001 => Some(Self::SP),
            8002 => Some(Self::SR),
            8003 => Some(Self::CG2),
            8004 => Some(Self::R4),
            8005 => Some(Self::R5),
            8006 => Some(Self::R6),
            8007 => Some(Self::R7),
            8008 => Some(Self::R8),
            8009 => Some(Self::R9),
            8010 => Some(Self::R10),
            8011 => Some(Self::R11),
            8012 => Some(Self::R12),
            8013 => Some(Self::R13),
            8014 => Some(Self::R14),
            8015 => Some(Self::R15),
            _ => None,
        }
    }
}

// ============================================================================
// §6: MSP430InstrInfo — Bridge-level Instruction Info
// ============================================================================

/// Bridge-level abstraction over `Msp430InstrInfo`.
///
/// Provides cross-target query methods and instruction set metadata
/// organized by category for easier access from the bridge.
pub struct BridgeMSP430InstrInfo {
    /// Reference to the core MSP430 instruction info
    pub core: Msp430InstrInfo,
    /// Single-operand instructions
    pub single_operand_ops: Vec<Msp430Opcode>,
    /// Double-operand instructions
    pub double_operand_ops: Vec<Msp430Opcode>,
    /// Jump instructions
    pub jump_ops: Vec<Msp430Opcode>,
    /// Emulated instructions
    pub emulated_ops: Vec<Msp430Opcode>,
    /// MSP430X extended instructions
    pub msp430x_ops: Vec<Msp430Opcode>,
    /// Terminator instructions
    pub terminator_ops: Vec<Msp430Opcode>,
    /// Memory instructions
    pub memory_ops: Vec<Msp430Opcode>,
}

impl BridgeMSP430InstrInfo {
    /// Create a new bridge Msp430InstrInfo with categorized instruction sets.
    pub fn new() -> Self {
        let mut info = Self {
            core: Msp430InstrInfo::new(),
            single_operand_ops: Vec::new(),
            double_operand_ops: Vec::new(),
            jump_ops: Vec::new(),
            emulated_ops: Vec::new(),
            msp430x_ops: Vec::new(),
            terminator_ops: Vec::new(),
            memory_ops: Vec::new(),
        };
        info.categorize();
        info
    }

    fn categorize(&mut self) {
        // Single-operand instructions
        self.single_operand_ops = vec![
            Msp430Opcode::RRC,
            Msp430Opcode::SWPB,
            Msp430Opcode::RRA,
            Msp430Opcode::SXT,
            Msp430Opcode::PUSH,
            Msp430Opcode::POP,
            Msp430Opcode::CALL,
            Msp430Opcode::RETI,
        ];

        // Double-operand instructions
        self.double_operand_ops = vec![
            Msp430Opcode::MOV,
            Msp430Opcode::ADD,
            Msp430Opcode::ADDC,
            Msp430Opcode::SUBC,
            Msp430Opcode::SUB,
            Msp430Opcode::CMP,
            Msp430Opcode::DADD,
            Msp430Opcode::BIT,
            Msp430Opcode::BIC,
            Msp430Opcode::BIS,
            Msp430Opcode::XOR,
            Msp430Opcode::AND,
        ];

        // Jump instructions
        self.jump_ops = vec![
            Msp430Opcode::JNE,
            Msp430Opcode::JEQ,
            Msp430Opcode::JNC,
            Msp430Opcode::JC,
            Msp430Opcode::JN,
            Msp430Opcode::JGE,
            Msp430Opcode::JL,
            Msp430Opcode::JMP,
        ];

        // Emulated instructions
        self.emulated_ops = vec![
            Msp430Opcode::CLR,
            Msp430Opcode::CLRC,
            Msp430Opcode::SETC,
            Msp430Opcode::CLRZ,
            Msp430Opcode::SETZ,
            Msp430Opcode::CLRN,
            Msp430Opcode::SETN,
            Msp430Opcode::DINT,
            Msp430Opcode::EINT,
            Msp430Opcode::NOP,
            Msp430Opcode::BR,
            Msp430Opcode::RET,
            Msp430Opcode::TST,
            Msp430Opcode::INV,
            Msp430Opcode::RLA,
            Msp430Opcode::RLC,
            Msp430Opcode::ADC,
            Msp430Opcode::DADC,
        ];

        // MSP430X extended instructions
        self.msp430x_ops = vec![
            Msp430Opcode::MOVA,
            Msp430Opcode::CMPA,
            Msp430Opcode::ADDA,
            Msp430Opcode::SUBA,
            Msp430Opcode::BRA,
            Msp430Opcode::RETA,
            Msp430Opcode::PUSHM,
            Msp430Opcode::POPM,
            Msp430Opcode::CALLA,
        ];

        // Terminator instructions
        self.terminator_ops = vec![
            Msp430Opcode::JMP,
            Msp430Opcode::BR,
            Msp430Opcode::BRA,
            Msp430Opcode::CALL,
            Msp430Opcode::CALLA,
            Msp430Opcode::RET,
            Msp430Opcode::RETA,
            Msp430Opcode::RETI,
        ];

        // Memory instructions (push/pop/load/store)
        self.memory_ops = vec![
            Msp430Opcode::MOV,
            Msp430Opcode::PUSH,
            Msp430Opcode::POP,
            Msp430Opcode::PUSHM,
            Msp430Opcode::POPM,
        ];
    }

    /// Check if an opcode is from the MSP430X extended set.
    pub fn is_msp430x_opcode(&self, opcode: Msp430Opcode) -> bool {
        self.msp430x_ops.contains(&opcode)
    }

    /// Get the mnemonic for an opcode.
    pub fn get_mnemonic(&self, opcode: Msp430Opcode) -> String {
        self.core.get_mnemonic(opcode)
    }

    /// List all branch opcodes.
    pub fn get_branch_ops(&self) -> &[Msp430Opcode] {
        &self.jump_ops
    }

    /// Count total instructions by category.
    pub fn instruction_counts(&self) -> InstructionCounts {
        InstructionCounts {
            single_operand: self.single_operand_ops.len() as u32,
            double_operand: self.double_operand_ops.len() as u32,
            jumps: self.jump_ops.len() as u32,
            emulated: self.emulated_ops.len() as u32,
            msp430x: self.msp430x_ops.len() as u32,
        }
    }
}

/// Counts of MSP430 instructions by category.
#[derive(Debug, Clone)]
pub struct InstructionCounts {
    pub single_operand: u32,
    pub double_operand: u32,
    pub jumps: u32,
    pub emulated: u32,
    pub msp430x: u32,
}

// ============================================================================
// §7: MSP430 Calling Convention Bridge
// ============================================================================

/// MSP430 calling convention representation for the bridge.
#[derive(Debug, Clone)]
pub struct MSP430CallingConventionBridge {
    /// Argument registers (R12-R15, pushed right-to-left)
    pub arg_regs: Vec<u32>,
    /// Return value register (R12, R13 for 32-bit)
    pub ret_regs: Vec<u32>,
    /// Callee-saved registers
    pub callee_saved: Vec<u32>,
    /// Caller-saved registers (scratch)
    pub caller_saved: Vec<u32>,
    /// Stack alignment for calls
    pub stack_alignment: u32,
    /// Whether arguments are passed on stack beyond 4 registers
    pub use_stack_args: bool,
}

impl MSP430CallingConventionBridge {
    /// Create standard MSP430 calling convention.
    pub fn new() -> Self {
        Self {
            arg_regs: vec![
                MSP430_GPR_BASE as u32 + 15, // R15
                MSP430_GPR_BASE as u32 + 14, // R14
                MSP430_GPR_BASE as u32 + 13, // R13
                MSP430_GPR_BASE as u32 + 12, // R12
            ],
            ret_regs: vec![
                MSP430_GPR_BASE as u32 + 12, // R12
                MSP430_GPR_BASE as u32 + 13, // R13 (32-bit return)
            ],
            callee_saved: vec![
                MSP430_GPR_BASE as u32 + 4,  // R4
                MSP430_GPR_BASE as u32 + 5,  // R5
                MSP430_GPR_BASE as u32 + 6,  // R6
                MSP430_GPR_BASE as u32 + 7,  // R7
                MSP430_GPR_BASE as u32 + 8,  // R8
                MSP430_GPR_BASE as u32 + 9,  // R9
                MSP430_GPR_BASE as u32 + 10, // R10
            ],
            caller_saved: vec![
                MSP430_GPR_BASE as u32 + 11, // R11
                MSP430_GPR_BASE as u32 + 12, // R12
                MSP430_GPR_BASE as u32 + 13, // R13
                MSP430_GPR_BASE as u32 + 14, // R14
                MSP430_GPR_BASE as u32 + 15, // R15
            ],
            stack_alignment: 2,
            use_stack_args: true,
        }
    }

    /// Get the register to use for the nth argument.
    pub fn get_arg_register(&self, n: usize) -> Option<u32> {
        if n < self.arg_regs.len() {
            Some(self.arg_regs[self.arg_regs.len() - 1 - n])
        } else {
            None
        }
    }

    /// Get the return value register.
    pub fn get_return_register(&self) -> u32 {
        self.ret_regs[0]
    }

    /// Check if a register is callee-saved.
    pub fn is_callee_saved(&self, reg: u32) -> bool {
        self.callee_saved.contains(&reg)
    }

    /// Map to X86 calling convention comparison.
    pub fn compare_with_x86(&self) -> CCComparison {
        CCComparison {
            msp430_arg_regs: self.arg_regs.len() as u32,
            x86_arg_regs: 6, // System V AMD64 passes 6 args in registers
            msp430_ret_regs: self.ret_regs.len() as u32,
            x86_ret_regs: 2, // RAX + RDX
            msp430_callee_saved: self.callee_saved.len() as u32,
            x86_callee_saved: 5, // RBX, RBP, R12-R15
            msp430_caller_saved: self.caller_saved.len() as u32,
            x86_caller_saved: 9,
        }
    }
}

/// Comparison between MSP430 and X86 calling conventions.
#[derive(Debug, Clone)]
pub struct CCComparison {
    pub msp430_arg_regs: u32,
    pub x86_arg_regs: u32,
    pub msp430_ret_regs: u32,
    pub x86_ret_regs: u32,
    pub msp430_callee_saved: u32,
    pub x86_callee_saved: u32,
    pub msp430_caller_saved: u32,
    pub x86_caller_saved: u32,
}

// ============================================================================
// §8: X86→MSP430 Code Size Analysis
// ============================================================================

/// Code size analysis comparing MSP430 and X86 encoding density.
pub struct CodeSizeAnalyzer {
    /// Total MSP430 bytes
    pub msp430_bytes: u64,
    /// Total X86 bytes
    pub x86_bytes: u64,
    /// Per-instruction breakdowns
    pub msp430_instr_sizes: Vec<(Msp430Opcode, u32)>,
    pub x86_instr_sizes: Vec<(X86Opcode, u32)>,
}

impl CodeSizeAnalyzer {
    /// Create a new code size analyzer.
    pub fn new() -> Self {
        Self {
            msp430_bytes: 0,
            x86_bytes: 0,
            msp430_instr_sizes: Vec::new(),
            x86_instr_sizes: Vec::new(),
        }
    }

    /// Record MSP430 instruction sizes from a sequence.
    pub fn analyze_msp430(&mut self, opcodes: &[Msp430Opcode]) {
        for opcode in opcodes {
            let size = match opcode {
                // Single-operand: 2 bytes
                Msp430Opcode::RRC
                | Msp430Opcode::SWPB
                | Msp430Opcode::RRA
                | Msp430Opcode::SXT
                | Msp430Opcode::PUSH
                | Msp430Opcode::RETI => 2,
                // Branch/call: 2 bytes (PC-relative) or 4 (symbolic)
                Msp430Opcode::CALL | Msp430Opcode::JMP => 4,
                // Conditional jumps: 2 bytes (PC-relative offset)
                Msp430Opcode::JNE
                | Msp430Opcode::JEQ
                | Msp430Opcode::JNC
                | Msp430Opcode::JC
                | Msp430Opcode::JN
                | Msp430Opcode::JGE
                | Msp430Opcode::JL => 2,
                // Double-operand: 2 bytes (register) or 4 (immediate/indexed)
                _ => 4,
            };
            self.msp430_bytes += size as u64;
            self.msp430_instr_sizes.push((*opcode, size));
        }
    }

    /// Record X86 instruction sizes.
    pub fn analyze_x86(&mut self, opcodes: &[X86Opcode]) {
        for opcode in opcodes {
            let size = match opcode {
                X86Opcode::NOP => 1,
                X86Opcode::RET => 1,
                X86Opcode::PUSH | X86Opcode::POP => 1,
                X86Opcode::INC | X86Opcode::DEC => 1,
                X86Opcode::JMP => 2,
                X86Opcode::JE
                | X86Opcode::JNE
                | X86Opcode::JB
                | X86Opcode::JAE
                | X86Opcode::JL
                | X86Opcode::JGE => 2,
                X86Opcode::CALL => 5,
                _ => 3,
            };
            self.x86_bytes += size as u64;
            self.x86_instr_sizes.push((*opcode, size));
        }
    }

    /// Get compression ratio (MSP430 / X86).
    pub fn compression_ratio(&self) -> f64 {
        if self.x86_bytes > 0 {
            self.msp430_bytes as f64 / self.x86_bytes as f64
        } else {
            0.0
        }
    }

    /// Format a report string.
    pub fn report(&self) -> String {
        format!(
            "Code Size: MSP430={} bytes, X86={} bytes, Ratio={:.3} (MSP430/X86)",
            self.msp430_bytes,
            self.x86_bytes,
            self.compression_ratio()
        )
    }
}

impl Default for CodeSizeAnalyzer {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// §9: Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_bridge_creation() {
        let bridge = MSP430X86Bridge::new();
        assert_eq!(bridge.config.target_variant, "msp430");
        assert!(!bridge.config.verbose);
    }

    #[test]
    fn test_bridge_with_config() {
        let config = BridgeConfig {
            target_variant: "msp430x".into(),
            ..BridgeConfig::default()
        };
        let bridge = MSP430X86Bridge::with_config(config);
        assert_eq!(bridge.config.target_variant, "msp430x");
    }

    #[test]
    fn test_translate_x86_to_msp430_add() {
        let mut bridge = MSP430X86Bridge::new();
        let result = bridge.translate_x86_to_msp430(&X86Opcode::ADD);
        assert!(result.is_some());
        match result.unwrap() {
            BridgeInstruction::DirectMap(op) => assert_eq!(op, Msp430Opcode::ADD),
            _ => panic!("Expected DirectMap"),
        }
    }

    #[test]
    fn test_translate_x86_to_msp430_sub() {
        let mut bridge = MSP430X86Bridge::new();
        let result = bridge.translate_x86_to_msp430(&X86Opcode::SUB);
        assert!(result.is_some());
        match result.unwrap() {
            BridgeInstruction::DirectMap(op) => assert_eq!(op, Msp430Opcode::SUB),
            _ => panic!("Expected DirectMap"),
        }
    }

    #[test]
    fn test_translate_x86_to_msp430_mov() {
        let mut bridge = MSP430X86Bridge::new();
        let result = bridge.translate_x86_to_msp430(&X86Opcode::MOV);
        assert!(result.is_some());
        match result.unwrap() {
            BridgeInstruction::DirectMap(op) => assert_eq!(op, Msp430Opcode::MOV),
            _ => panic!("Expected DirectMap"),
        }
    }

    #[test]
    fn test_translate_msp430_to_x86_add() {
        let mut bridge = MSP430X86Bridge::new();
        let result = bridge.translate_msp430_to_x86(&Msp430Opcode::ADD);
        assert!(result.is_some());
        match result.unwrap() {
            BridgeInstruction::DirectMapX86(op) => assert_eq!(op, X86Opcode::ADD),
            _ => panic!("Expected DirectMapX86"),
        }
    }

    #[test]
    fn test_translate_msp430_to_x86_bis() {
        let mut bridge = MSP430X86Bridge::new();
        let result = bridge.translate_msp430_to_x86(&Msp430Opcode::BIS);
        assert!(result.is_some());
        match result.unwrap() {
            BridgeInstruction::DirectMapX86(op) => assert_eq!(op, X86Opcode::OR),
            _ => panic!("Expected DirectMapX86"),
        }
    }

    #[test]
    fn test_pattern_loading() {
        let patterns = SharedISelPatterns::default();
        assert!(patterns.pattern_count() > 20);
    }

    #[test]
    fn test_find_pattern() {
        let patterns = SharedISelPatterns::default();
        let result = patterns.find("add_16bit", true);
        assert!(result.is_some());
        let m = result.unwrap();
        assert_eq!(m.msp430_sequence[0], Msp430Opcode::ADD);
        assert_eq!(m.x86_sequence[0], X86Opcode::ADD);
    }

    #[test]
    fn test_lowering_rules() {
        let rules = CrossTargetLowering::default();
        assert!(rules.rule_count() >= 8);
    }

    #[test]
    fn test_apply_lowering_rule() {
        let rules = CrossTargetLowering::default();
        let results = rules.apply(&["cmp", "jmp"]);
        assert!(!results.is_empty());
        let first = &results[0];
        assert!(first.matched);
    }

    #[test]
    fn test_ra_context() {
        let ctx = SharedRegisterAllocContext::default();
        assert_eq!(ctx.msp430_classes.len(), 4);
        assert_eq!(ctx.x86_classes.len(), 2);
    }

    #[test]
    fn test_ra_allocate_free() {
        let mut ctx = SharedRegisterAllocContext::new();
        ctx.initialize();
        ctx.allocate_register(100, 8004);
        assert!(ctx.is_register_available(8005));
        assert!(!ctx.is_register_available(8004));
        ctx.free_register(8004);
        assert!(ctx.is_register_available(8004));
    }

    #[test]
    fn test_ra_spill_slot() {
        let mut ctx = SharedRegisterAllocContext::new();
        ctx.initialize();
        let slot = ctx.add_spill_slot(100, 2, 2);
        assert_eq!(slot, 0);
        assert!(ctx.is_spilled(100));
        let info = ctx.get_spill_slot(100).unwrap();
        assert_eq!(info.size, 2);
    }

    #[test]
    fn test_target_machine_msp430() {
        let tm = BridgeMSP430TargetMachine::new_msp430();
        assert!(!tm.is_msp430x());
        assert_eq!(tm.pointer_size, 2);
        assert_eq!(tm.get_target_name(), "msp430");
    }

    #[test]
    fn test_target_machine_msp430x() {
        let tm = BridgeMSP430TargetMachine::new_msp430x();
        assert!(tm.is_msp430x());
        assert_eq!(tm.pointer_size, 4);
        assert_eq!(tm.get_target_name(), "msp430x");
    }

    #[test]
    fn test_register_enumeration() {
        let regs = Msp430BridgeReg::allocatable_regs();
        assert_eq!(regs.len(), 12); // R4-R15
        assert!(Msp430BridgeReg::PC.is_special());
        assert!(Msp430BridgeReg::SP.is_special());
        assert!(!Msp430BridgeReg::R5.is_special());
    }

    #[test]
    fn test_register_callee_saved() {
        assert!(Msp430BridgeReg::R4.is_callee_saved());
        assert!(Msp430BridgeReg::R10.is_callee_saved());
        assert!(!Msp430BridgeReg::R12.is_callee_saved());
    }

    #[test]
    fn test_register_from_id() {
        assert_eq!(Msp430BridgeReg::from_id(8000), Some(Msp430BridgeReg::PC));
        assert_eq!(Msp430BridgeReg::from_id(8015), Some(Msp430BridgeReg::R15));
        assert_eq!(Msp430BridgeReg::from_id(9999), None);
    }

    #[test]
    fn test_calling_convention() {
        let cc = MSP430CallingConventionBridge::new();
        assert_eq!(cc.arg_regs.len(), 4);
        assert_eq!(cc.ret_regs.len(), 2);
        assert_eq!(cc.callee_saved.len(), 7);
        assert_eq!(cc.caller_saved.len(), 5);
        assert_eq!(cc.get_return_register(), 8012);
    }

    #[test]
    fn test_calling_convention_args() {
        let cc = MSP430CallingConventionBridge::new();
        assert_eq!(cc.get_arg_register(0), Some(8015)); // R15 = first arg
        assert_eq!(cc.get_arg_register(1), Some(8014)); // R14
        assert_eq!(cc.get_arg_register(4), None); // no 5th register arg
    }

    #[test]
    fn test_code_size_analyzer() {
        let mut analyzer = CodeSizeAnalyzer::new();
        analyzer.analyze_msp430(&[Msp430Opcode::MOV, Msp430Opcode::ADD, Msp430Opcode::JMP]);
        analyzer.analyze_x86(&[X86Opcode::MOV, X86Opcode::ADD, X86Opcode::JMP]);
        // MOV(4) + ADD(4) + JMP(4) = 12 for MSP430
        assert_eq!(analyzer.msp430_bytes, 12);
        // MOV(3) + ADD(3) + JMP(2) = 8 for X86
        assert_eq!(analyzer.x86_bytes, 8);
    }

    #[test]
    fn test_const_materializer() {
        let cm = CrossTargetConstMaterializer::new();
        assert_eq!(cm.materialize_msp430(0), vec![Msp430Opcode::CLR]);
        assert_eq!(cm.materialize_msp430(42), vec![Msp430Opcode::MOV]);
        assert_eq!(cm.materialize_x86_cost(0), 1);
        assert_eq!(cm.materialize_x86_cost(42), 1);
    }

    #[test]
    fn test_frame_context() {
        let mut ctx = SharedFrameLoweringContext::new();
        ctx.has_frame_pointer = true;
        ctx.frame_size = 8;
        ctx.add_callee_saved_slot(8004, -2);
        ctx.add_callee_saved_slot(8005, -4);

        assert_eq!(ctx.compute_prologue_size(), 6); // push fp + mov fp,sp + sub #8 + 2 callee pushes
        assert_eq!(ctx.get_callee_saved_offset(8004), Some(-2));
        assert_eq!(ctx.get_callee_saved_offset(8005), Some(-4));
    }

    #[test]
    fn test_instr_info_categorization() {
        let info = BridgeMSP430InstrInfo::new();
        assert_eq!(info.single_operand_ops.len(), 8);
        assert_eq!(info.double_operand_ops.len(), 12);
        assert_eq!(info.jump_ops.len(), 8);
        assert_eq!(info.emulated_ops.len(), 18);
        assert_eq!(info.msp430x_ops.len(), 9);
    }
}