llvm-native-core 0.1.10

//! Lanai Target Backend — Google Myricom Lanai 32-bit RISC
//! processor.
//!
//! Clean-room behavioral reconstruction from the Lanai ISA
//! specification and published documentation.
//! Zero LLVM source code consultation.
//!
//! The Lanai is a 32-bit RISC processor with:
//! - 32 general-purpose registers (r0–r31)
//! - 3-operand ALU instructions
//! - Conditional branch on condition codes
//! - Special registers: PC, PSW, MCR, IR
//!
//! Registers:
//! - r0: always zero
//! - r1/r4: return address (rca)
//! - r26: return value (rr1)
//! - r30: stack pointer (sp)
//! - r31: program counter (rpc)
//!
//! Modules:
//! - lanai_register_info: 32 GPRs + special registers
//! - lanai_instr_info: Full Lanai instruction descriptor table
//! - lanai_isel: Instruction selection from LLVM IR to Lanai
//! - lanai_asm_printer: Lanai assembly printer

pub mod lanai_asm_printer;
pub mod lanai_instr_info;
pub mod lanai_isel;
pub mod lanai_register_info;
pub mod lanai_x86_bridge;

pub use lanai_asm_printer::LanaiAsmPrinter;
pub use lanai_instr_info::{LanaiInstrDesc, LanaiInstrInfo, LanaiOpcode, LanaiOperandType};
pub use lanai_isel::LanaiInstructionSelector;
pub use lanai_register_info::{LanaiRegClass, LanaiRegisterInfo};

/// Lanai instruction size is always 32 bits (4 bytes).
pub const LANAI_INSTR_SIZE: u32 = 4;

/// Lanai endianness.
pub const LANAI_ENDIANNESS: &str = "big";

/// Lanai stack alignment.
pub const LANAI_STACK_ALIGNMENT: u32 = 8;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_lanai_constants() {
        assert_eq!(LANAI_INSTR_SIZE, 4);
        assert_eq!(LANAI_ENDIANNESS, "big");
        assert_eq!(LANAI_STACK_ALIGNMENT, 8);
    }
}