llvm-native-core 0.1.10

LLVM-native core semantic engine — IR, CodeGen, X86 MC, Clang frontend pipeline
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//! Hexagon Target Backend — Qualcomm Hexagon VLIW DSP architecture.
//!
//! Complete register information, instruction set metadata, instruction
//! selection, MC encoding, and assembly printer for the Qualcomm Hexagon
//! Very Long Instruction Word (VLIW) digital signal processor.
//!
//! Clean-room behavioral reconstruction from the Hexagon V5/V6 Programmer's
//! Reference Manual, the Hexagon Application Binary Interface Specification,
//! and the Qualcomm Hexagon SDK documentation. Zero LLVM source consultation.
//!
//! Architecture coverage:
//! - Hexagon V5/V6: 32-bit fixed-length instructions in 4-slot VLIW packets
//! - Predicated execution: IF p0/p1/p2/p3 conditionals
//! - SIMD vector extensions: v0-v31 with VADD/VSUB/VMPY/VSHUFF
//! - Hardware loops: loop0/loop1 with SPxLOOP/ENDLOOP

pub mod hexagon_asm_printer;
pub mod hexagon_instr_info;
pub mod hexagon_isel;
pub mod hexagon_isel_full;
pub mod hexagon_mc_encoder;
pub mod hexagon_register_info;
pub mod hexagon_x86_bridge;

// Re-export key types for convenience
pub use hexagon_asm_printer::HexagonAsmPrinter;
pub use hexagon_instr_info::{
    HexagonInstrDesc, HexagonInstrInfo, HexagonOpcode, HexagonOperandType,
};
pub use hexagon_isel::HexagonInstructionSelector;
pub use hexagon_mc_encoder::HexagonMCEncoder;
pub use hexagon_register_info::{
    HexagonRegClass, HexagonRegisterInfo, HEXAGON_GPR_BASE, HEXAGON_GPR_COUNT, HEXAGON_MAX_REG_ID,
    HEXAGON_PRED_BASE, HEXAGON_VEC_BASE,
};

/// Hexagon is little-endian.
pub const HEXAGON_ENDIANNESS: &str = "little";

/// Hexagon stack alignment (8 bytes).
pub const HEXAGON_STACK_ALIGNMENT: u32 = 8;

/// Hexagon red zone size (none defined by ABI).
pub const HEXAGON_RED_ZONE_SIZE: u32 = 0;

/// Default Hexagon page size (4 KiB).
pub const HEXAGON_PAGE_SIZE: u32 = 4096;

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_hexagon_constants() {
        assert_eq!(HEXAGON_ENDIANNESS, "little");
        assert_eq!(HEXAGON_STACK_ALIGNMENT, 8);
        assert_eq!(HEXAGON_RED_ZONE_SIZE, 0);
        assert_eq!(HEXAGON_PAGE_SIZE, 4096);
    }
}