llvm-native-core 0.1.10

//! AVR Instruction Encoder — encodes AVR instructions to machine code.
//!
//! AVR uses a primarily 16-bit instruction encoding scheme, with a few
//! 32-bit instructions (JMP, CALL, LDS, STS). Instructions are encoded
//! in little-endian byte order (low byte first).

use crate::avr::avr_instr_info::AvrOpcode;

// ============================================================================
//  AVR MC Encoder
// ============================================================================

/// Encodes AVR assembly instructions to machine-code bytes.
pub struct AvrMCEncoder;

impl AvrMCEncoder {
    pub fn new() -> Self {
        AvrMCEncoder
    }

    /// Encode a single AVR instruction with its operands.
    ///
    /// Returns the encoded bytes (2 or 4 bytes for AVR).
    pub fn encode(opcode: AvrOpcode, rd: u8, rr: u8, imm: u16) -> Vec<u8> {
        match opcode {
            // ---- Arithmetic ----
            // ADD rd, rr  =>  0000 11rd dddd rrrr
            AvrOpcode::ADD => {
                let word: u16 = 0x0C00
                    | ((rd as u16 & 0x1F) << 4)
                    | ((rd as u16 & 0x10) << 5)
                    | (rr as u16 & 0x0F)
                    | ((rr as u16 & 0x10) << 5);
                let w = 0x0C00
                    | (((rd & 0x1F) as u16) << 4)
                    | (((rd & 0x10) as u16) << 5)
                    | ((rr & 0x0F) as u16)
                    | (((rr & 0x10) as u16) << 5);
                vec![w as u8, (w >> 8) as u8]
            }

            // SUB rd, rr  =>  0001 10rd dddd rrrr
            AvrOpcode::SUB => {
                let word: u16 = encode_two_reg(0x1800, rd, rr);
                vec![word as u8, (word >> 8) as u8]
            }

            // AND rd, rr  =>  0010 00rd dddd rrrr
            AvrOpcode::AND => {
                let word: u16 = encode_two_reg(0x2000, rd, rr);
                vec![word as u8, (word >> 8) as u8]
            }

            // OR rd, rr  =>  0010 10rd dddd rrrr
            AvrOpcode::OR => {
                let word: u16 = encode_two_reg(0x2800, rd, rr);
                vec![word as u8, (word >> 8) as u8]
            }

            // EOR rd, rr  =>  0010 01rd dddd rrrr
            AvrOpcode::EOR => {
                let word: u16 = encode_two_reg(0x2400, rd, rr);
                vec![word as u8, (word >> 8) as u8]
            }

            // INC rd  =>  1001 010d dddd 0011
            AvrOpcode::INC => {
                let word: u16 = 0x9403 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // DEC rd  =>  1001 010d dddd 1010
            AvrOpcode::DEC => {
                let word: u16 = 0x940A | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // NEG rd  =>  1001 010d dddd 0001
            AvrOpcode::NEG => {
                let word: u16 = 0x9401 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // COM rd  =>  1001 010d dddd 0000
            AvrOpcode::COM => {
                let word: u16 = 0x9400 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // LSL rd  =>  same as ADD rd, rd
            AvrOpcode::LSL => {
                let word: u16 = encode_two_reg(0x0C00, rd, rd);
                vec![word as u8, (word >> 8) as u8]
            }

            // LSR rd  =>  1001 010d dddd 0110
            AvrOpcode::LSR => {
                let word: u16 = 0x9406 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // ROR rd  =>  1001 010d dddd 0111
            AvrOpcode::ROR => {
                let word: u16 = 0x9407 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // ASR rd  =>  1001 010d dddd 0101
            AvrOpcode::ASR => {
                let word: u16 = 0x9405 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // SWAP rd  =>  1001 010d dddd 0010
            AvrOpcode::SWAP => {
                let word: u16 = 0x9402 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // MOV rd, rr  =>  0010 11rd dddd rrrr
            AvrOpcode::MOV => {
                let word: u16 = encode_two_reg(0x2C00, rd, rr);
                vec![word as u8, (word >> 8) as u8]
            }

            // LDI rd, K  =>  1110 KKKK dddd KKKK
            AvrOpcode::LDI => {
                if rd < 16 {
                    return vec![0, 0]; // LDI only works on r16-r31
                }
                let k = imm as u8;
                let word: u16 = 0xE000u16
                    | ((k as u16 & 0xF0u16) << 4)
                    | (((rd - 16) & 0x0F) as u16) << 4
                    | (k & 0x0F) as u16;
                vec![word as u8, (word >> 8) as u8]
            }

            // NOP  =>  0000 0000 0000 0000
            AvrOpcode::NOP => vec![0, 0],

            // RJMP k  =>  1100 kkkk kkkk kkkk
            AvrOpcode::RJMP => {
                // k is signed 12-bit offset (in words)
                let k = (imm as i16) & 0xFFF;
                let word: u16 = 0xC000 | (k as u16 & 0xFFF);
                vec![word as u8, (word >> 8) as u8]
            }

            // IJMP  =>  1001 0100 0000 1001
            AvrOpcode::IJMP => vec![0x09, 0x94],

            // JMP addr  =>  1001 010k kkkk 110k kkkk kkkk kkkk kkkk
            AvrOpcode::JMP => {
                // 22-bit address
                let addr = imm as u32 & 0x3FFFFF;
                let word1: u16 =
                    0x940C | (((addr >> 18) & 0x3F) as u16) << 3 | ((addr >> 16) as u16 & 0x01);
                let word2: u16 = (addr & 0xFFFF) as u16;
                vec![
                    word1 as u8,
                    (word1 >> 8) as u8,
                    word2 as u8,
                    (word2 >> 8) as u8,
                ]
            }

            // CALL addr  =>  1001 010k kkkk 111k kkkk kkkk kkkk kkkk
            AvrOpcode::CALL => {
                let addr = imm as u32 & 0x3FFFFF;
                let word1: u16 =
                    0x940E | (((addr >> 18) & 0x3F) as u16) << 3 | ((addr >> 16) as u16 & 0x01);
                let word2: u16 = (addr & 0xFFFF) as u16;
                vec![
                    word1 as u8,
                    (word1 >> 8) as u8,
                    word2 as u8,
                    (word2 >> 8) as u8,
                ]
            }

            // RCALL k  =>  1101 kkkk kkkk kkkk
            AvrOpcode::RCALL => {
                let k = (imm as i16) & 0xFFF;
                let word: u16 = 0xD000 | (k as u16 & 0xFFF);
                vec![word as u8, (word >> 8) as u8]
            }

            // RET  =>  1001 0101 0000 1000
            AvrOpcode::RET => vec![0x08, 0x95],

            // RETI  =>  1001 0101 0001 1000
            AvrOpcode::RETI => vec![0x18, 0x95],

            // IN rd, A  =>  1011 0AAd dddd AAAA
            AvrOpcode::IN => {
                let a = imm as u8 & 0x3F;
                let word: u16 = 0xB000u16
                    | ((a as u16 & 0x30u16) << 5)
                    | ((rd as u16 & 0x1Fu16) << 4)
                    | (a & 0x0F) as u16;
                vec![word as u8, (word >> 8) as u8]
            }

            // OUT A, rr  =>  1011 1AAr rrrr AAAA
            AvrOpcode::OUT => {
                let a = imm as u8 & 0x3F;
                let word: u16 = 0xB800u16
                    | ((a as u16 & 0x30u16) << 5)
                    | ((rr as u16 & 0x1Fu16) << 4)
                    | (a & 0x0F) as u16;
                vec![word as u8, (word >> 8) as u8]
            }

            // PUSH rr  =>  1001 001d dddd 1111
            AvrOpcode::PUSH => {
                let word: u16 = 0x920F | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // POP rd  =>  1001 000d dddd 1111
            AvrOpcode::POP => {
                let word: u16 = 0x900F | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8]
            }

            // SBI A, b  =>  1001 1010 AAAA Abbb
            AvrOpcode::SBI => {
                let a = imm as u8 & 0x1F;
                let b = rd as u8 & 0x07;
                let word: u16 = 0x9A00 | (a as u16) << 3 | (b as u16);
                vec![word as u8, (word >> 8) as u8]
            }

            // CBI A, b  =>  1001 1000 AAAA Abbb
            AvrOpcode::CBI => {
                let a = imm as u8 & 0x1F;
                let b = rd as u8 & 0x07;
                let word: u16 = 0x9800 | (a as u16) << 3 | (b as u16);
                vec![word as u8, (word >> 8) as u8]
            }

            // LDS rd, addr (32-bit) => 1001 000d dddd 0000
            AvrOpcode::LDS => {
                let addr = imm;
                let word: u16 = 0x9000 | ((rd as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8, addr as u8, (addr >> 8) as u8]
            }

            // STS addr, rr (32-bit) => 1001 001d dddd 0000
            AvrOpcode::STS => {
                let addr = imm;
                let word: u16 = 0x9200 | ((rr as u16 & 0x1F) << 4);
                vec![word as u8, (word >> 8) as u8, addr as u8, (addr >> 8) as u8]
            }

            // BREAK  =>  1001 0101 1001 1000
            AvrOpcode::BREAK => vec![0x98, 0x95],

            // SLEEP  =>  1001 0101 1000 1000
            AvrOpcode::SLEEP => vec![0x88, 0x95],

            // WDR  =>  1001 0101 1010 1000
            AvrOpcode::WDR => vec![0xA8, 0x95],

            // Default: return zeros for unimplemented encodings
            _ => vec![0, 0],
        }
    }

    /// Get the byte size of an instruction encoding.
    pub fn instr_size(opcode: AvrOpcode) -> u8 {
        match opcode {
            AvrOpcode::JMP | AvrOpcode::CALL | AvrOpcode::LDS | AvrOpcode::STS => 4,
            _ => 2,
        }
    }

    /// Check if this opcode is a 32-bit instruction.
    pub fn is_32bit(opcode: AvrOpcode) -> bool {
        Self::instr_size(opcode) == 4
    }

    /// Encode raw machine code from a list of opcodes (for testing).
    pub fn encode_sequence(opcodes: &[(AvrOpcode, u8, u8, u16)]) -> Vec<u8> {
        let mut bytes = Vec::new();
        for &(op, rd, rr, imm) in opcodes {
            bytes.extend(Self::encode(op, rd, rr, imm));
        }
        bytes
    }
}

/// Encode a two-register instruction in the format `OP rd, rr`.
///
/// Most AVR 2-operand instructions use: `[opcode] r[4:0] r[4:0] r[9] r[4:0] r[9]`
fn encode_two_reg(base: u16, rd: u8, rr: u8) -> u16 {
    base | ((rd as u16 & 0x10) << 5)
        | ((rd as u16 & 0x0F) << 4)
        | ((rr as u16 & 0x10) << 1)
        | (rr as u16 & 0x0F)
}

// ============================================================================
//  Tests
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_encode_nop() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::NOP, 0, 0, 0);
        assert_eq!(bytes, vec![0x00, 0x00]);
    }

    #[test]
    fn test_encode_ret() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::RET, 0, 0, 0);
        assert_eq!(bytes, vec![0x08, 0x95]);
    }

    #[test]
    fn test_encode_reti() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::RETI, 0, 0, 0);
        assert_eq!(bytes, vec![0x18, 0x95]);
    }

    #[test]
    fn test_encode_rjmp_zero_offset() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::RJMP, 0, 0, 0);
        assert_eq!(bytes, vec![0x00, 0xC0]);
    }

    #[test]
    fn test_encode_ijmp() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::IJMP, 0, 0, 0);
        assert_eq!(bytes, vec![0x09, 0x94]);
    }

    #[test]
    fn test_encode_break() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::BREAK, 0, 0, 0);
        assert_eq!(bytes, vec![0x98, 0x95]);
    }

    #[test]
    fn test_encode_sleep() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::SLEEP, 0, 0, 0);
        assert_eq!(bytes, vec![0x88, 0x95]);
    }

    #[test]
    fn test_encode_wdr() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::WDR, 0, 0, 0);
        assert_eq!(bytes, vec![0xA8, 0x95]);
    }

    #[test]
    fn test_encode_mov_r16_r16() {
        // MOV r16, r16 — each source/dest bit pattern
        let bytes = AvrMCEncoder::encode(AvrOpcode::MOV, 16, 16, 0);
        // base=0x2C00, rd=16 (0x10), rr=16 (0x10)
        // encode_two_reg: base | (0x10<<5) | (0x00) | (0x10<<1) | 0x00
        // = 0x2C00 | 0x0200 | 0x0000 | 0x0020 | 0x0000 = 0x2E20
        assert_eq!(bytes, vec![0x20, 0x2E]);
    }

    #[test]
    fn test_encode_push_r0() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::PUSH, 0, 0, 0);
        assert_eq!(bytes, vec![0x0F, 0x92]);
    }

    #[test]
    fn test_encode_pop_r0() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::POP, 0, 0, 0);
        assert_eq!(bytes, vec![0x0F, 0x90]);
    }

    #[test]
    fn test_instr_size_16bit() {
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::ADD), 2);
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::NOP), 2);
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::RJMP), 2);
    }

    #[test]
    fn test_instr_size_32bit() {
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::JMP), 4);
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::CALL), 4);
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::LDS), 4);
        assert_eq!(AvrMCEncoder::instr_size(AvrOpcode::STS), 4);
    }

    #[test]
    fn test_is_32bit() {
        assert!(!AvrMCEncoder::is_32bit(AvrOpcode::ADD));
        assert!(AvrMCEncoder::is_32bit(AvrOpcode::JMP));
        assert!(AvrMCEncoder::is_32bit(AvrOpcode::CALL));
    }

    #[test]
    fn test_encode_call_addr() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::CALL, 0, 0, 0x1000);
        assert_eq!(bytes.len(), 4);
        // word1: 0x940E | ((0x1000>>18)&0x3F)<<3 = 0x940E
        // word2: 0x1000
        assert_eq!(bytes[2], 0x00);
        assert_eq!(bytes[3], 0x10);
    }

    #[test]
    fn test_encode_jmp_addr() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::JMP, 0, 0, 0x2000);
        assert_eq!(bytes.len(), 4);
    }

    #[test]
    fn test_encode_ldi_r16() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::LDI, 16, 0, 0xAB);
        // rd=16 -> (16-16)=0, K=0xAB
        // word = 0xE000 | ((0xAB&0xF0)<<4) | (0)<<4 | (0xAB&0x0F)
        // = 0xE000 | 0x0A00 | 0x0000 | 0x000B = 0xEA0B
        assert_eq!(bytes[0], 0x0B);
        assert_eq!(bytes[1], 0xEA);
    }

    #[test]
    fn test_encode_ldi_invalid_rd() {
        // LDI only valid for r16-r31; r0 will encode incorrectly
        let bytes = AvrMCEncoder::encode(AvrOpcode::LDI, 0, 0, 0xFF);
        assert_eq!(bytes, vec![0, 0]);
    }

    #[test]
    fn test_encode_sequence() {
        let seq = vec![(AvrOpcode::NOP, 0, 0, 0), (AvrOpcode::RET, 0, 0, 0)];
        let bytes = AvrMCEncoder::encode_sequence(&seq);
        assert_eq!(bytes, vec![0x00, 0x00, 0x08, 0x95]);
    }

    #[test]
    fn test_encode_sub() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::SUB, 16, 17, 0);
        // base=0x1800, rd=16, rr=17
        // = 0x1800 | 0x0200 | 0x0000 | 0x0020 | 0x0001 = 0x1A21
        assert_eq!(bytes.len(), 2);
    }

    #[test]
    fn test_encode_add() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::ADD, 0, 1, 0);
        assert_eq!(bytes.len(), 2);
    }

    #[test]
    fn test_encode_neg() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::NEG, 0, 0, 0);
        assert_eq!(bytes, vec![0x01, 0x94]);
    }

    #[test]
    fn test_encode_com() {
        let bytes = AvrMCEncoder::encode(AvrOpcode::COM, 0, 0, 0);
        assert_eq!(bytes, vec![0x00, 0x94]);
    }
}