llvm-native-core 0.1.10

//! ARM Full Instruction Information — extended opcode definitions
//! covering ARM32 extended DSP/SIMD, system, synchronization,
//! advanced SIMD (NEON), AArch64 atomic/pointer-auth/crypto/CRC
//! instructions beyond the basic set.
//!
//! Clean-room behavioral reconstruction from the ARM Architecture
//! Reference Manual (ARM ARM), AArch64 ISA encoding, and ARM32
//! instruction set specifications.

use std::collections::HashMap;

/// Full extended ARM opcodes covering ARM32 DSP, SIMD, system,
/// synchronization, and AArch64 advanced features.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum ArmFullOpcode {
    // === ARM32 additional arithmetic ===
    Sbc,
    Rsc,
    Rsb,
    Adc,
    Qadd,
    Qsub,
    Qdadd,
    Qdsub,
    // === ARM32 multiply-accumulate extended ===
    Smlal,
    Smull,
    Umlal,
    Umull,
    Smlabb,
    Smlabt,
    Smlatb,
    Smlatt,
    Smlalbb,
    Smlalbt,
    Smlaltb,
    Smlaltt,
    Smulbb,
    Smulbt,
    Smultb,
    Smultt,
    Smulwb,
    Smulwt,
    Smlawb,
    Smlawt,
    // === ARM32 packing/unpacking ===
    Pkhbt,
    Pkhtb,
    Usat,
    Ssat,
    Usat16,
    Ssat16,
    // === ARM32 SIMD (Pre-NEON DSP extensions) ===
    Uqadd8,
    Uqadd16,
    Uqadd32,
    Uqsub8,
    Uqsub16,
    Uqsub32,
    Uhadd8,
    Uhadd16,
    Uhadd32,
    Uhsub8,
    Uhsub16,
    Uhsub32,
    Shadd8,
    Shadd16,
    Shadd32,
    Shsub8,
    Shsub16,
    Shsub32,
    Usad8,
    Usada8,
    Sel,
    Sadd8,
    Sadd16,
    Ssub8,
    Ssub16,
    // === ARM32 bit manipulation ===
    Rev,
    Rev16,
    Revsh,
    Rbit,
    Clz,
    // === ARM32 cache/prefetch ===
    Pld,
    Pli,
    Pldw,
    // === ARM32 barriers ===
    Dmb,
    Dsb,
    Isb,
    // === ARM32 hint/wait ===
    Yield,
    Wfe,
    Wfi,
    Sev,
    Sevl,
    // === ARM32 debug/exception ===
    Dbg,
    Bkpt,
    Hvc,
    Smc,
    Svc,
    // === ARM32 system register access ===
    Mrs,
    Msr,
    Cps,
    Setend,
    // === ARM32 exclusive access ===
    Ldrex,
    Strex,
    Ldrexb,
    Strexb,
    Ldrexh,
    Strexh,
    Ldrexd,
    Strexd,
    Clrex,
    Swp,
    Swpb,
    // === ARM32 load/store dual / halfword / signed ===
    Ldrd,
    Strd,
    Ldrh,
    Ldrsb,
    Ldrsh,
    Strh,
    // === ARM32 block data transfer ===
    Ldm,
    Stm,
    Ldmda,
    Stmda,
    Ldmdb,
    Stmdb,
    Ldmib,
    Stmib,
    // === ARM32 exception return ===
    Rfe,
    Srs,
    // === ARM32 NEON/VFP — absolute/comparison ===
    Vaba,
    Vabd,
    Vabs,
    Vacge,
    Vacgt,
    Vacle,
    Vaclt,
    // === ARM32 NEON — arithmetic ===
    Vadd,
    Vaddhn,
    Vaddl,
    Vaddw,
    // === ARM32 NEON — bitwise ===
    Vand,
    Vbic,
    Vbif,
    Vbit,
    Vbsl,
    // === ARM32 NEON — comparison ===
    Vceq,
    Vcge,
    Vcgt,
    Vcle,
    Vclt,
    Vcls,
    Vclz,
    Vcnt,
    Vcmp,
    Vcmpe,
    Vcvt,
    Vcvtb,
    Vcvtt,
    // === ARM32 NEON — division/duplicate/extract ===
    Vdiv,
    Vdup,
    Veor,
    Vext,
    // === ARM32 NEON — fused multiply-add ===
    Vfma,
    Vfms,
    Vfnma,
    Vfnms,
    // === ARM32 NEON — halving add/sub ===
    Vhadd,
    Vhsub,
    // === ARM32 NEON — load/store structures ===
    Vld1,
    Vld2,
    Vld3,
    Vld4,
    // === ARM32 NEON — max/min/MLA/MLS/move ===
    Vmax,
    Vmin,
    Vmla,
    Vmls,
    Vmov,
    Vmovl,
    Vmovn,
    Vmrs,
    Vmsr,
    Vmul,
    Vmull,
    Vmvn,
    Vneg,
    Vnmla,
    Vnmls,
    Vnmul,
    Vorn,
    Vorr,
    // === ARM32 NEON — pairwise ===
    Vpadal,
    Vpadd,
    Vpaddl,
    Vpmax,
    Vpmin,
    // === ARM32 NEON — saturating absolute/add/DMLAL/DMLSL/DMULH/DMULL ===
    Vqabs,
    Vqadd,
    Vqdmlal,
    Vqdmlsl,
    Vqdmulh,
    Vqdmull,
    Vqmovn,
    Vqmovun,
    Vqneg,
    Vqrdmulh,
    Vqrshl,
    Vqrshrn,
    Vqrshrun,
    Vqshl,
    Vqshlu,
    Vqshrn,
    Vqshrun,
    Vqsub,
    // === ARM32 NEON — rounding/reciprocal/rev ===
    Vraddhn,
    Vrecpe,
    Vrecps,
    Vrev16Neon,
    Vrev32Neon,
    Vrev64Neon,
    Vrhadd,
    Vrshl,
    Vrshr,
    Vrshrn,
    Vrsqrte,
    Vrsqrts,
    Vrsra,
    Vrsubhn,
    // === ARM32 NEON — shift/insert/sqrt ===
    Vshl,
    Vshll,
    Vshr,
    Vshrn,
    Vsli,
    Vsqrt,
    Vsra,
    Vsri,
    // === ARM32 NEON — store structures ===
    Vst1,
    Vst2,
    Vst3,
    Vst4,
    // === ARM32 NEON — subtract ===
    Vsub,
    Vsubhn,
    Vsubl,
    Vsubw,
    // === ARM32 NEON — swap/table/transpose/test/zip ===
    Vswp,
    Vtbl,
    Vtbx,
    Vtrn,
    Vtst,
    Vuzp,
    Vzip,

    // ==========================================================
    // AArch64 additional opcodes
    // ==========================================================

    // === AArch64 speculation barriers ===
    Csdb,
    Pssbb,
    Ssbb,
    // === AArch64 exception return ===
    Eret,
    Drps,
    // === AArch64 cache/TLB maintenance ===
    Dc,
    Ic,
    At,
    Tlbi,
    // === AArch64 exclusive pair ===
    Ldxp,
    Stxp,
    Ldaxp,
    Stlxp,
    // === AArch64 exclusive load/store acquire/release ===
    Ldaxr,
    Stlxr,
    Ldaxrb,
    Stlxrb,
    Ldaxrh,
    Stlxrh,
    // === AArch64 CAS (Compare-And-Swap) ===
    Cas,
    Casa,
    Casl,
    Casal,
    Casb,
    Casab,
    Caslb,
    Casalb,
    Cash,
    Casah,
    Caslh,
    Casalh,
    // === AArch64 atomic memory operations (LSE) ===
    Ldadd,
    Ldadda,
    Ldaddl,
    Ldaddal,
    Ldset,
    Ldsmax,
    Ldsmin,
    Ldumax,
    Ldumin,
    // === AArch64 swap / LDApR / STLR ===
    SwpAarch64,
    Ldapr,
    Stlr,
    // === AArch64 pointer authentication ===
    Pacia,
    Pacib,
    Pacda,
    Pacdb,
    Autia,
    Autib,
    Autda,
    Autdb,
    Paciza,
    Pacizb,
    Pacdza,
    Pacdzb,
    Autiza,
    Autizb,
    Autdza,
    Autdzb,
    Xpaci,
    Xpacd,
    // === AArch64 branch target identification ===
    Bti,
    Blraa,
    Blrab,
    Braa,
    Brab,
    // === AArch64 error synchronization barrier ===
    Esb,
    Psb,
    // === AArch64 system register access ===
    MrsAarch64,
    MsrAarch64,
    Sys,
    Sysl,
    // === AArch64 CRC ===
    Crc32b,
    Crc32h,
    Crc32w,
    Crc32x,
    Crc32cb,
    Crc32ch,
    Crc32cw,
    Crc32cx,
    // === AArch64 AES crypto ===
    Aesd,
    Aese,
    Aesimc,
    Aesmc,
    // === AArch64 SHA1 ===
    Sha1h,
    Sha1su0,
    Sha1su1,
    // === AArch64 SHA256 ===
    Sha256su0,
    Sha256su1,
    Sha256h,
    Sha256h2,
    // === AArch64 SHA512 ===
    Sha512h,
    Sha512h2,
    Sha512su0,
    Sha512su1,
    // === AArch64 SM3 crypto ===
    Sm3ss1,
    Sm3tt1a,
    Sm3tt1b,
    Sm3tt2a,
    Sm3tt2b,
    Sm3partw1,
    Sm3partw2,
    // === AArch64 SM4 crypto ===
    Sm4e,
    Sm4ekey,
    // === AArch64 SHA1 (additional variants) ===
    Sha1c,
    Sha1p,
    Sha1m,
    Sha1hA64,
    // === AArch64 bitfield ===
    Bc,
    Bfc,
    Bfi,
    Bfxil,
    Ubfiz,
    Sbfiz,
    Ubfx,
    Sbfx,
    // === AArch64 extract/rotate ===
    Extr,
    RorImm,
    RorV,
    // === AArch64 conditional compare/select ===
    Ccmn,
    Ccmp,
    Csinc,
    Csel,
    // === AArch64 floating-point conditional ===
    Fcsel,
    Fmadd,
    Fmsub,
    Fnmadd,
    Fnmsub,
    // === AArch64 floating-point rounding ===
    Frintn,
    Frintp,
    Frintm,
    Frintz,
    Frinta,
    Frintx,
    Frinti,
    // === AArch64 floating-point conversion ===
    Scvtf,
    Ucvtf,
    Fcvtzs,
    Fcvtzu,
    Fcvtas,
    Fcvtaus,
    Fcvtps,
    Fcvtpu,
    Fcvtms,
    Fcvtmu,
    // === AArch64 floating-point move ===
    FmovAarch64,
    // === AArch64 floating-point max/min ===
    Fmax,
    Fmin,
    Fmaxnm,
    Fminnm,
    // === AArch64 integer absolute/negate ===
    AbsAarch64,
    NegAarch64,
    // === AArch64 bit manipulation ===
    RbitAarch64,
    RevAarch64,
    Rev16Aarch64,
    Rev32Aarch64,
    ClzAarch64,
    Cls,
    // === AArch64 divide ===
    SdivAarch64,
    UdivAarch64,
    // === AArch64 multiply-add/sub ===
    Madd,
    Msub,
    Mneg,
    Smulh,
    Umulh,
    // === AArch64 ALU with flags ===
    AddsAarch64,
    SubsAarch64,
    Adcs,
    Sbcs,
    Ands,
    Bics,
    Negs,
    Ngcs,
    // === AArch64 variable shift ===
    Lslv,
    Lsrv,
    Asrv,
    Rorv,
    // === AArch64 prefetch ===
    Prfm,
    Prfum,

    /// Sentinel for invalid/unknown opcodes.
    Invalid,
}

/// Describes an instruction's operand constraints and encoding class.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub enum ArmFullOperandClass {
    /// Three registers (dst, src1, src2)
    Reg3,
    /// Two GPR registers
    Reg2,
    /// Register + immediate
    RegImm,
    /// Register + register + immediate
    RegRegImm,
    /// Memory operand (base + offset)
    Mem,
    /// Register list for LDM/STM
    RegList,
    /// System register
    SysReg,
    /// Label / branch target
    Label,
    /// No operands (implicit)
    None_,
}

/// Full instruction descriptor for extended opcodes.
#[derive(Debug, Clone)]
pub struct ArmFullInstrDesc {
    pub opcode: ArmFullOpcode,
    pub mnemonic: &'static str,
    pub operands: ArmFullOperandClass,
    pub is_aarch64: bool,
    pub is_arm32: bool,
    pub is_thumb: bool,
    pub is_simd: bool,
    pub is_crypto: bool,
    pub is_atomic: bool,
    pub is_barrier: bool,
    pub has_side_effects: bool,
    pub may_load: bool,
    pub may_store: bool,
    pub encoding_length: u8, // 2, 4 bytes
}

/// The full instruction information table.
pub struct ArmFullInstrInfo {
    descriptors: Vec<ArmFullInstrDesc>,
    mnemonic_map: HashMap<String, usize>,
}

impl ArmFullInstrInfo {
    /// Build the complete instruction table.
    pub fn new() -> Self {
        let descriptors = vec![
            // ARM32 arithmetic
            desc(
                ArmFullOpcode::Sbc,
                "sbc",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Rsc,
                "rsc",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Rsb,
                "rsb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Adc,
                "adc",
                ArmFullOperandClass::Reg3,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Qadd,
                "qadd",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Qsub,
                "qsub",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Qdadd,
                "qdadd",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Qdsub,
                "qdsub",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            // ARM32 multiply
            desc(
                ArmFullOpcode::Smlal,
                "smlal",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smull,
                "smull",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Umlal,
                "umlal",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Umull,
                "umull",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlabb,
                "smlabb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlabt,
                "smlabt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlatb,
                "smlatb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlatt,
                "smlatt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlalbb,
                "smlalbb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlalbt,
                "smlalbt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlaltb,
                "smlaltb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlaltt,
                "smlaltt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smulbb,
                "smulbb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smulbt,
                "smulbt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smultb,
                "smultb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smultt,
                "smultt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smulwb,
                "smulwb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smulwt,
                "smulwt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlawb,
                "smlawb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smlawt,
                "smlawt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            // Packing
            desc(
                ArmFullOpcode::Pkhbt,
                "pkhbt",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Pkhtb,
                "pkhtb",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Usat,
                "usat",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ssat,
                "ssat",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Usat16,
                "usat16",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ssat16,
                "ssat16",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            // SIMD DSP
            desc(
                ArmFullOpcode::Uqadd8,
                "uqadd8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uqadd16,
                "uqadd16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uqadd32,
                "uqadd32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uqsub8,
                "uqsub8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uqsub16,
                "uqsub16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uqsub32,
                "uqsub32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhadd8,
                "uhadd8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhadd16,
                "uhadd16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhadd32,
                "uhadd32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhsub8,
                "uhsub8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhsub16,
                "uhsub16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Uhsub32,
                "uhsub32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shadd8,
                "shadd8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shadd16,
                "shadd16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shadd32,
                "shadd32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shsub8,
                "shsub8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shsub16,
                "shsub16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Shsub32,
                "shsub32",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Usad8,
                "usad8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Usada8,
                "usada8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Sel,
                "sel",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Sadd8,
                "sadd8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Sadd16,
                "sadd16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ssub8,
                "ssub8",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ssub16,
                "ssub16",
                ArmFullOperandClass::Reg3,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            // Bit manipulation
            desc(
                ArmFullOpcode::Rev,
                "rev",
                ArmFullOperandClass::Reg2,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Rev16,
                "rev16",
                ArmFullOperandClass::Reg2,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Revsh,
                "revsh",
                ArmFullOperandClass::Reg2,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Rbit,
                "rbit",
                ArmFullOperandClass::Reg2,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Clz,
                "clz",
                ArmFullOperandClass::Reg2,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                4,
            ),
            // Cache/prefetch
            desc(
                ArmFullOpcode::Pld,
                "pld",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Pli,
                "pli",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Pldw,
                "pldw",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                4,
            ),
            // Barriers
            desc(
                ArmFullOpcode::Dmb,
                "dmb",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Dsb,
                "dsb",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Isb,
                "isb",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                false,
                4,
            ),
            // Hints
            desc(
                ArmFullOpcode::Yield,
                "yield",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Wfe,
                "wfe",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Wfi,
                "wfi",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Sev,
                "sev",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Sevl,
                "sevl",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            // Debug/exception
            desc(
                ArmFullOpcode::Dbg,
                "dbg",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Bkpt,
                "bkpt",
                ArmFullOperandClass::RegImm,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Hvc,
                "hvc",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Smc,
                "smc",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Svc,
                "svc",
                ArmFullOperandClass::RegImm,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            // System register
            desc(
                ArmFullOpcode::Mrs,
                "mrs",
                ArmFullOperandClass::SysReg,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Msr,
                "msr",
                ArmFullOperandClass::SysReg,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Cps,
                "cps",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Setend,
                "setend",
                ArmFullOperandClass::RegImm,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            // Exclusive
            desc(
                ArmFullOpcode::Ldrex,
                "ldrex",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strex,
                "strex",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrexb,
                "ldrexb",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strexb,
                "strexb",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrexh,
                "ldrexh",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strexh,
                "strexh",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrexd,
                "ldrexd",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strexd,
                "strexd",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Clrex,
                "clrex",
                ArmFullOperandClass::None_,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Swp,
                "swp",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Swpb,
                "swpb",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                4,
            ),
            // Load/store dual/halfword
            desc(
                ArmFullOpcode::Ldrd,
                "ldrd",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strd,
                "strd",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrh,
                "ldrh",
                ArmFullOperandClass::Mem,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrsb,
                "ldrsb",
                ArmFullOperandClass::Mem,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Ldrsh,
                "ldrsh",
                ArmFullOperandClass::Mem,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Strh,
                "strh",
                ArmFullOperandClass::Mem,
                false,
                true,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            // Block transfer
            desc(
                ArmFullOpcode::Ldm,
                "ldm",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Stm,
                "stm",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldmda,
                "ldmda",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Stmda,
                "stmda",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldmdb,
                "ldmdb",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Stmdb,
                "stmdb",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            desc(
                ArmFullOpcode::Ldmib,
                "ldmib",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Stmib,
                "stmib",
                ArmFullOperandClass::RegList,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                false,
                false,
                true,
                4,
            ),
            // Exception return
            desc(
                ArmFullOpcode::Rfe,
                "rfe",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                true,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Srs,
                "srs",
                ArmFullOperandClass::Mem,
                false,
                true,
                false,
                false,
                false,
                false,
                false,
                true,
                false,
                true,
                4,
            ),
            // === NEON/VFP ===
            desc_neon(ArmFullOpcode::Vaba, "vaba"),
            desc_neon(ArmFullOpcode::Vabd, "vabd"),
            desc_neon(ArmFullOpcode::Vabs, "vabs"),
            desc_neon(ArmFullOpcode::Vacge, "vacge"),
            desc_neon(ArmFullOpcode::Vacgt, "vacgt"),
            desc_neon(ArmFullOpcode::Vacle, "vacle"),
            desc_neon(ArmFullOpcode::Vaclt, "vaclt"),
            desc_neon(ArmFullOpcode::Vadd, "vadd"),
            desc_neon(ArmFullOpcode::Vaddhn, "vaddhn"),
            desc_neon(ArmFullOpcode::Vaddl, "vaddl"),
            desc_neon(ArmFullOpcode::Vaddw, "vaddw"),
            desc_neon(ArmFullOpcode::Vand, "vand"),
            desc_neon(ArmFullOpcode::Vbic, "vbic"),
            desc_neon(ArmFullOpcode::Vbif, "vbif"),
            desc_neon(ArmFullOpcode::Vbit, "vbit"),
            desc_neon(ArmFullOpcode::Vbsl, "vbsl"),
            desc_neon(ArmFullOpcode::Vceq, "vceq"),
            desc_neon(ArmFullOpcode::Vcge, "vcge"),
            desc_neon(ArmFullOpcode::Vcgt, "vcgt"),
            desc_neon(ArmFullOpcode::Vcle, "vcle"),
            desc_neon(ArmFullOpcode::Vclt, "vclt"),
            desc_neon(ArmFullOpcode::Vcls, "vcls"),
            desc_neon(ArmFullOpcode::Vclz, "vclz"),
            desc_neon(ArmFullOpcode::Vcnt, "vcnt"),
            desc_neon(ArmFullOpcode::Vcmp, "vcmp"),
            desc_neon(ArmFullOpcode::Vcmpe, "vcmpe"),
            desc_neon(ArmFullOpcode::Vcvt, "vcvt"),
            desc_neon(ArmFullOpcode::Vcvtb, "vcvtb"),
            desc_neon(ArmFullOpcode::Vcvtt, "vcvtt"),
            desc_neon(ArmFullOpcode::Vdiv, "vdiv"),
            desc_neon(ArmFullOpcode::Vdup, "vdup"),
            desc_neon(ArmFullOpcode::Veor, "veor"),
            desc_neon(ArmFullOpcode::Vext, "vext"),
            desc_neon(ArmFullOpcode::Vfma, "vfma"),
            desc_neon(ArmFullOpcode::Vfms, "vfms"),
            desc_neon(ArmFullOpcode::Vfnma, "vfnma"),
            desc_neon(ArmFullOpcode::Vfnms, "vfnms"),
            desc_neon(ArmFullOpcode::Vhadd, "vhadd"),
            desc_neon(ArmFullOpcode::Vhsub, "vhsub"),
            desc_neon_load_store(ArmFullOpcode::Vld1, "vld1"),
            desc_neon_load_store(ArmFullOpcode::Vld2, "vld2"),
            desc_neon_load_store(ArmFullOpcode::Vld3, "vld3"),
            desc_neon_load_store(ArmFullOpcode::Vld4, "vld4"),
            desc_neon(ArmFullOpcode::Vmax, "vmax"),
            desc_neon(ArmFullOpcode::Vmin, "vmin"),
            desc_neon(ArmFullOpcode::Vmla, "vmla"),
            desc_neon(ArmFullOpcode::Vmls, "vmls"),
            desc_neon(ArmFullOpcode::Vmov, "vmov"),
            desc_neon(ArmFullOpcode::Vmovl, "vmovl"),
            desc_neon(ArmFullOpcode::Vmovn, "vmovn"),
            desc_neon(ArmFullOpcode::Vmul, "vmul"),
            desc_neon(ArmFullOpcode::Vmull, "vmull"),
            desc_neon(ArmFullOpcode::Vmvn, "vmvn"),
            desc_neon(ArmFullOpcode::Vneg, "vneg"),
            desc_neon(ArmFullOpcode::Vnmla, "vnmla"),
            desc_neon(ArmFullOpcode::Vnmls, "vnmls"),
            desc_neon(ArmFullOpcode::Vnmul, "vnmul"),
            desc_neon(ArmFullOpcode::Vorn, "vorn"),
            desc_neon(ArmFullOpcode::Vorr, "vorr"),
            desc_neon(ArmFullOpcode::Vpadal, "vpadal"),
            desc_neon(ArmFullOpcode::Vpadd, "vpadd"),
            desc_neon(ArmFullOpcode::Vpaddl, "vpaddl"),
            desc_neon(ArmFullOpcode::Vpmax, "vpmax"),
            desc_neon(ArmFullOpcode::Vpmin, "vpmin"),
            desc_neon(ArmFullOpcode::Vqabs, "vqabs"),
            desc_neon(ArmFullOpcode::Vqadd, "vqadd"),
            desc_neon(ArmFullOpcode::Vqdmlal, "vqdmlal"),
            desc_neon(ArmFullOpcode::Vqdmlsl, "vqdmlsl"),
            desc_neon(ArmFullOpcode::Vqdmulh, "vqdmulh"),
            desc_neon(ArmFullOpcode::Vqdmull, "vqdmull"),
            desc_neon(ArmFullOpcode::Vqmovn, "vqmovn"),
            desc_neon(ArmFullOpcode::Vqmovun, "vqmovun"),
            desc_neon(ArmFullOpcode::Vqneg, "vqneg"),
            desc_neon(ArmFullOpcode::Vqrdmulh, "vqrdmulh"),
            desc_neon(ArmFullOpcode::Vqrshl, "vqrshl"),
            desc_neon(ArmFullOpcode::Vqrshrn, "vqrshrn"),
            desc_neon(ArmFullOpcode::Vqrshrun, "vqrshrun"),
            desc_neon(ArmFullOpcode::Vqshl, "vqshl"),
            desc_neon(ArmFullOpcode::Vqshlu, "vqshlu"),
            desc_neon(ArmFullOpcode::Vqshrn, "vqshrn"),
            desc_neon(ArmFullOpcode::Vqshrun, "vqshrun"),
            desc_neon(ArmFullOpcode::Vqsub, "vqsub"),
            desc_neon(ArmFullOpcode::Vraddhn, "vraddhn"),
            desc_neon(ArmFullOpcode::Vrecpe, "vrecpe"),
            desc_neon(ArmFullOpcode::Vrecps, "vrecps"),
            desc_neon(ArmFullOpcode::Vrev16Neon, "vrev16"),
            desc_neon(ArmFullOpcode::Vrev32Neon, "vrev32"),
            desc_neon(ArmFullOpcode::Vrev64Neon, "vrev64"),
            desc_neon(ArmFullOpcode::Vrhadd, "vrhadd"),
            desc_neon(ArmFullOpcode::Vrshl, "vrshl"),
            desc_neon(ArmFullOpcode::Vrshr, "vrshr"),
            desc_neon(ArmFullOpcode::Vrshrn, "vrshrn"),
            desc_neon(ArmFullOpcode::Vrsqrte, "vrsqrte"),
            desc_neon(ArmFullOpcode::Vrsqrts, "vrsqrts"),
            desc_neon(ArmFullOpcode::Vrsra, "vrsra"),
            desc_neon(ArmFullOpcode::Vrsubhn, "vrsubhn"),
            desc_neon(ArmFullOpcode::Vshl, "vshl"),
            desc_neon(ArmFullOpcode::Vshll, "vshll"),
            desc_neon(ArmFullOpcode::Vshr, "vshr"),
            desc_neon(ArmFullOpcode::Vshrn, "vshrn"),
            desc_neon(ArmFullOpcode::Vsli, "vsli"),
            desc_neon(ArmFullOpcode::Vsqrt, "vsqrt"),
            desc_neon(ArmFullOpcode::Vsra, "vsra"),
            desc_neon(ArmFullOpcode::Vsri, "vsri"),
            desc_neon_store(ArmFullOpcode::Vst1, "vst1"),
            desc_neon_store(ArmFullOpcode::Vst2, "vst2"),
            desc_neon_store(ArmFullOpcode::Vst3, "vst3"),
            desc_neon_store(ArmFullOpcode::Vst4, "vst4"),
            desc_neon(ArmFullOpcode::Vsub, "vsub"),
            desc_neon(ArmFullOpcode::Vsubhn, "vsubhn"),
            desc_neon(ArmFullOpcode::Vsubl, "vsubl"),
            desc_neon(ArmFullOpcode::Vsubw, "vsubw"),
            desc_neon(ArmFullOpcode::Vswp, "vswp"),
            desc_neon(ArmFullOpcode::Vtbl, "vtbl"),
            desc_neon(ArmFullOpcode::Vtbx, "vtbx"),
            desc_neon(ArmFullOpcode::Vtrn, "vtrn"),
            desc_neon(ArmFullOpcode::Vtst, "vtst"),
            desc_neon(ArmFullOpcode::Vuzp, "vuzp"),
            desc_neon(ArmFullOpcode::Vzip, "vzip"),
            // System reg NEON
            desc(
                ArmFullOpcode::Vmrs,
                "vmrs",
                ArmFullOperandClass::SysReg,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            desc(
                ArmFullOpcode::Vmsr,
                "vmsr",
                ArmFullOperandClass::SysReg,
                false,
                true,
                false,
                true,
                false,
                false,
                false,
                true,
                false,
                false,
                4,
            ),
            // === AArch64 opcodes ===
            desc_a64(ArmFullOpcode::Csdb, "csdb", true),
            desc_a64(ArmFullOpcode::Pssbb, "pssbb", true),
            desc_a64(ArmFullOpcode::Ssbb, "ssbb", true),
            desc_a64(ArmFullOpcode::Eret, "eret", true),
            desc_a64(ArmFullOpcode::Drps, "drps", true),
            desc_a64(ArmFullOpcode::Dc, "dc", true),
            desc_a64(ArmFullOpcode::Ic, "ic", true),
            desc_a64(ArmFullOpcode::At, "at", true),
            desc_a64(ArmFullOpcode::Tlbi, "tlbi", true),
            desc_a64_ldst(ArmFullOpcode::Ldxp, "ldxp", true, false),
            desc_a64_ldst(ArmFullOpcode::Stxp, "stxp", true, true),
            desc_a64_ldst(ArmFullOpcode::Ldaxp, "ldaxp", true, false),
            desc_a64_ldst(ArmFullOpcode::Stlxp, "stlxp", true, true),
            desc_a64_ldst(ArmFullOpcode::Ldaxr, "ldaxr", true, false),
            desc_a64_ldst(ArmFullOpcode::Stlxr, "stlxr", true, true),
            desc_a64_ldst(ArmFullOpcode::Ldaxrb, "ldaxrb", true, false),
            desc_a64_ldst(ArmFullOpcode::Stlxrb, "stlxrb", true, true),
            desc_a64_ldst(ArmFullOpcode::Ldaxrh, "ldaxrh", true, false),
            desc_a64_ldst(ArmFullOpcode::Stlxrh, "stlxrh", true, true),
            desc_a64_atomic(ArmFullOpcode::Cas, "cas"),
            desc_a64_atomic(ArmFullOpcode::Casa, "casa"),
            desc_a64_atomic(ArmFullOpcode::Casl, "casl"),
            desc_a64_atomic(ArmFullOpcode::Casal, "casal"),
            desc_a64_atomic(ArmFullOpcode::Casb, "casb"),
            desc_a64_atomic(ArmFullOpcode::Casab, "casab"),
            desc_a64_atomic(ArmFullOpcode::Caslb, "caslb"),
            desc_a64_atomic(ArmFullOpcode::Casalb, "casalb"),
            desc_a64_atomic(ArmFullOpcode::Cash, "cash"),
            desc_a64_atomic(ArmFullOpcode::Casah, "casah"),
            desc_a64_atomic(ArmFullOpcode::Caslh, "caslh"),
            desc_a64_atomic(ArmFullOpcode::Casalh, "casalh"),
            desc_a64_atomic(ArmFullOpcode::Ldadd, "ldadd"),
            desc_a64_atomic(ArmFullOpcode::Ldadda, "ldadda"),
            desc_a64_atomic(ArmFullOpcode::Ldaddl, "ldaddl"),
            desc_a64_atomic(ArmFullOpcode::Ldaddal, "ldaddal"),
            desc_a64_atomic(ArmFullOpcode::Ldset, "ldset"),
            desc_a64_atomic(ArmFullOpcode::Ldsmax, "ldsmax"),
            desc_a64_atomic(ArmFullOpcode::Ldsmin, "ldsmin"),
            desc_a64_atomic(ArmFullOpcode::Ldumax, "ldumax"),
            desc_a64_atomic(ArmFullOpcode::Ldumin, "ldumin"),
            desc_a64_atomic(ArmFullOpcode::SwpAarch64, "swp"),
            desc_a64_ldst(ArmFullOpcode::Ldapr, "ldapr", true, false),
            desc_a64_ldst(ArmFullOpcode::Stlr, "stlr", false, true),
            // PAC
            desc_a64(ArmFullOpcode::Pacia, "pacia", false),
            desc_a64(ArmFullOpcode::Pacib, "pacib", false),
            desc_a64(ArmFullOpcode::Pacda, "pacda", false),
            desc_a64(ArmFullOpcode::Pacdb, "pacdb", false),
            desc_a64(ArmFullOpcode::Autia, "autia", false),
            desc_a64(ArmFullOpcode::Autib, "autib", false),
            desc_a64(ArmFullOpcode::Autda, "autda", false),
            desc_a64(ArmFullOpcode::Autdb, "autdb", false),
            desc_a64(ArmFullOpcode::Paciza, "paciza", false),
            desc_a64(ArmFullOpcode::Pacizb, "pacizb", false),
            desc_a64(ArmFullOpcode::Pacdza, "pacdza", false),
            desc_a64(ArmFullOpcode::Pacdzb, "pacdzb", false),
            desc_a64(ArmFullOpcode::Autiza, "autiza", false),
            desc_a64(ArmFullOpcode::Autizb, "autizb", false),
            desc_a64(ArmFullOpcode::Autdza, "autdza", false),
            desc_a64(ArmFullOpcode::Autdzb, "autdzb", false),
            desc_a64(ArmFullOpcode::Xpaci, "xpaci", false),
            desc_a64(ArmFullOpcode::Xpacd, "xpacd", false),
            // BTI
            desc_a64(ArmFullOpcode::Bti, "bti", true),
            desc_a64(ArmFullOpcode::Blraa, "blraa", false),
            desc_a64(ArmFullOpcode::Blrab, "blrab", false),
            desc_a64(ArmFullOpcode::Braa, "braa", false),
            desc_a64(ArmFullOpcode::Brab, "brab", false),
            desc_a64(ArmFullOpcode::Esb, "esb", true),
            desc_a64(ArmFullOpcode::Psb, "psb", true),
            // System reg
            desc_a64(ArmFullOpcode::MrsAarch64, "mrs", true),
            desc_a64(ArmFullOpcode::MsrAarch64, "msr", true),
            desc_a64(ArmFullOpcode::Sys, "sys", true),
            desc_a64(ArmFullOpcode::Sysl, "sysl", true),
            // CRC
            desc_a64_crypto(ArmFullOpcode::Crc32b, "crc32b"),
            desc_a64_crypto(ArmFullOpcode::Crc32h, "crc32h"),
            desc_a64_crypto(ArmFullOpcode::Crc32w, "crc32w"),
            desc_a64_crypto(ArmFullOpcode::Crc32x, "crc32x"),
            desc_a64_crypto(ArmFullOpcode::Crc32cb, "crc32cb"),
            desc_a64_crypto(ArmFullOpcode::Crc32ch, "crc32ch"),
            desc_a64_crypto(ArmFullOpcode::Crc32cw, "crc32cw"),
            desc_a64_crypto(ArmFullOpcode::Crc32cx, "crc32cx"),
            // AES
            desc_a64_crypto(ArmFullOpcode::Aesd, "aesd"),
            desc_a64_crypto(ArmFullOpcode::Aese, "aese"),
            desc_a64_crypto(ArmFullOpcode::Aesimc, "aesimc"),
            desc_a64_crypto(ArmFullOpcode::Aesmc, "aesmc"),
            // SHA1
            desc_a64_crypto(ArmFullOpcode::Sha1h, "sha1h"),
            desc_a64_crypto(ArmFullOpcode::Sha1su0, "sha1su0"),
            desc_a64_crypto(ArmFullOpcode::Sha1su1, "sha1su1"),
            // SHA256
            desc_a64_crypto(ArmFullOpcode::Sha256su0, "sha256su0"),
            desc_a64_crypto(ArmFullOpcode::Sha256su1, "sha256su1"),
            desc_a64_crypto(ArmFullOpcode::Sha256h, "sha256h"),
            desc_a64_crypto(ArmFullOpcode::Sha256h2, "sha256h2"),
            // SHA512
            desc_a64_crypto(ArmFullOpcode::Sha512h, "sha512h"),
            desc_a64_crypto(ArmFullOpcode::Sha512h2, "sha512h2"),
            desc_a64_crypto(ArmFullOpcode::Sha512su0, "sha512su0"),
            desc_a64_crypto(ArmFullOpcode::Sha512su1, "sha512su1"),
            // SM3
            desc_a64_crypto(ArmFullOpcode::Sm3ss1, "sm3ss1"),
            desc_a64_crypto(ArmFullOpcode::Sm3tt1a, "sm3tt1a"),
            desc_a64_crypto(ArmFullOpcode::Sm3tt1b, "sm3tt1b"),
            desc_a64_crypto(ArmFullOpcode::Sm3tt2a, "sm3tt2a"),
            desc_a64_crypto(ArmFullOpcode::Sm3tt2b, "sm3tt2b"),
            desc_a64_crypto(ArmFullOpcode::Sm3partw1, "sm3partw1"),
            desc_a64_crypto(ArmFullOpcode::Sm3partw2, "sm3partw2"),
            // SM4
            desc_a64_crypto(ArmFullOpcode::Sm4e, "sm4e"),
            desc_a64_crypto(ArmFullOpcode::Sm4ekey, "sm4ekey"),
            // SHA1 A64 extra
            desc_a64_crypto(ArmFullOpcode::Sha1c, "sha1c"),
            desc_a64_crypto(ArmFullOpcode::Sha1p, "sha1p"),
            desc_a64_crypto(ArmFullOpcode::Sha1m, "sha1m"),
            desc_a64_crypto(ArmFullOpcode::Sha1hA64, "sha1h"),
            // Bitfield
            desc_a64(ArmFullOpcode::Bc, "bc", false),
            desc_a64(ArmFullOpcode::Bfc, "bfc", false),
            desc_a64(ArmFullOpcode::Bfi, "bfi", false),
            desc_a64(ArmFullOpcode::Bfxil, "bfxil", false),
            desc_a64(ArmFullOpcode::Ubfiz, "ubfiz", false),
            desc_a64(ArmFullOpcode::Sbfiz, "sbfiz", false),
            desc_a64(ArmFullOpcode::Ubfx, "ubfx", false),
            desc_a64(ArmFullOpcode::Sbfx, "sbfx", false),
            desc_a64(ArmFullOpcode::Extr, "extr", false),
            desc_a64(ArmFullOpcode::RorImm, "ror", false),
            desc_a64(ArmFullOpcode::RorV, "ror", false),
            // Conditional
            desc_a64(ArmFullOpcode::Ccmn, "ccmn", false),
            desc_a64(ArmFullOpcode::Ccmp, "ccmp", false),
            desc_a64(ArmFullOpcode::Csinc, "csinc", false),
            desc_a64(ArmFullOpcode::Csel, "csel", false),
            desc_a64_fp(ArmFullOpcode::Fcsel, "fcsel"),
            desc_a64_fp(ArmFullOpcode::Fmadd, "fmadd"),
            desc_a64_fp(ArmFullOpcode::Fmsub, "fmsub"),
            desc_a64_fp(ArmFullOpcode::Fnmadd, "fnmadd"),
            desc_a64_fp(ArmFullOpcode::Fnmsub, "fnmsub"),
            desc_a64_fp(ArmFullOpcode::Frintn, "frintn"),
            desc_a64_fp(ArmFullOpcode::Frintp, "frintp"),
            desc_a64_fp(ArmFullOpcode::Frintm, "frintm"),
            desc_a64_fp(ArmFullOpcode::Frintz, "frintz"),
            desc_a64_fp(ArmFullOpcode::Frinta, "frinta"),
            desc_a64_fp(ArmFullOpcode::Frintx, "frintx"),
            desc_a64_fp(ArmFullOpcode::Frinti, "frinti"),
            desc_a64_fp(ArmFullOpcode::Scvtf, "scvtf"),
            desc_a64_fp(ArmFullOpcode::Ucvtf, "ucvtf"),
            desc_a64_fp(ArmFullOpcode::Fcvtzs, "fcvtzs"),
            desc_a64_fp(ArmFullOpcode::Fcvtzu, "fcvtzu"),
            desc_a64_fp(ArmFullOpcode::Fcvtas, "fcvtas"),
            desc_a64_fp(ArmFullOpcode::Fcvtaus, "fcvtau"),
            desc_a64_fp(ArmFullOpcode::Fcvtps, "fcvtps"),
            desc_a64_fp(ArmFullOpcode::Fcvtpu, "fcvtpu"),
            desc_a64_fp(ArmFullOpcode::Fcvtms, "fcvtms"),
            desc_a64_fp(ArmFullOpcode::Fcvtmu, "fcvtmu"),
            desc_a64_fp(ArmFullOpcode::FmovAarch64, "fmov"),
            desc_a64_fp(ArmFullOpcode::Fmax, "fmax"),
            desc_a64_fp(ArmFullOpcode::Fmin, "fmin"),
            desc_a64_fp(ArmFullOpcode::Fmaxnm, "fmaxnm"),
            desc_a64_fp(ArmFullOpcode::Fminnm, "fminnm"),
            // Integer
            desc_a64(ArmFullOpcode::AbsAarch64, "abs", false),
            desc_a64(ArmFullOpcode::NegAarch64, "neg", false),
            desc_a64(ArmFullOpcode::RbitAarch64, "rbit", false),
            desc_a64(ArmFullOpcode::RevAarch64, "rev", false),
            desc_a64(ArmFullOpcode::Rev16Aarch64, "rev16", false),
            desc_a64(ArmFullOpcode::Rev32Aarch64, "rev32", false),
            desc_a64(ArmFullOpcode::ClzAarch64, "clz", false),
            desc_a64(ArmFullOpcode::Cls, "cls", false),
            desc_a64(ArmFullOpcode::SdivAarch64, "sdiv", false),
            desc_a64(ArmFullOpcode::UdivAarch64, "udiv", false),
            desc_a64(ArmFullOpcode::Madd, "madd", false),
            desc_a64(ArmFullOpcode::Msub, "msub", false),
            desc_a64(ArmFullOpcode::Mneg, "mneg", false),
            desc_a64(ArmFullOpcode::Smulh, "smulh", false),
            desc_a64(ArmFullOpcode::Umulh, "umulh", false),
            desc_a64(ArmFullOpcode::AddsAarch64, "adds", false),
            desc_a64(ArmFullOpcode::SubsAarch64, "subs", false),
            desc_a64(ArmFullOpcode::Adcs, "adcs", false),
            desc_a64(ArmFullOpcode::Sbcs, "sbcs", false),
            desc_a64(ArmFullOpcode::Ands, "ands", false),
            desc_a64(ArmFullOpcode::Bics, "bics", false),
            desc_a64(ArmFullOpcode::Negs, "negs", false),
            desc_a64(ArmFullOpcode::Ngcs, "ngcs", false),
            desc_a64(ArmFullOpcode::Lslv, "lslv", false),
            desc_a64(ArmFullOpcode::Lsrv, "lsrv", false),
            desc_a64(ArmFullOpcode::Asrv, "asrv", false),
            desc_a64(ArmFullOpcode::Rorv, "rorv", false),
            desc_a64(ArmFullOpcode::Prfm, "prfm", false),
            desc_a64(ArmFullOpcode::Prfum, "prfum", false),
        ];

        let mut mnemonic_map = HashMap::new();
        for (i, d) in descriptors.iter().enumerate() {
            mnemonic_map.insert(d.mnemonic.to_string(), i);
        }

        ArmFullInstrInfo {
            descriptors,
            mnemonic_map,
        }
    }

    /// Look up a descriptor by opcode.
    pub fn get(&self, opcode: ArmFullOpcode) -> Option<&ArmFullInstrDesc> {
        self.descriptors.iter().find(|d| d.opcode == opcode)
    }

    /// Look up a descriptor by mnemonic string.
    pub fn find_by_mnemonic(&self, mnemonic: &str) -> Option<&ArmFullInstrDesc> {
        self.mnemonic_map
            .get(mnemonic)
            .and_then(|&idx| self.descriptors.get(idx))
    }

    /// Return the total number of descriptors.
    pub fn len(&self) -> usize {
        self.descriptors.len()
    }

    /// Return true if the table is empty.
    pub fn is_empty(&self) -> bool {
        self.descriptors.is_empty()
    }

    /// Get all AArch64-only opcodes.
    pub fn get_aarch64_opcodes(&self) -> Vec<ArmFullOpcode> {
        self.descriptors
            .iter()
            .filter(|d| d.is_aarch64 && !d.is_arm32)
            .map(|d| d.opcode)
            .collect()
    }

    /// Get all ARM32-only opcodes.
    pub fn get_arm32_opcodes(&self) -> Vec<ArmFullOpcode> {
        self.descriptors
            .iter()
            .filter(|d| !d.is_aarch64 && d.is_arm32)
            .map(|d| d.opcode)
            .collect()
    }

    /// Get all SIMD/NEON opcodes.
    pub fn get_simd_opcodes(&self) -> Vec<ArmFullOpcode> {
        self.descriptors
            .iter()
            .filter(|d| d.is_simd)
            .map(|d| d.opcode)
            .collect()
    }

    /// Get all crypto opcodes.
    pub fn get_crypto_opcodes(&self) -> Vec<ArmFullOpcode> {
        self.descriptors
            .iter()
            .filter(|d| d.is_crypto)
            .map(|d| d.opcode)
            .collect()
    }

    /// Get all atomic opcodes.
    pub fn get_atomic_opcodes(&self) -> Vec<ArmFullOpcode> {
        self.descriptors
            .iter()
            .filter(|d| d.is_atomic)
            .map(|d| d.opcode)
            .collect()
    }

    /// Check if an opcode is a barrier instruction.
    pub fn is_barrier(&self, opcode: ArmFullOpcode) -> bool {
        self.get(opcode).map_or(false, |d| d.is_barrier)
    }

    /// Check if an opcode has side effects.
    pub fn has_side_effects(&self, opcode: ArmFullOpcode) -> bool {
        self.get(opcode).map_or(false, |d| d.has_side_effects)
    }

    /// Iterate over all descriptors.
    pub fn iter(&self) -> impl Iterator<Item = &ArmFullInstrDesc> {
        self.descriptors.iter()
    }

    /// Get the mnemonic for an opcode.
    pub fn get_mnemonic(&self, opcode: ArmFullOpcode) -> Option<&'static str> {
        self.get(opcode).map(|d| d.mnemonic)
    }
}

impl Default for ArmFullInstrInfo {
    fn default() -> Self {
        Self::new()
    }
}

// --- Helper constructors ---

fn desc(
    opcode: ArmFullOpcode,
    mnemonic: &'static str,
    operands: ArmFullOperandClass,
    is_aarch64: bool,
    is_arm32: bool,
    is_thumb: bool,
    is_simd: bool,
    is_crypto: bool,
    is_atomic: bool,
    is_barrier: bool,
    has_side_effects: bool,
    may_load: bool,
    may_store: bool,
    encoding_length: u8,
) -> ArmFullInstrDesc {
    ArmFullInstrDesc {
        opcode,
        mnemonic,
        operands,
        is_aarch64,
        is_arm32,
        is_thumb,
        is_simd,
        is_crypto,
        is_atomic,
        is_barrier,
        has_side_effects,
        may_load,
        may_store,
        encoding_length,
    }
}

fn desc_neon(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Reg3,
        false,
        true,
        false,
        true,
        false,
        false,
        false,
        false,
        false,
        false,
        4,
    )
}

fn desc_neon_load_store(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Mem,
        false,
        true,
        false,
        true,
        false,
        false,
        false,
        false,
        true,
        false,
        4,
    )
}

fn desc_neon_store(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Mem,
        false,
        true,
        false,
        true,
        false,
        false,
        false,
        false,
        false,
        true,
        4,
    )
}

fn desc_a64(
    opcode: ArmFullOpcode,
    mnemonic: &'static str,
    has_side_effects: bool,
) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Reg3,
        true,
        false,
        false,
        false,
        false,
        false,
        false,
        has_side_effects,
        false,
        false,
        4,
    )
}

fn desc_a64_ldst(
    opcode: ArmFullOpcode,
    mnemonic: &'static str,
    may_load: bool,
    may_store: bool,
) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Mem,
        true,
        false,
        false,
        false,
        false,
        false,
        false,
        false,
        may_load,
        may_store,
        4,
    )
}

fn desc_a64_atomic(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Mem,
        true,
        false,
        false,
        false,
        false,
        true,
        false,
        true,
        true,
        true,
        4,
    )
}

fn desc_a64_crypto(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Reg3,
        true,
        false,
        false,
        false,
        true,
        false,
        false,
        false,
        false,
        false,
        4,
    )
}

fn desc_a64_fp(opcode: ArmFullOpcode, mnemonic: &'static str) -> ArmFullInstrDesc {
    desc(
        opcode,
        mnemonic,
        ArmFullOperandClass::Reg3,
        true,
        false,
        false,
        false,
        false,
        false,
        false,
        false,
        false,
        false,
        4,
    )
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    fn test_table_not_empty() {
        let info = ArmFullInstrInfo::new();
        assert!(!info.is_empty());
        assert!(
            info.len() > 300,
            "expected >300 opcodes, got {}",
            info.len()
        );
    }

    #[test]
    fn test_get_sbc() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Sbc).unwrap();
        assert_eq!(d.mnemonic, "sbc");
        assert!(!d.is_aarch64);
        assert!(d.is_arm32);
    }

    #[test]
    fn test_get_cas() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Cas).unwrap();
        assert_eq!(d.mnemonic, "cas");
        assert!(d.is_aarch64);
        assert!(d.is_atomic);
    }

    #[test]
    fn test_find_by_mnemonic() {
        let info = ArmFullInstrInfo::new();
        let d = info.find_by_mnemonic("vadd").unwrap();
        assert_eq!(d.opcode, ArmFullOpcode::Vadd);
        assert!(d.is_simd);
    }

    #[test]
    fn test_find_by_mnemonic_not_found() {
        let info = ArmFullInstrInfo::new();
        assert!(info.find_by_mnemonic("nonexistent").is_none());
    }

    #[test]
    fn test_get_aarch64_opcodes() {
        let info = ArmFullInstrInfo::new();
        let a64 = info.get_aarch64_opcodes();
        assert!(
            a64.len() > 50,
            "expected >50 AArch64 opcodes, got {}",
            a64.len()
        );
        assert!(a64.contains(&ArmFullOpcode::Cas));
        assert!(a64.contains(&ArmFullOpcode::Crc32b));
    }

    #[test]
    fn test_get_arm32_opcodes() {
        let info = ArmFullInstrInfo::new();
        let a32 = info.get_arm32_opcodes();
        assert!(
            a32.len() > 100,
            "expected >100 ARM32 opcodes, got {}",
            a32.len()
        );
        assert!(a32.contains(&ArmFullOpcode::Sbc));
        assert!(a32.contains(&ArmFullOpcode::Vadd));
    }

    #[test]
    fn test_get_simd_opcodes() {
        let info = ArmFullInstrInfo::new();
        let simd = info.get_simd_opcodes();
        assert!(
            simd.len() > 60,
            "expected >60 SIMD opcodes, got {}",
            simd.len()
        );
        assert!(simd.contains(&ArmFullOpcode::Vadd));
        assert!(simd.contains(&ArmFullOpcode::Vqadd));
    }

    #[test]
    fn test_get_crypto_opcodes() {
        let info = ArmFullInstrInfo::new();
        let crypto = info.get_crypto_opcodes();
        assert!(
            crypto.len() > 10,
            "expected >10 crypto opcodes, got {}",
            crypto.len()
        );
        assert!(crypto.contains(&ArmFullOpcode::Aesd));
        assert!(crypto.contains(&ArmFullOpcode::Sha256h));
    }

    #[test]
    fn test_get_atomic_opcodes() {
        let info = ArmFullInstrInfo::new();
        let atomic = info.get_atomic_opcodes();
        assert!(
            atomic.len() > 10,
            "expected >10 atomic opcodes, got {}",
            atomic.len()
        );
        assert!(atomic.contains(&ArmFullOpcode::Cas));
        assert!(atomic.contains(&ArmFullOpcode::Ldadd));
    }

    #[test]
    fn test_is_barrier() {
        let info = ArmFullInstrInfo::new();
        assert!(info.is_barrier(ArmFullOpcode::Dmb));
        assert!(info.is_barrier(ArmFullOpcode::Dsb));
        assert!(info.is_barrier(ArmFullOpcode::Isb));
        assert!(!info.is_barrier(ArmFullOpcode::AddsAarch64));
    }

    #[test]
    fn test_has_side_effects() {
        let info = ArmFullInstrInfo::new();
        assert!(info.has_side_effects(ArmFullOpcode::Svc));
        assert!(info.has_side_effects(ArmFullOpcode::Hvc));
        assert!(info.has_side_effects(ArmFullOpcode::Dmb));
        assert!(!info.has_side_effects(ArmFullOpcode::Vadd));
    }

    #[test]
    fn test_neon_opcodes_have_simd_flag() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Vfma).unwrap();
        assert!(d.is_simd);
        let d = info.get(ArmFullOpcode::Vqrshl).unwrap();
        assert!(d.is_simd);
        let d = info.get(ArmFullOpcode::Vzip).unwrap();
        assert!(d.is_simd);
    }

    #[test]
    fn test_get_mnemonic() {
        let info = ArmFullInstrInfo::new();
        assert_eq!(info.get_mnemonic(ArmFullOpcode::Vfma), Some("vfma"));
        assert_eq!(info.get_mnemonic(ArmFullOpcode::Cas), Some("cas"));
        assert_eq!(info.get_mnemonic(ArmFullOpcode::Invalid), None);
    }

    #[test]
    fn test_pac_opcodes_are_aarch64() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Pacia).unwrap();
        assert!(d.is_aarch64);
        assert!(!d.is_arm32);
        let d = info.get(ArmFullOpcode::Autib).unwrap();
        assert!(d.is_aarch64);
    }

    #[test]
    fn test_exclusive_opcodes() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Ldrex).unwrap();
        assert!(d.may_load);
        assert!(!d.may_store);
        let d = info.get(ArmFullOpcode::Strex).unwrap();
        assert!(d.may_store);
        assert!(!d.may_load);
    }

    #[test]
    fn test_ldm_stm_variants() {
        let info = ArmFullInstrInfo::new();
        let variants = [
            ArmFullOpcode::Ldm,
            ArmFullOpcode::Ldmda,
            ArmFullOpcode::Ldmdb,
            ArmFullOpcode::Ldmib,
        ];
        for v in &variants {
            let d = info.get(*v).unwrap();
            assert!(d.may_load);
            assert!(!d.may_store);
        }
        let variants = [
            ArmFullOpcode::Stm,
            ArmFullOpcode::Stmda,
            ArmFullOpcode::Stmdb,
            ArmFullOpcode::Stmib,
        ];
        for v in &variants {
            let d = info.get(*v).unwrap();
            assert!(d.may_store);
            assert!(!d.may_load);
        }
    }

    #[test]
    fn test_dsp_simd_opcodes() {
        let info = ArmFullInstrInfo::new();
        let d = info.get(ArmFullOpcode::Uqadd8).unwrap();
        assert!(d.is_simd);
        assert!(d.is_arm32);
        let d = info.get(ArmFullOpcode::Sadd16).unwrap();
        assert!(d.is_simd);
    }

    #[test]
    fn test_iter_yields_all() {
        let info = ArmFullInstrInfo::new();
        let count = info.iter().count();
        assert_eq!(count, info.len());
    }

    #[test]
    fn test_vld_vst_are_load_store() {
        let info = ArmFullInstrInfo::new();
        for op in &[
            ArmFullOpcode::Vld1,
            ArmFullOpcode::Vld2,
            ArmFullOpcode::Vld3,
            ArmFullOpcode::Vld4,
        ] {
            let d = info.get(*op).unwrap();
            assert!(d.may_load, "{:?} should load", op);
        }
        for op in &[
            ArmFullOpcode::Vst1,
            ArmFullOpcode::Vst2,
            ArmFullOpcode::Vst3,
            ArmFullOpcode::Vst4,
        ] {
            let d = info.get(*op).unwrap();
            assert!(d.may_store, "{:?} should store", op);
        }
    }

    #[test]
    fn test_sha_variants() {
        let info = ArmFullInstrInfo::new();
        assert!(info.get(ArmFullOpcode::Sha1c).unwrap().is_crypto);
        assert!(info.get(ArmFullOpcode::Sha512h).unwrap().is_crypto);
        assert!(info.get(ArmFullOpcode::Sm3ss1).unwrap().is_crypto);
    }

    #[test]
    fn test_cas_variants() {
        let info = ArmFullInstrInfo::new();
        for op in &[
            ArmFullOpcode::Casb,
            ArmFullOpcode::Casab,
            ArmFullOpcode::Caslb,
            ArmFullOpcode::Casalb,
        ] {
            assert!(info.get(*op).unwrap().is_atomic);
        }
    }

    #[test]
    fn test_hint_opcodes() {
        let info = ArmFullInstrInfo::new();
        for op in &[
            ArmFullOpcode::Yield,
            ArmFullOpcode::Wfe,
            ArmFullOpcode::Wfi,
            ArmFullOpcode::Sev,
            ArmFullOpcode::Sevl,
        ] {
            assert!(info.get(*op).unwrap().has_side_effects);
        }
    }

    #[test]
    fn test_crc32_variants() {
        let info = ArmFullInstrInfo::new();
        let crcs = [
            ArmFullOpcode::Crc32b,
            ArmFullOpcode::Crc32h,
            ArmFullOpcode::Crc32w,
            ArmFullOpcode::Crc32x,
            ArmFullOpcode::Crc32cb,
            ArmFullOpcode::Crc32ch,
            ArmFullOpcode::Crc32cw,
            ArmFullOpcode::Crc32cx,
        ];
        for crc in &crcs {
            let d = info.get(*crc).unwrap();
            assert!(d.is_crypto);
            assert!(d.is_aarch64);
        }
    }
}