llvm-native-core 0.1.0

//! LLVM CodeGen — opcode-aware machine code generation framework.
//! Clean-room behavioral reconstruction. Phase 5 — LLVM.CODEGEN.1 Court.
//!
//! @llvm_behavior: The CodeGen framework lowers LLVM IR to machine code
//! through three stages:
//! 1. Instruction Selection: IR → MachineInstr (target-specific opcodes)
//! 2. Register Allocation: virtual registers → physical registers
//! 3. Assembly Printing: MachineInstr → assembly text
//!
//! The instruction selector now uses explicit IR opcodes for dispatch,
//! enabling correct lowering of all common IR instructions to X86-64.

use crate::mc_streamer::x86_opcodes;
use crate::opcode::Opcode;
use crate::value::{SubclassKind, Value, ValueRef};
use std::collections::{HashMap, HashSet};

/// A virtual register (SSA value in machine code).
pub type VirtReg = u32;
/// A physical register (actual CPU register).
pub type PhysReg = u32;

/// A machine instruction operand: register, immediate, label, or global symbol.
#[derive(Debug, Clone, PartialEq, Eq)]
pub enum MachineOperand {
    /// A virtual register operand (definition or use).
    Reg(VirtReg),
    /// A physical register operand.
    PhysReg(PhysReg),
    /// An immediate constant operand.
    Imm(i64),
    /// A label reference operand.
    Label(String),
    /// A global symbol reference operand.
    Global(String),
}

impl MachineOperand {
    // ------------------------------------------------------------------
    // Constructors (struct-era compatibility aliases)
    // ------------------------------------------------------------------

    pub fn new_reg(reg: VirtReg) -> Self {
        Self::Reg(reg)
    }
    pub fn new_phys_reg(reg: PhysReg) -> Self {
        Self::PhysReg(reg)
    }
    pub fn new_use(reg: u32) -> Self {
        Self::Reg(reg)
    }
    pub fn new_imm(imm: i64) -> Self {
        Self::Imm(imm)
    }
    pub fn new_label(label: &str) -> Self {
        Self::Label(label.to_string())
    }
    pub fn new_global(name: &str) -> Self {
        Self::Global(name.to_string())
    }

    // ------------------------------------------------------------------
    // Predicates (struct-era field-access compatibility)
    // ------------------------------------------------------------------

    /// Returns true when the operand is any kind of register (virtual or physical).
    pub fn is_reg(&self) -> bool {
        matches!(self, Self::Reg(_) | Self::PhysReg(_))
    }

    /// Returns true when the operand is an immediate constant.
    pub fn is_imm(&self) -> bool {
        matches!(self, Self::Imm(_))
    }

    /// Returns true when the operand is a label reference.
    pub fn is_label(&self) -> bool {
        matches!(self, Self::Label(_))
    }

    /// Returns true when the operand is a global symbol reference.
    pub fn is_global(&self) -> bool {
        matches!(self, Self::Global(_))
    }

    /// Returns true when this operand defines a register.
    /// For enum compatibility this is always true for register variants;
    /// callers that need precise def/use tracking should use position-based analysis.
    pub fn is_def(&self) -> bool {
        matches!(self, Self::Reg(_) | Self::PhysReg(_))
    }

    /// Returns true when this operand uses a register.
    /// For enum compatibility this is always true for register variants;
    /// callers that need precise def/use tracking should use position-based analysis.
    pub fn is_use(&self) -> bool {
        matches!(self, Self::Reg(_) | Self::PhysReg(_))
    }

    // ------------------------------------------------------------------
    // Value accessors (struct-era field-access compatibility)
    // ------------------------------------------------------------------

    /// Returns the register number for Reg or PhysReg variants, or 0 otherwise.
    pub fn reg(&self) -> u32 {
        match self {
            Self::Reg(r) | Self::PhysReg(r) => *r,
            _ => 0,
        }
    }

    /// Returns the register value if this is a register operand.
    pub fn reg_val(&self) -> Option<VirtReg> {
        match self {
            Self::Reg(r) | Self::PhysReg(r) => Some(*r),
            _ => None,
        }
    }

    /// Returns the immediate value for Imm variants, or 0 otherwise.
    pub fn imm_val(&self) -> i64 {
        match self {
            Self::Imm(i) => *i,
            _ => 0,
        }
    }

    /// Returns the label string for Label variants, or empty string otherwise.
    pub fn label_str(&self) -> &str {
        match self {
            Self::Label(l) => l.as_str(),
            _ => "",
        }
    }

    /// Returns the global symbol name for Global variants, or empty string otherwise.
    pub fn global_str(&self) -> &str {
        match self {
            Self::Global(g) => g.as_str(),
            _ => "",
        }
    }
}

/// A machine instruction with opcode and operands.
#[derive(Debug, Clone)]
pub struct MachineInstr {
    pub opcode: u32,
    pub operands: Vec<MachineOperand>,
    /// If this instruction defines a virtual register
    pub def: Option<VirtReg>,
    /// Operand size in bytes (0 = default 64-bit, 4 = 32-bit, etc.)
    pub size: u8,
}

impl MachineInstr {
    pub fn new(opcode: u32) -> Self {
        Self {
            opcode,
            operands: Vec::new(),
            def: None,
            size: 0,
        }
    }
    pub fn with_def(mut self, reg: VirtReg) -> Self {
        self.def = Some(reg);
        self
    }
    pub fn push_reg(&mut self, reg: VirtReg) {
        self.operands.push(MachineOperand::new_reg(reg));
    }
    pub fn push_imm(&mut self, imm: i64) {
        self.operands.push(MachineOperand::new_imm(imm));
    }
    pub fn push_label(&mut self, label: &str) {
        self.operands.push(MachineOperand::new_label(label));
    }
    /// Builder: attach instruction flags (for ISel and encoding).
    #[allow(dead_code)]
    pub fn with_flags(mut self, _flags: u32) -> Self {
        // Flags are stored for target-specific use; default no-op for base.
        self
    }
    /// Builder: set opcode.
    #[allow(dead_code)]
    pub fn with_opcode(mut self, opcode: u32) -> Self {
        self.opcode = opcode;
        self
    }
}

impl Default for MachineInstr {
    fn default() -> Self {
        Self::new(0)
    }
}

/// A machine basic block: list of MachineInstrs.
#[derive(Debug, Clone)]
pub struct MachineBasicBlock {
    pub id: usize,
    pub name: String,
    pub instructions: Vec<MachineInstr>,
    pub successors: Vec<usize>,
    pub predecessors: Vec<usize>,
    pub is_entry: bool,
}

impl Default for MachineBasicBlock {
    fn default() -> Self {
        Self {
            id: 0,
            name: String::new(),
            instructions: Vec::new(),
            successors: Vec::new(),
            predecessors: Vec::new(),
            is_entry: false,
        }
    }
}

impl MachineBasicBlock {
    pub fn new(id: usize) -> Self {
        Self {
            id,
            name: format!("bb{}", id),
            instructions: Vec::new(),
            successors: Vec::new(),
            predecessors: Vec::new(),
            is_entry: false,
        }
    }

    /// Create a basic block with an explicit name.
    pub fn new_named(id: usize, name: &str) -> Self {
        Self {
            id,
            name: name.to_string(),
            instructions: Vec::new(),
            successors: Vec::new(),
            predecessors: Vec::new(),
            is_entry: false,
        }
    }

    /// Create a basic block with just a name; other fields defaulted.
    pub fn with_name(name: String) -> Self {
        Self {
            id: 0,
            name,
            instructions: Vec::new(),
            successors: Vec::new(),
            predecessors: Vec::new(),
            is_entry: false,
        }
    }
}

/// Machine function: contains machine basic blocks.
#[derive(Debug, Clone)]
pub struct MachineFunction {
    pub name: String,
    pub blocks: Vec<MachineBasicBlock>,
    pub virt_reg_counter: u32,
    /// Byte-accurate stack offset counter for alloca instructions.
    /// Each alloca consumes its actual byte size (rounded up to 8 for
    /// alignment), and the running offset determines the address:
    ///   addr = rbp - offset
    /// This replaces the old (alloca_counter + 1) * 8 scheme, which gave
    /// every alloca a fixed 8-byte slot regardless of allocated type size.
    pub alloca_counter: i64,
    /// Total byte offset from rbp for the next alloca.  Accumulates downward.
    pub alloca_byte_offset: i64,

    // IR Alloca ValueId/vid -> positive byte offset from rbp.
    // Address is: rbp - offset.
    //
    // This lets LOAD/STORE of direct local allocas bypass the fragile
    // "alloca pointer lives in a vreg" path.
    pub alloca_offsets: std::collections::HashMap<usize, i64>,
}

impl MachineFunction {
    pub fn new(name: &str) -> Self {
        Self {
            name: name.into(),
            blocks: Vec::new(),
            virt_reg_counter: 0,
            alloca_counter: 0,
            alloca_byte_offset: 0,
            alloca_offsets: std::collections::HashMap::new(),
        }
    }
    pub fn new_vreg(&mut self) -> VirtReg {
        let r = self.virt_reg_counter;
        self.virt_reg_counter += 1;
        r
    }
    pub fn push_block(&mut self, bb: MachineBasicBlock) {
        self.blocks.push(bb);
    }
}

// ============================================================================
// Instruction Selector — Opcode-Aware
// ============================================================================

/// Maps IR instructions to X86-64 machine instructions using explicit opcodes.
pub struct InstructionSelector;

impl InstructionSelector {
    /// SysV x86-64 ABI argument registers for integer/pointer args.
    /// arg0 -> rdi (7), arg1 -> rsi (6), arg2 -> rdx (2),
    /// arg3 -> rcx (1), arg4 -> r8 (8), arg5 -> r9 (9).
    fn arg_index_to_abi_reg(idx: usize) -> Option<u32> {
        match idx {
            0 => Some(7), // rdi
            1 => Some(6), // rsi
            2 => Some(2), // rdx
            3 => Some(1), // rcx
            4 => Some(8), // r8
            5 => Some(9), // r9
            _ => None,    // stack args not yet supported
        }
    }

    /// Select machine instructions for a function's IR.
    pub fn select(mf: &mut MachineFunction, func: &ValueRef) {
        let f = func.borrow();
        let mut vreg_map: HashMap<usize, VirtReg> = HashMap::new();
        // arg_to_alloca_map was removed: load-forwarding from argument allocas
        // is incorrect when parameters are mutated (e.g., x++ in a loop).
        // See https://github.com/one/llvm-native/issues/NNN for details.

        // Phase 0: Find all Argument values used across all blocks and
        // assign vregs to them (ClangCodeGen path).
        // These appear as operands of instructions (e.g. Store arg, alloca).
        // We collect them in order of first occurrence which matches
        // parameter order (ClangCodeGen::compile_function creates them in a loop).
        let mut arg_vids: Vec<(usize, VirtReg, u32, bool, bool)> = Vec::new(); // (vid, vreg, bit_width, is_float, is_double)
        for block in &f.blocks {
            let ir_bb = block.borrow();
            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if !inst.is_instruction() {
                    if inst.is_argument() {
                        let vid = inst.vid as usize;
                        if !vreg_map.contains_key(&vid) {
                            let vr = mf.new_vreg();
                            vreg_map.insert(vid, vr);
                            let bw = inst.ty.integer_bit_width();
                            let is_fp = inst.ty.is_floating_point();
                            let is_double = inst.ty.is_double_ty();
                            arg_vids.push((vid, vr, bw, is_fp, is_double));
                        }
                    }
                    continue;
                }
                for operand in &inst.operands {
                    let op = operand.borrow();
                    if op.is_argument() {
                        let vid = op.vid as usize;
                        if !vreg_map.contains_key(&vid) {
                            let vr = mf.new_vreg();
                            vreg_map.insert(vid, vr);
                            let bw = op.ty.integer_bit_width();
                            let is_fp = op.ty.is_floating_point();
                            let is_double = op.ty.is_double_ty();
                            arg_vids.push((vid, vr, bw, is_fp, is_double));
                        }
                    }
                }
            }
        }

        // First pass: assign vregs to all IR values that produce results
        // Check f.operands (asm_parser convention)
        for op in &f.operands {
            let ir_bb = op.borrow();
            if ir_bb.is_basic_block() {
                for inst_val in &ir_bb.operands {
                    let inst = inst_val.borrow();
                    if inst.is_instruction() && !inst.ty.is_void() {
                        let vr = mf.new_vreg();
                        vreg_map.insert(inst.vid as usize, vr);
                    }
                }
            }
        }
        // Also check f.blocks (ClangCodeGen convention)
        for block in &f.blocks {
            let ir_bb = block.borrow();
            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if inst.is_instruction() && !inst.ty.is_void() {
                    if !vreg_map.contains_key(&(inst.vid as usize)) {
                        let vr = mf.new_vreg();
                        vreg_map.insert(inst.vid as usize, vr);
                    }
                }
            }
        }

        // Also ensure vregs exist for all instruction operands (not just defs).
        // This catches cases where a value is used as an operand of another
        // instruction (e.g. alloca pointer used in Store, Load, or Call)
        // but the operand's vid is stored separately and might not match
        // the defining instruction's vid.
        for block in &f.blocks {
            let ir_bb = block.borrow();
            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if inst.is_instruction() {
                    for op in &inst.operands {
                        if !op.borrow().is_constant() && !op.borrow().is_function() {
                            let op_vid = op.borrow().vid as usize;
                            if !vreg_map.contains_key(&op_vid) {
                                let vr = mf.new_vreg();
                                vreg_map.insert(op_vid, vr);
                            }
                        }
                    }
                }
            }
        }

        // Pre-scan: collect phi instructions for lowering
        // (phi_vreg, [(input_vreg_or_const, input_value, pred_block_name)])
        // Where input_vreg_or_const is Some(vreg) for register inputs
        // or None for constant inputs (input_value holds the constant).
        let mut phi_list: Vec<(VirtReg, Vec<(Option<VirtReg>, i64, String)>)> = Vec::new();

        for block in &f.blocks {
            let ir_bb = block.borrow();
            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if !inst.is_instruction() {
                    continue;
                }
                if inst.get_opcode() == Some(Opcode::Phi) {
                    let phi_vr = vreg_map.get(&(inst.vid as usize)).copied();
                    if let Some(pvr) = phi_vr {
                        let mut inputs = Vec::new();
                        // Phi operands are pairs: (value, predecessor_block)
                        // Even indices are values, odd indices are blocks
                        let mut i = 0;
                        while i + 1 < inst.operands.len() {
                            let val = inst.operands[i].borrow();
                            let block_name = inst.operands[i + 1].borrow().name.clone();
                            if let Some(&vr) = vreg_map.get(&(val.vid as usize)) {
                                // Register input
                                inputs.push((Some(vr), 0, block_name));
                            } else if val.is_constant() {
                                // Constant input: parse the value from name
                                let imm_val: i64 = val.name.parse().unwrap_or(0);
                                inputs.push((None, imm_val, block_name));
                            }
                            i += 2;
                        }
                        if !inputs.is_empty() {
                            phi_list.push((pvr, inputs));
                        }
                    }
                }
            }
        }

        // Pre-scan: check for allocas and calls to determine if we need
        // a stack frame. When both allocas and calls are present, we must
        // adjust RSP to prevent callee pushes from clobbering alloca data.
        let mut has_alloca = false;
        let mut has_call = false;
        let mut max_alloca_vid: usize = 0;

        // Scan f.operands (asm_parser convention)
        for op in &f.operands {
            let ir_bb = op.borrow();
            if ir_bb.is_basic_block() {
                for inst_val in &ir_bb.operands {
                    let inst = inst_val.borrow();
                    if !inst.is_instruction() {
                        continue;
                    }
                    match inst.get_opcode() {
                        Some(Opcode::Alloca) => {
                            has_alloca = true;
                            let vid = inst.vid as usize;
                            if vid > max_alloca_vid {
                                max_alloca_vid = vid;
                            }
                        }
                        Some(Opcode::Call) => has_call = true,
                        _ => {}
                    }
                }
            }
        }

        // Scan f.blocks (ClangCodeGen convention)
        for block in &f.blocks {
            let ir_bb = block.borrow();
            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if !inst.is_instruction() {
                    continue;
                }
                match inst.get_opcode() {
                    Some(Opcode::Alloca) => {
                        has_alloca = true;
                        let vid = inst.vid as usize;
                        if vid > max_alloca_vid {
                            max_alloca_vid = vid;
                        }
                    }
                    Some(Opcode::Call) => has_call = true,
                    _ => {}
                }
            }
        }

        // Total stack size for `sub rsp, N` in the prologue.
        // The pipeline also computes frame_size from actual alloca sizes
        // and spill depth, so this is a fallback for the asm_parser path.
        let total_stack_size: Option<i64> = if has_alloca && has_call {
            let mut sz = (max_alloca_vid as i64 + 1) * 8 + 8;
            if sz % 16 == 0 {
                sz += 8;
            }
            if sz > 0 {
                Some(sz)
            } else {
                None
            }
        } else {
            None
        };
        // Dummy alloca_offsets: empty = use vid-based fallback in Alloca lowering.
        let alloca_offsets: HashMap<usize, i64> = HashMap::new();

        // Second pass: emit machine instructions
        // Check f.operands first (asm_parser), then f.blocks (ClangCodeGen)
        for op in &f.operands {
            let ir_bb = op.borrow();
            if !ir_bb.is_basic_block() {
                continue;
            }

            let mut mbb = MachineBasicBlock {
                name: ir_bb.name.clone(),
                instructions: Vec::new(),
                successors: Vec::new(),
                ..Default::default()
            };

            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if !inst.is_instruction() {
                    continue;
                }

                Self::select_ir_instruction(&mut mbb, &inst, &mut vreg_map, mf, &alloca_offsets);
            }

            mf.push_block(mbb);
        }

        // Also process f.blocks (ClangCodeGen convention)
        for (block_idx, block) in f.blocks.iter().enumerate() {
            let ir_bb = block.borrow();
            let mut mbb = MachineBasicBlock {
                name: ir_bb.name.clone(),
                instructions: Vec::new(),
                successors: Vec::new(),
                ..Default::default()
            };

            // For the entry block (first block), emit MOV from ABI register to
            // argument vreg for each function argument.
            // SysV x86-64 ABI:
            //   Integer args: rdi(7), rsi(6), rdx(2), rcx(1), r8(8), r9(9)
            //   Float args: xmm0(64), xmm1(65), xmm2(66), xmm3(67), xmm4(68), xmm5(69), xmm6(70), xmm7(71)
            if block_idx == 0 {
                // SysV x86-64 ABI: separate counters for int and float arg registers.
                let mut fp_arg_idx = 0usize;
                for (arg_idx, &(arg_vid, arg_vr, bw, is_fp, is_double_arg)) in
                    arg_vids.iter().enumerate()
                {
                    if is_fp {
                        if fp_arg_idx < 8 {
                            let xmm_reg = 64 + fp_arg_idx as u32;
                            // Use MOVD (XMM→GPR) to transfer float bits from XMM
                            // parameter register to a GPR vreg. This avoids the
                            // register-class confusion that happens when MOVSS
                            // (XMM↔XMM) is used: the vreg gets classified as XMM
                            // but is then used in GPR integer ops via BitCast.
                            let op = if is_double_arg {
                                x86_opcodes::MOVQ_FROM_XMM
                            } else {
                                x86_opcodes::MOVD_FROM_XMM
                            };
                            let mut mi = MachineInstr::new(op);
                            mi.operands.push(MachineOperand::PhysReg(xmm_reg)); // XMM src
                            mi.push_reg(arg_vr); // GPR dst
                            mbb.instructions.push(mi);
                            fp_arg_idx += 1;
                        }
                    } else if let Some(abi_reg) = Self::arg_index_to_abi_reg(arg_idx) {
                        if bw == 8 || bw == 32 || bw == 1 {
                            // i8, i32, or i1: use 32-bit MOV (zero-extends to 64-bit on x86-64).
                            // For i8 (char), the ABI passes the value in a 32-bit register with
                            // upper bits undefined; copying 32 bits preserves the valid byte.
                            let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(arg_vr);
                            mi.size = 4;
                            mi.operands.push(MachineOperand::PhysReg(abi_reg));
                            mbb.instructions.push(mi);
                        } else if bw == 64 || bw == 0 {
                            // 64-bit integer or pointer (bw==0 for non-integer types):
                            // plain 64-bit MOV, no sign-extension.
                            let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(arg_vr);
                            mi.size = 0;
                            mi.operands.push(MachineOperand::PhysReg(abi_reg));
                            mbb.instructions.push(mi);
                        } else {
                            // Fallback: MOVSXD (sign-extend 32-bit arg to 64-bit)
                            let mut mi = MachineInstr::new(x86_opcodes::MOVSXD).with_def(arg_vr);
                            mi.operands.push(MachineOperand::PhysReg(abi_reg));
                            mbb.instructions.push(mi);
                        }
                    }
                }
            }

            for inst_val in &ir_bb.operands {
                let inst = inst_val.borrow();
                if !inst.is_instruction() {
                    continue;
                }
                // Use the same instruction selection logic
                Self::select_ir_instruction(&mut mbb, &inst, &mut vreg_map, mf, &alloca_offsets);
            }
            mf.push_block(mbb);
        }

        // NOTE: Stack frame allocation (`sub rsp, <size>`) is now
        // handled by the prologue insertion in the E2E pipeline
        // (clang_x86_e2e_pipeline_full.rs), which runs after register
        // allocation and knows the exact spill slot footprint.
        // The old per-function `sub rsp` here was removed to avoid
        // double-allocating when both alloca safety and spill slots
        // need space.

        // === Phi lowering: insert MOVs in predecessor blocks ===
        // Build a map: block_name -> block_index
        let block_idx_map: std::collections::HashMap<String, usize> = mf
            .blocks
            .iter()
            .enumerate()
            .map(|(i, b)| (b.name.clone(), i))
            .collect();

        for (phi_vr, ref inputs) in &phi_list {
            for &(ref input_vr, imm_val, ref pred_name) in inputs {
                if let Some(&pred_idx) = block_idx_map.get(pred_name.as_str()) {
                    let pred_block = &mut mf.blocks[pred_idx];
                    // Insert a MOV before the terminator (last instruction)
                    let insert_pos = if pred_block.instructions.is_empty() {
                        0
                    } else {
                        // Insert before the last instruction (which should be a branch)
                        pred_block.instructions.len() - 1
                    };
                    let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(*phi_vr);
                    mov.size = 4; // 32-bit move
                    if let Some(vr) = input_vr {
                        // Register input: mov phi_vr, input_vr
                        mov.push_reg(*vr);
                    } else {
                        // Constant input: mov phi_vr, imm_val
                        mov.push_imm(imm_val);
                    }
                    pred_block.instructions.insert(insert_pos, mov);
                }
            }
        }

        // NOTE: Stack frame teardown is intentionally NOT inserted here.
        // The pipeline's epilogue insertion (in clang_x86_e2e_pipeline_full.rs)
        // adds `mov rsp, rbp; pop rbp` before each RET, which correctly restores
        // RSP by relying on the frame pointer. Since `sub rsp, frame_size` is
        // emitted after `mov rbp, rsp` in the entry block, the `mov rsp, rbp`
        // epilogue effectively deallocates the stack space.
        //
        // Do NOT insert `add rsp, frame_size` here — it would conflict with the
        // pipeline's epilogue insertion order and end up AFTER `pop rbp`,
        // corrupting the return address.
    }

    /// Shared instruction selection: emits machine instructions for a single
    /// IR instruction. Used by both f.operands (asm_parser) and f.blocks
    /// (ClangCodeGen) paths to ensure identical lowering.
    fn select_ir_instruction(
        mbb: &mut MachineBasicBlock,
        inst: &std::cell::Ref<'_, Value>,
        vreg_map: &mut HashMap<usize, VirtReg>,
        mf: &mut MachineFunction,
        alloca_offsets: &HashMap<usize, i64>,
    ) {
        if mf.name.contains("__divXf3__") && inst.get_opcode() == Some(Opcode::AShr) {
            let rhs = inst.operands.get(1).map(|o| o.borrow().name.clone());
            eprintln!("ASHR_TRACE vid={} ty={:?} rhs={:?}", inst.vid, inst.ty, rhs);
        }
        let opcode = inst.get_opcode();
        let num_ops = inst.operands.len();

        match opcode {
            // === Terminators ===
            Some(Opcode::Ret) => {
                if num_ops == 0 {
                    // ret void
                    mbb.instructions.push(MachineInstr::new(x86_opcodes::RET));
                } else {
                    // ret <val> — move return value to rax (integer) or xmm0 (float), then ret
                    let val = &inst.operands[0];
                    let val_vid = val.borrow().vid as usize;
                    let ret_ty = val.borrow().ty.clone();
                    let ret_bw = ret_ty.integer_bit_width();
                    // For pointer return types, force 64-bit (size=0).
                    // integer_bit_width() returns 0 for pointers, which maps
                    // to size=0 in the fallthrough, producing a 64-bit MOV to RAX.
                    let size = if ret_bw == 32 || ret_bw == 1 {
                        4
                    } else if ret_ty.is_pointer() {
                        // void* return: ensure 64-bit MOV (rax = full 64-bit value)
                        eprintln!(
                            "ISEL_RET_PTR: func={} ret_ty=pointer size=0 (64-bit)",
                            mf.name
                        );
                        0
                    } else if ret_bw == 64 || ret_bw == 0 {
                        0
                    } else {
                        0
                    };
                    let is_fp_ret = ret_ty.is_floating_point();
                    if let Some(&vr) = vreg_map.get(&val_vid) {
                        if is_fp_ret {
                            // Float/double return: use MOVD/MOVQ to transfer from
                            // GPR (where the float bit pattern lives) to XMM0.
                            let is_double = ret_ty.is_double_ty();
                            let mut mi = MachineInstr::new(if is_double {
                                x86_opcodes::MOVQ
                            } else {
                                x86_opcodes::MOVD
                            });
                            mi.push_reg(vr); // operand[0] = GPR src (holds result bits)
                            mi.operands.push(MachineOperand::PhysReg(64)); // operand[1] = XMM dst = xmm0
                            mbb.instructions.push(mi);
                        } else {
                            // Integer/pointer return: move result to rax
                            let mut mi = MachineInstr::new(x86_opcodes::MOV);
                            mi.operands.push(MachineOperand::PhysReg(0)); // rax
                            mi.push_reg(vr);
                            mi.size = size;
                            mbb.instructions.push(mi);
                        }
                    } else if val.borrow().is_constant() {
                        if is_fp_ret {
                            let is_double = ret_ty.is_double_ty();
                            // FP constant return: load constant into rax, then MOVD to xmm0
                            let imm_val: i64 = val.borrow().name.parse().unwrap_or(0);
                            let mut mov = MachineInstr::new(x86_opcodes::MOV);
                            mov.operands.push(MachineOperand::PhysReg(0)); // rax
                            mov.push_imm(imm_val);
                            mov.size = if is_double { 0u8 } else { 4u8 };
                            mbb.instructions.push(mov);
                            let mut movd = MachineInstr::new(if is_double {
                                x86_opcodes::MOVQ
                            } else {
                                x86_opcodes::MOVD
                            });
                            movd.operands.push(MachineOperand::PhysReg(0)); // rax (GPR src)
                            movd.operands.push(MachineOperand::PhysReg(64)); // xmm0 (XMM dst)
                            mbb.instructions.push(movd);
                        } else {
                            // Integer constant return: mov immediate to eax
                            let imm_val: i64 = val.borrow().name.parse().unwrap_or(0);
                            let mut mi = MachineInstr::new(x86_opcodes::MOV);
                            mi.operands.push(MachineOperand::PhysReg(0)); // rax
                            mi.push_imm(imm_val);
                            mi.size = size;
                            mbb.instructions.push(mi);
                        }
                    }
                    mbb.instructions.push(MachineInstr::new(x86_opcodes::RET));
                }
            }

            Some(Opcode::Br) => {
                if num_ops == 1 {
                    // Unconditional branch
                    let dest = inst.operands[0].borrow().name.clone();
                    mbb.successors.push(0);
                    let mut mi = MachineInstr::new(x86_opcodes::JMP);
                    mi.push_label(&dest);
                    mbb.instructions.push(mi);
                } else if num_ops == 3 {
                    // Conditional branch: cond, true_block, false_block
                    let cond_vid = inst.operands[0].borrow().vid as usize;
                    let t_label = inst.operands[1].borrow().name.clone();
                    let f_label = inst.operands[2].borrow().name.clone();
                    mbb.successors.push(0);
                    mbb.successors.push(0);

                    // Compare condition with 0
                    if let Some(&cond_vr) = vreg_map.get(&cond_vid) {
                        let mut cmp = MachineInstr::new(x86_opcodes::CMP);
                        cmp.push_reg(cond_vr);
                        cmp.push_imm(0);
                        mbb.instructions.push(cmp);
                    }
                    // Jump if not equal (branch taken path)
                    let mut jne = MachineInstr::new(x86_opcodes::JNE);
                    jne.push_label(&t_label);
                    mbb.instructions.push(jne);
                    // Fall through to false block
                    let mut jmp = MachineInstr::new(x86_opcodes::JMP);
                    jmp.push_label(&f_label);
                    mbb.instructions.push(jmp);
                }
            }

            Some(Opcode::Unreachable) => {
                // ud2 or nothing
            }

            // === Multiplication (special case: MUL uses implicit EAX) ===
            Some(Opcode::Mul) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let op0_vid = inst.operands[0].borrow().vid as usize;
                let op1_vid = inst.operands[1].borrow().vid as usize;
                let is_64bit = inst.ty.integer_bit_width() == 64;
                let mul_size: u8 = if is_64bit { 0 } else { 4 };

                if let Some(def) = def_vr {
                    let src0_vr = if let Some(vr) = vreg_map.get(&op0_vid).copied() {
                        Some(vr)
                    } else if op0_vid > 0 {
                        let vr = mf.new_vreg();
                        let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                        mov.size = mul_size;
                        mov.push_imm(imm_val);
                        mbb.instructions.push(mov);
                        Some(vr)
                    } else {
                        None
                    };
                    let src1_vr = if let Some(vr) = vreg_map.get(&op1_vid).copied() {
                        Some(vr)
                    } else if op1_vid > 0 {
                        let vr = mf.new_vreg();
                        let imm_val: i64 = inst.operands[1].borrow().name.parse().unwrap_or(0);
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                        mov.size = mul_size;
                        mov.push_imm(imm_val);
                        mbb.instructions.push(mov);
                        Some(vr)
                    } else {
                        None
                    };
                    // Both operands resolved as constants? Constant-fold at ISel time.
                    let op0_is_const = inst.operands[0].borrow().is_constant();
                    let op1_is_const = inst.operands[1].borrow().is_constant();
                    if op0_is_const && op1_is_const {
                        let v0: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let v1: i64 = inst.operands[1].borrow().name.parse().unwrap_or(0);
                        let result = v0.wrapping_mul(v1);
                        let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                        mi.size = mul_size;
                        mi.push_imm(result);
                        mbb.instructions.push(mi);
                    } else if let (Some(s0), Some(s1)) = (src0_vr, src1_vr) {
                        // Use two-operand IMUL to avoid the register-collision
                        // problem with MUL's implicit RAX.  IMUL r64, r/m64
                        // computes dst = dst * src without tying up RAX.
                        // This avoids the case where both MUL operands get
                        // the same physical register from the allocator,
                        // which causes MUL to compute RAX * RAX (squaring).
                        //
                        // Convention for with_def(def): rewritter inserts
                        // def's physreg at operand[0].  So the MOV below
                        // has operands [def_vreg, s0_vreg] which after rewrite
                        // becomes [def_phys, s0_phys] → MOV def, s0.
                        // MOV def, src0  (def = src0)
                        let mut mov_src0 = MachineInstr::new(x86_opcodes::MOV);
                        mov_src0.size = mul_size;
                        mov_src0.push_reg(def); // operands[0] = def (dst)
                        mov_src0.push_reg(s0); // operands[1] = s0 (src)
                        mbb.instructions.push(mov_src0);
                        // IMUL def, src1: with_def(def) causes rewritter to
                        // insert def's physreg at position 0.  So after
                        // rewrite: operands = [def_phys, s1_phys].
                        // IMUL def, s1  → def = def * s1
                        let mut imul = MachineInstr::new(x86_opcodes::IMUL).with_def(def);
                        imul.size = mul_size;
                        imul.push_reg(s1); // operands[0] = s1 (src, will shift)
                        mbb.instructions.push(imul);
                    }
                }
            }

            // === Binary Operations ===
            Some(Opcode::Add) | Some(Opcode::Sub) | Some(Opcode::And) | Some(Opcode::Or)
            | Some(Opcode::Xor) | Some(Opcode::Shl) | Some(Opcode::LShr) | Some(Opcode::AShr) => {
                let mc_opcode = ir_binop_to_x86(opcode.unwrap());
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                // Determine operand size from the IR type width, but pointers are always 64-bit.
                // i1 booleans are zero-extended to 32-bit in registers (from MOVZX after SETcc).
                // Determine the operation size. The instruction's result type
                // may be incorrectly set to a pointer type by the frontend when
                // the loaded value's type is copied from the pointer (alloca)
                // rather than the pointee type (see compile_ident in clang/codegen).
                // As a workaround, when the result type is a pointer we fall back
                // to checking the first operand's type; if that's also a pointer,
                // we try the second operand (which may be a constant with correct
                // type).
                let op_size = if inst.ty.is_pointer() || inst.get_opcode() == Some(Opcode::Alloca) {
                    // Try the first operand's type
                    let mut fallback_size = 0u8;
                    if let Some(op0) = inst.operands.first() {
                        let op0_ty = &op0.borrow().ty;
                        if !op0_ty.is_pointer() {
                            fallback_size = match op0_ty.integer_bit_width() {
                                32 | 1 => 4,
                                64 => 0,
                                _ => 0,
                            };
                        }
                    }
                    // If still couldn't determine, try the second operand.
                    // BUT only if the first operand is NOT a pointer.
                    // When the first operand is a pointer (frontend bug where
                    // loaded value type is copied from the alloca pointer rather
                    // than the pointee type), the value is 64-bit on x86-64 and
                    // we should NOT fall back to the second operand's narrower
                    // type (e.g. i32 from 1U in x_UQ0 -= 1U).  Doing so would
                    // truncate the subtraction to 32 bits, destroying the upper
                    // 32 bits of the value.
                    if fallback_size == 0 && inst.operands.len() > 1 {
                        // Check if first operand is a pointer — if so, default to 64-bit
                        let first_is_ptr = inst
                            .operands
                            .first()
                            .map_or(false, |op| op.borrow().ty.is_pointer());
                        if first_is_ptr {
                            fallback_size = 0; // 64-bit (0 means 64-bit for non-shift ALU)
                        } else {
                            let op1_ty = &inst.operands[1].borrow().ty;
                            if !op1_ty.is_pointer() {
                                fallback_size = match op1_ty.integer_bit_width() {
                                    32 | 1 => 4,
                                    64 => 0,
                                    _ => 0,
                                };
                            }
                        }
                    }
                    // For shift by constant, also check the constant's type
                    // (constants typically have the correct integer type).
                    // Shift operations need explicit size: 8 for 64-bit (triggers
                    // REX.W via inst.size >= 8), 4 for 32-bit. The fallback path
                    // above sets 64-bit operands to 0 (matching non-shift ALU), but
                    // the SHL encoder does NOT use inst_is_64bit() (which treats
                    // size==0 as 64-bit). Instead it checks inst.size >= 8, so
                    // size==0 falls through to 32-bit encoding, truncating the
                    // upper 32 bits of the value.  Override to 8 for 64-bit shifts.
                    let is_shift_op =
                        matches!(opcode.unwrap(), Opcode::Shl | Opcode::LShr | Opcode::AShr);
                    if is_shift_op {
                        // If fallback_size is 0 (64-bit operand but not set for shift)
                        // or 4 (from the int shift-count operand when the first
                        // operand was a pointer), re-check the first operand.  If
                        // the first operand is itself a pointer (frontend type
                        // copy bug — the loaded value's type was incorrectly
                        // copied from the alloca/pointer), then the pointee type
                        // width should be inferred from the pointer itself.
                        // On x86-64 all pointers are 64-bit, so use 8.
                        if fallback_size != 8 {
                            if let Some(op0) = inst.operands.first() {
                                let op0_ty = &op0.borrow().ty;
                                if op0_ty.is_pointer() {
                                    // First operand is a pointer (frontend bug).
                                    // The value being shifted is the POINTEE,
                                    // which should be a 64-bit integer for
                                    // compiler-rt (rep_t = uint64_t). Use 8.
                                    fallback_size = 8;
                                } else if op0_ty.integer_bit_width() == 64 {
                                    fallback_size = 8;
                                }
                            }
                        }
                    }
                    fallback_size
                } else {
                    // Shift operations need explicit size: 8 for 64-bit (triggers
                    // REX.W via inst.size >= 8), 4 for 32-bit. This matters because
                    // the SHL encoder does NOT use inst_is_64bit() (which treats
                    // size==0 as 64-bit). Instead it checks inst.size >= 8, so
                    // size==0 falls through to 32-bit encoding.
                    let is_shift_op =
                        matches!(opcode.unwrap(), Opcode::Shl | Opcode::LShr | Opcode::AShr);
                    if is_shift_op {
                        // Determine shift width from first operand's type.
                        // When shift count >= 32 on 32-bit operand, force 64-bit
                        // to avoid x86 masking (63 & 31 = 31) for 1ULL<<63.
                        let mut shift_size = 4u8;

                        if let Some(op0) = inst.operands.first() {
                            let op0_bw = op0.borrow().ty.integer_bit_width();
                            if op0_bw == 64 {
                                shift_size = 8;
                            }
                        }
                        // For constant shifts >= 32 on 32-bit operand, force 64-bit
                        // to avoid x86 masking (63 & 31 = 31) for `1U << 31` being
                        // masked to 31 & 31 = 0 on 32-bit SHL.
                        if shift_size == 4 && inst.operands.len() > 1 {
                            if let Ok(imm) = inst.operands[1].borrow().name.parse::<u64>() {
                                if imm >= 32 {
                                    shift_size = 8;
                                }
                                // NOTE: Do NOT force 32-bit for imm == 31.
                                // The lower 32 bits of (zext_i32 val to i64) << 31
                                // are identical to (i32)val << 31 regardless of shift
                                // width.  Forcing 32-bit here breaks 64-bit >> 31 in
                                // double-precision division's Newton-Raphson correction:
                                //   ((rep_t)x_UQ0_hw * lo_corr >> (HW - 1))
                                // where HW=32 so the shift is 64-bit >> 31.
                                // Shift width must derive from LHS type only (above).
                            }
                        }
                        shift_size
                    } else {
                        match inst.ty.integer_bit_width() {
                            32 | 1 => 4,
                            64 => 0,
                            _ => 0,
                        }
                    }
                };

                let op0_vid = inst.operands[0].borrow().vid as usize;
                let op1 = &inst.operands[1];

                let src_vr = vreg_map.get(&op0_vid).copied();

                if let Some(def) = def_vr {
                    // mc_assembler convention for ALU:
                    //   reg-imm: operand[0]=dest(r/m), operand[1]=imm
                    //   reg-reg: operand[0]=src(reg field), operand[1]=dest(r/m field)
                    //
                    // Emit MOV def, src0 to copy first source into def,
                    // then ALU with def as destination.

                    // Special case: both operands constant — fold to MOV reg, const
                    if src_vr.is_none() && op1.borrow().is_constant() {
                        let src0: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let src1: i64 = op1.borrow().name.parse().unwrap_or(0);
                        let result = match opcode.unwrap() {
                            Opcode::Add => src0 + src1,
                            Opcode::Sub => src0 - src1,
                            Opcode::Mul => src0 * src1,
                            Opcode::And => src0 & src1,
                            Opcode::Or => src0 | src1,
                            Opcode::Xor => src0 ^ src1,
                            Opcode::Shl => src0 << src1,
                            Opcode::LShr => ((src0 as u64) >> (src1 as u64)) as i64,
                            Opcode::AShr => src0 >> src1,
                            _ => src1,
                        };
                        let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                        mi.size = op_size;
                        mi.push_imm(result);
                        mbb.instructions.push(mi);
                    } else {
                        // Copy first source into def (x86 2-address form)
                        if let Some(src) = src_vr {
                            let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                            mov.size = op_size;
                            mov.push_reg(src);
                            mbb.instructions.push(mov);
                        } else if !op1.borrow().is_constant() {
                            // First operand is a constant (no vreg) but second operand is
                            // NOT constant — MOV the constant into def first.
                            let src0: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                            let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                            mov.size = op_size;
                            mov.push_imm(src0);
                            mbb.instructions.push(mov);
                        }

                        if op1.borrow().is_constant() {
                            let imm_val: i64 = op1.borrow().name.parse().unwrap_or(0);
                            // x86 ALU r/m64, imm32 sign-extends the 32-bit immediate to
                            // 64 bits. If the immediate doesn't fit in a sign-extended 32-bit
                            // value, load it into a temp register and use reg-reg form.
                            let fits_in_signed32 =
                                imm_val >= (-0x8000_0000i64) && imm_val <= 0x7FFF_FFFF;
                            if op_size == 0 && !fits_in_signed32 {
                                // 64-bit ALU with 64-bit immediate: load into temp reg first
                                let tmp = mf.new_vreg();
                                let mut load = MachineInstr::new(x86_opcodes::MOV).with_def(tmp);
                                load.size = 0; // 64-bit
                                load.push_imm(imm_val);
                                mbb.instructions.push(load);
                                // reg-reg: operand[0]=src, operand[1]=dest
                                let mut mi = MachineInstr::new(mc_opcode);
                                mi.size = op_size;
                                mi.push_reg(tmp); // operand[0] = source (reg field)
                                mi.push_reg(def); // operand[1] = dest (r/m field)
                                mbb.instructions.push(mi);
                            } else {
                                // reg-imm: operand[0]=dest, operand[1]=imm
                                let mut mi = MachineInstr::new(mc_opcode).with_def(def);
                                mi.size = op_size;
                                mi.push_imm(imm_val);
                                mbb.instructions.push(mi);
                            }
                        } else {
                            let op1_vid = op1.borrow().vid as usize;
                            if let Some(op1r) = vreg_map.get(&op1_vid).copied() {
                                // x86 shifts (SHL/SHR/ASHR) only accept CL or imm8
                                // as the shift count. If shift amount is in a register,
                                // move it to CL (phys reg 1, low byte = CL) first.
                                let is_shift = matches!(
                                    opcode.unwrap(),
                                    Opcode::Shl | Opcode::LShr | Opcode::AShr
                                );
                                if is_shift {
                                    // x86 shift: SHL/SHR/SAR r/m, CL  (second operand is always CL)
                                    // mc_assembler: operand[0]=r/m, operand[1]=CL(1) or imm
                                    // mov cl, shift_amount  (move variable shift count to CL)
                                    // Save rcx (physreg 1) into a dedicated non-rcx temporary.
                                    // We use physreg 3 (rbx) as the temp since it's callee-saved
                                    // and the pipeline handles save/restore. The RegAlloc must
                                    // NOT assign rcx_save to physreg 1 or the save/restore becomes
                                    // a NOP. Using with_def ensures the allocator chooses a reg
                                    // that is NOT implicitly clobbered by the physreg=1 usage.
                                    // rcx may hold a 64-bit alloca pointer, so save/restore
                                    // the full 64-bit register even if the data op is 32-bit.
                                    let rcx_save = mf.new_vreg();
                                    let mut save_rcx =
                                        MachineInstr::new(x86_opcodes::MOV).with_def(rcx_save);
                                    save_rcx.size = 0; // always 64-bit (rcx may hold a pointer)
                                    save_rcx.operands.push(MachineOperand::PhysReg(1)); // src = rcx
                                    mbb.instructions.push(save_rcx);
                                    // mov cl, shift_amount  (clobbers rcx)
                                    let mut mov_to_cl = MachineInstr::new(x86_opcodes::MOV);
                                    mov_to_cl.size = op_size;
                                    mov_to_cl.operands.push(MachineOperand::PhysReg(1)); // rcx (CL = low byte)
                                    mov_to_cl.push_reg(op1r);
                                    mbb.instructions.push(mov_to_cl);
                                    // shift def, CL (no with_def, push def then CL)
                                    let mut mi = MachineInstr::new(mc_opcode);
                                    mi.size = op_size;
                                    mi.push_reg(def); // operand[0] = reg to shift (r/m)
                                    mi.operands.push(MachineOperand::PhysReg(1)); // operand[1] = CL
                                    mbb.instructions.push(mi);
                                    // Restore rcx from temporary (always 64-bit restore)
                                    let mut restore_rcx = MachineInstr::new(x86_opcodes::MOV);
                                    restore_rcx.size = 0; // always 64-bit
                                    restore_rcx.operands.push(MachineOperand::PhysReg(1)); // dst = rcx
                                    restore_rcx.push_reg(rcx_save);
                                    mbb.instructions.push(restore_rcx);
                                } else {
                                    // reg-reg: mc_assembler expects operand[0]=src, operand[1]=dest
                                    // So push op1 (second source) then def (dest). No with_def.
                                    let mut mi = MachineInstr::new(mc_opcode);
                                    mi.size = op_size;
                                    mi.push_reg(op1r); // operand[0] = source (reg field)
                                    mi.push_reg(def); // operand[1] = dest (r/m field)
                                    mbb.instructions.push(mi);
                                }
                            }
                        }
                    }
                }
            }

            // === ICmp ===
            Some(Opcode::ICmp) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let op0_vid = inst.operands[0].borrow().vid as usize;
                let op1 = &inst.operands[1];

                // Parse the predicate from the instruction name: "icmp.eq", "icmp.sgt", etc.
                // The name may also have a suffix like "icmp.eq.cmp" or "icmp.ugt.cmp".
                // ClangCodeGen also emits ICmp with name='tobool' for "ne 0" (boolean conversion).
                let pred = if inst.name.starts_with("icmp.") {
                    let after_prefix = &inst.name[5..]; // "eq.cmp" or "ugt" or "ugt.cmp"
                                                        // Take only the part before any '.'
                    if let Some(dot) = after_prefix.find('.') {
                        &after_prefix[..dot]
                    } else {
                        after_prefix
                    }
                } else if inst.name == "tobool" {
                    "ne"
                } else {
                    "eq"
                };

                // Compute CMP operand size from the first operand's type (not inst.ty, which is i1)
                let cmp_op_bw = inst.operands[0].borrow().ty.integer_bit_width();
                // i1 operands are stored zero-extended to 32-bit, so compare as 32-bit.
                let cmp_size = if cmp_op_bw == 32 || cmp_op_bw == 1 {
                    4u8
                } else {
                    0u8
                };

                // Emit CMP: ensure at least one operand is materialized into a register.
                // If op0 is a constant, load it into a temp vreg first.
                let cmp_src_vr = if let Some(vr) = vreg_map.get(&op0_vid).copied() {
                    vr
                } else if op0_vid > 0 {
                    // Operand is a constant — create a temp vreg and load it
                    let vr = mf.new_vreg();
                    let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                    mov.size = cmp_size;
                    let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                    mov.push_imm(imm_val);
                    mbb.instructions.push(mov);
                    vr
                } else {
                    // Fallback: use an existing vreg
                    mf.new_vreg()
                };
                {
                    let mut cmp = MachineInstr::new(x86_opcodes::CMP);
                    cmp.size = cmp_size;
                    cmp.push_reg(cmp_src_vr);
                    // x86 CMP r64, imm32 only accepts a sign-extended 32-bit
                    // immediate.  If the constant doesn't fit in a sign-extended
                    // i32, materialize it into a temporary register first.
                    let fits_in_i32 = |v: i64| v >= i32::MIN as i64 && v <= i32::MAX as i64;
                    if op1.borrow().is_constant() {
                        let imm_val: i64 = op1.borrow().name.parse().unwrap_or(0);
                        if fits_in_i32(imm_val) {
                            cmp.push_imm(imm_val);
                        } else {
                            let vr = mf.new_vreg();
                            let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                            mov.size = cmp_size;
                            mov.push_imm(imm_val);
                            mbb.instructions.push(mov);
                            cmp.push_reg(vr);
                        }
                    } else if let Some(&op1_vr) = vreg_map.get(&(op1.borrow().vid as usize)) {
                        cmp.push_reg(op1_vr);
                    } else {
                        // op1 is also a constant without vreg — load it as immediate
                        let imm_val: i64 = op1.borrow().name.parse().unwrap_or(0);
                        if fits_in_i32(imm_val) {
                            cmp.push_imm(imm_val);
                        } else {
                            let vr = mf.new_vreg();
                            let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                            mov.size = cmp_size;
                            mov.push_imm(imm_val);
                            mbb.instructions.push(mov);
                            cmp.push_reg(vr);
                        }
                    }
                    mbb.instructions.push(cmp);
                }

                // Map predicate to SETcc opcode
                let setcc_op = match pred {
                    "eq" => x86_opcodes::SETE,
                    "ne" => x86_opcodes::SETNE,
                    "sgt" => x86_opcodes::SETG,
                    "sge" => x86_opcodes::SETGE,
                    "slt" => x86_opcodes::SETL,
                    "sle" => x86_opcodes::SETLE,
                    "ugt" => x86_opcodes::SETA,
                    "uge" => x86_opcodes::SETAE,
                    "ult" => x86_opcodes::SETB,
                    "ule" => x86_opcodes::SETBE,
                    _ => x86_opcodes::SETE,
                };

                // Emit SETcc + MOVZX to produce a 32-bit boolean result
                if let Some(def) = def_vr {
                    // setcc def (sets 8-bit register al/cl/dl/bl from flags)
                    let mut set = MachineInstr::new(setcc_op).with_def(def);
                    mbb.instructions.push(set);

                    // movzx def, def (zero-extend 8-bit result to 32-bit)
                    let mut zx = MachineInstr::new(x86_opcodes::MOVZX).with_def(def);
                    zx.push_reg(def);
                    mbb.instructions.push(zx);
                }
            }

            // === Alloca ===
            // Alloca: compute a unique offset from rbp based on the
            // allocated byte size (stored as the first constant operand).
            // Each alloca consumes its actual byte-size rounded up to
            // alignment (8 bytes), so large structs/arrays get adequate
            // stack space.
            //
            // Using rbp (not rsp) ensures allocas stay within the frame
            // even after `sub rsp, N` has been executed. The pipeline's
            // `push rbp; mov rbp, rsp` prologue runs before any alloca
            // so rbp is always valid at this point.
            Some(Opcode::Alloca) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                if let Some(def) = def_vr {
                    let ptr_size: u8 = 0;
                    // Read the allocated byte size from operand[0] (a
                    // constant i64 stored by instruction::alloca()).
                    let byte_size: i64 = inst
                        .operands
                        .first()
                        .and_then(|v| v.borrow().name.parse::<i64>().ok())
                        .unwrap_or(8)
                        .max(1);
                    // Round up to 8-byte alignment.
                    let aligned_size = ((byte_size + 7) / 8) * 8;
                    // Accumulate downward from rbp.
                    mf.alloca_byte_offset += aligned_size;
                    let offset = mf.alloca_byte_offset;
                    // Record this alloca's frame offset for direct LOAD/STORE bypass.
                    mf.alloca_offsets.insert(inst.vid as usize, offset);
                    eprintln!(
                        "ALLOCA_SLOT func={} ir_vid={} name='{}' size={} aligned={} offset=rbp-0x{:x}",
                        mf.name,
                        inst.vid,
                        inst.name,
                        byte_size,
                        aligned_size,
                        offset
                    );
                    // MOV def, rbp
                    let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                    mov.size = ptr_size;
                    mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                    mbb.instructions.push(mov);
                    // SUB def, offset
                    let mut sub = MachineInstr::new(x86_opcodes::SUB).with_def(def);
                    sub.size = ptr_size;
                    sub.push_imm(offset);
                    mbb.instructions.push(sub);
                }
            }

            // === Load ===
            Some(Opcode::Load) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let ptr_vid = inst.operands[0].borrow().vid as usize;
                let load_size = if inst.ty.is_floating_point() {
                    if inst.ty.is_double_ty() {
                        0u8
                    } else {
                        4u8
                    } // double=64bit, float=32bit
                } else if inst.ty.integer_bit_width() == 8 {
                    1u8 // i8: byte load, zero-extend to 32-bit
                } else if inst.ty.integer_bit_width() == 32 || inst.ty.integer_bit_width() == 1 {
                    4u8 // i1 booleans are zero-extended to 32-bit
                } else {
                    0u8
                };

                // ALWAYS load from memory — no parameter forwarding.
                if let Some(def) = def_vr {
                    // Fast/direct path for local allocas:
                    // If the pointer operand is an Alloca result, load directly from its
                    // rbp-relative frame slot instead of loading through the alloca pointer vreg.
                    //
                    // This kills the productHi bug:
                    //   wideMultiply writes productHi at rbp-0x60
                    //   later productHi read must also read rbp-0x60
                    // not reload a spilled pointer from rbp-8 and then double-deref it.
                    if let Some(&offset) = mf.alloca_offsets.get(&ptr_vid) {
                        eprintln!(
                            "DIRECT_ALLOCA_LOAD func={} ptr_vid={} offset=rbp-0x{:x} size={}",
                            mf.name, ptr_vid, offset, load_size
                        );

                        // MOV r12, rbp
                        let mut mov_addr = MachineInstr::new(x86_opcodes::MOV);
                        mov_addr.operands.push(MachineOperand::PhysReg(12)); // r12 = frame addr temp
                        mov_addr.operands.push(MachineOperand::PhysReg(5)); // rbp
                        mov_addr.size = 0;
                        mbb.instructions.push(mov_addr);

                        // SUB r12, offset
                        let mut sub_addr = MachineInstr::new(x86_opcodes::SUB);
                        sub_addr.operands.push(MachineOperand::PhysReg(12));
                        sub_addr.push_imm(offset);
                        sub_addr.size = 0;
                        mbb.instructions.push(sub_addr);

                        // LOAD def, [r12]
                        let mut mi = MachineInstr::new(x86_opcodes::LOAD).with_def(def);
                        mi.size = load_size;
                        mi.operands.push(MachineOperand::PhysReg(12));
                        mbb.instructions.push(mi);
                    } else if let Some(&ptr_vr) = vreg_map.get(&ptr_vid) {
                        // Check if the pointer is a GlobalVariable that needs
                        // its address materialized via LEA.
                        let ptr_val = inst.operands[0].borrow();
                        let is_global = ptr_val.is_global_variable()
                            || ptr_val.subclass == SubclassKind::GlobalVariable;

                        if is_global {
                            // Global variable: emit LEA to get its address into
                            // r10, then load from [r10] into def.
                            let gv_name = ptr_val.name.clone();
                            let mut lea = MachineInstr::new(x86_opcodes::LEA);
                            lea.operands.push(MachineOperand::PhysReg(10));
                            lea.operands.push(MachineOperand::Global(gv_name));
                            mbb.instructions.push(lea);
                            // LOAD def, [r10]
                            let mut mi = MachineInstr::new(x86_opcodes::LOAD).with_def(def);
                            mi.size = load_size;
                            mi.operands.push(MachineOperand::PhysReg(10));
                            mbb.instructions.push(mi);
                        } else {
                            // Float values live in GPRs (bit pattern extracted via
                            // MOVD_FROM_XMM at function entry or from CALL return).
                            // Use integer LOAD/STORE instead of MOVSS/MOVSD which
                            // would treat the GPR vreg as an XMM register number.
                            let mut mi = MachineInstr::new(x86_opcodes::LOAD).with_def(def);
                            mi.size = load_size;
                            mi.push_reg(ptr_vr);
                            mbb.instructions.push(mi);
                        }
                    }
                }
            }

            // === Store ===
            Some(Opcode::Store) => {
                let val_vid = inst.operands[0].borrow().vid as usize;
                let ptr_vid = inst.operands[1].borrow().vid as usize;
                let val_ty = inst.operands[0].borrow().ty.clone();
                let store_size = if val_ty.is_floating_point() {
                    if val_ty.is_double_ty() {
                        0u8
                    } else {
                        4u8
                    }
                } else if val_ty.integer_bit_width() == 8 {
                    1u8 // i8: byte store
                } else if val_ty.integer_bit_width() == 32 || val_ty.integer_bit_width() == 1 {
                    4u8
                } else {
                    0u8
                };

                // Fast/direct path for local allocas:
                // If the pointer operand is an Alloca result, store directly to its
                // rbp-relative frame slot instead of storing through the alloca pointer vreg.
                if let Some(&offset) = mf.alloca_offsets.get(&ptr_vid) {
                    eprintln!(
                        "DIRECT_ALLOCA_STORE func={} ptr_vid={} offset=rbp-0x{:x} size={}",
                        mf.name, ptr_vid, offset, store_size
                    );

                    // MOV r12, rbp
                    let mut mov_addr = MachineInstr::new(x86_opcodes::MOV);
                    mov_addr.operands.push(MachineOperand::PhysReg(12)); // r12
                    mov_addr.operands.push(MachineOperand::PhysReg(5)); // rbp
                    mov_addr.size = 0;
                    mbb.instructions.push(mov_addr);

                    // SUB r12, offset
                    let mut sub_addr = MachineInstr::new(x86_opcodes::SUB);
                    sub_addr.operands.push(MachineOperand::PhysReg(12));
                    sub_addr.push_imm(offset);
                    sub_addr.size = 0;
                    mbb.instructions.push(sub_addr);

                    if let Some(&val_vr) = vreg_map.get(&val_vid) {
                        // STORE [r12], val_vr
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = store_size;
                        mi.operands.push(MachineOperand::PhysReg(12)); // ptr
                        mi.push_reg(val_vr); // val
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().subclass == SubclassKind::Function {
                        // Store a function pointer: LEA r10, [func_name]; STORE [r12], r10
                        let func_name = inst.operands[0].borrow().name.clone();
                        let mut lea = MachineInstr::new(x86_opcodes::LEA);
                        lea.operands.push(MachineOperand::PhysReg(10));
                        lea.operands.push(MachineOperand::Global(func_name));
                        mbb.instructions.push(lea);
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = 0; // 64-bit store for pointer
                        mi.operands.push(MachineOperand::PhysReg(12)); // ptr
                        mi.operands.push(MachineOperand::PhysReg(10)); // val
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().is_global_variable() {
                        // Store a global variable address: LEA r10, [gv]; STORE [r12], r10
                        let gv_name = inst.operands[0].borrow().name.clone();
                        let mut lea = MachineInstr::new(x86_opcodes::LEA);
                        lea.operands.push(MachineOperand::PhysReg(10));
                        lea.operands.push(MachineOperand::Global(gv_name));
                        mbb.instructions.push(lea);
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = 0; // 64-bit pointer store
                        mi.operands.push(MachineOperand::PhysReg(12)); // ptr
                        mi.operands.push(MachineOperand::PhysReg(10)); // val
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().is_constant() {
                        let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let tmp_vr = mf.new_vreg();

                        // For i8 stores, load constant as 32-bit MOV (auto zero-extends),
                        // then store as byte. The MOV must be 32-bit (size=4) because
                        // the MOV encoder doesn't support sub-32-bit immediates.
                        let mov_size: u8 = if store_size == 1 { 4 } else { store_size };
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(tmp_vr);
                        mov.size = mov_size;
                        mov.push_imm(imm_val);
                        mbb.instructions.push(mov);

                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = store_size;
                        mi.operands.push(MachineOperand::PhysReg(12)); // ptr
                        mi.push_reg(tmp_vr); // val
                        mbb.instructions.push(mi);
                    }
                } else if let Some(&ptr_vr) = vreg_map.get(&ptr_vid) {
                    if let Some(&val_vr) = vreg_map.get(&val_vid) {
                        // Float values live in GPRs — use integer STORE.
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = store_size;
                        mi.push_reg(ptr_vr);
                        mi.push_reg(val_vr);
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().subclass == SubclassKind::Function {
                        // Store a function pointer: LEA r10, [func_name]; STORE [ptr_vr], r10
                        let func_name = inst.operands[0].borrow().name.clone();
                        let mut lea = MachineInstr::new(x86_opcodes::LEA);
                        lea.operands.push(MachineOperand::PhysReg(10));
                        lea.operands.push(MachineOperand::Global(func_name));
                        mbb.instructions.push(lea);
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = 0; // 64-bit store for pointer
                        mi.push_reg(ptr_vr);
                        mi.operands.push(MachineOperand::PhysReg(10));
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().is_global_variable() {
                        // Store a global variable address: LEA r10, [gv]; STORE [ptr_vr], r10
                        let gv_name = inst.operands[0].borrow().name.clone();
                        let mut lea = MachineInstr::new(x86_opcodes::LEA);
                        lea.operands.push(MachineOperand::PhysReg(10));
                        lea.operands.push(MachineOperand::Global(gv_name));
                        mbb.instructions.push(lea);
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = 0; // 64-bit pointer store
                        mi.push_reg(ptr_vr);
                        mi.operands.push(MachineOperand::PhysReg(10));
                        mbb.instructions.push(mi);
                    } else if inst.operands[0].borrow().is_constant() {
                        let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let tmp_vr = mf.new_vreg();
                        let mov_size: u8 = if store_size == 1 { 4 } else { store_size };
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(tmp_vr);
                        mov.size = mov_size;
                        mov.push_imm(imm_val);
                        mbb.instructions.push(mov);
                        let mut mi = MachineInstr::new(x86_opcodes::STORE);
                        mi.size = store_size;
                        mi.push_reg(ptr_vr);
                        mi.push_reg(tmp_vr);
                        mbb.instructions.push(mi);
                    }
                }
            }

            // === Call ===
            Some(Opcode::Call) => {
                if num_ops >= 1 {
                    let func_name = inst.operands[0].borrow().name.clone();
                    eprintln!(
                        "ISel Call: func='{}' num_ops={}",
                        func_name,
                        inst.operands.len()
                    );

                    // Move arguments to ABI registers (SysV x86-64)
                    // Integer: arg0 -> rdi(7), arg1 -> rsi(6), arg2 -> rdx(2),
                    //          arg3 -> rcx(1), arg4 -> r8(8), arg5 -> r9(9)
                    // FP:      arg0 -> xmm0(64), arg1 -> xmm1(65), ...
                    let int_abi_regs: [PhysReg; 6] = [7, 6, 2, 1, 8, 9];
                    let mut int_arg_idx = 0usize;
                    let mut fp_arg_idx = 0usize;

                    // === Stack-based CALL argument setup (real parallel copy) ===
                    // Phase 1: Capture ALL integer argument sources to the STACK through
                    //          reserved r10(10) BEFORE writing any ABI destination registers.
                    // Phase 2: Load from stack to ABI registers in reverse capture order.
                    //
                    // This is safe because:
                    //   1. r10 is RESERVED — never assigned to a vreg by the allocator.
                    //   2. rsp(4) is RESERVED — always valid stack pointer.
                    //   3. Stack captures don't go through vregs, so the allocator cannot
                    //      clobber captured values by assigning them to ABI registers.
                    //   4. ALL sources are captured to stack BEFORE any ABI register write,
                    //      avoiding the classic sequential-MOV cycle:
                    //        mov rdi, rsi  ; arg0 src is in rsi
                    //        mov rsi, rdi  ; arg1 src is in rdi — rdi was clobbered! CORRUPT!
                    let mut num_int_arg_captures = 0usize;

                    for op in inst.operands.iter().skip(1) {
                        let ty = op.borrow().ty.clone();
                        if ty.is_floating_point() {
                            if fp_arg_idx >= 8 {
                                break; // Stack arguments not yet supported
                            }
                            let xmm_reg = 64 + fp_arg_idx as u32;
                            let is_double = ty.is_double_ty();
                            // Float values live in GPRs (bit pattern). Use MOVD (GPR→XMM)
                            // instead of MOVSS/MOVSD (XMM→XMM) to transfer bits to XMM
                            // registers for the CALL ABI.
                            // MOVD convention: operands[0]=GPR(src), operands[1]=XMM(dst)
                            let mut mov = MachineInstr::new(if is_double {
                                x86_opcodes::MOVQ
                            } else {
                                x86_opcodes::MOVD
                            });
                            let arg_vid = op.borrow().vid as usize;
                            if let Some(&arg_vr) = vreg_map.get(&arg_vid) {
                                mov.push_reg(arg_vr); // operands[0] = source = GPR vreg
                                mov.operands.push(MachineOperand::PhysReg(xmm_reg));
                            // operands[1] = dest = XMM
                            } else {
                                let imm_val: i64 = op.borrow().name.parse().unwrap_or(0);
                                // Load constant into xmm via MOVD
                                // MOVD only supports register sources, so load into GPR first
                                let tmp_vr = mf.new_vreg();
                                let mut load = MachineInstr::new(x86_opcodes::MOV).with_def(tmp_vr);
                                load.size = if is_double { 0 } else { 4 };
                                load.push_imm(imm_val);
                                mbb.instructions.push(load);
                                mov.push_reg(tmp_vr); // operands[0] = GPR with constant
                                mov.operands.push(MachineOperand::PhysReg(xmm_reg));
                                // operands[1] = dest = XMM
                            }
                            mbb.instructions.push(mov);
                            fp_arg_idx += 1;
                        } else {
                            if int_arg_idx >= int_abi_regs.len() {
                                break; // Stack arguments not yet supported
                            }
                            let dst_phys = int_abi_regs[int_arg_idx];
                            let arg_vid = op.borrow().vid as usize;

                            // Determine argument size for proper MOV width.
                            // On x86-64, writing a 32-bit register zero-extends to
                            // upper 32 bits.  This matters for compiler-rt wideMultiply:
                            //   (uint64_t)(uint32_t)a * (uint32_t)b
                            let arg_bw = ty.integer_bit_width();
                            let arg_size: u8 = if arg_bw > 0 && arg_bw <= 32 { 4 } else { 0 };

                            let arg_vid = op.borrow().vid as usize;
                            // Check GlobalVariable and Alloca BEFORE vreg_map.
                            // The operand scan loop adds all non-constant operands to
                            // vreg_map, including GlobalVariable and Alloca values.
                            // But those vregs may not be reliable as call-argument
                            // addresses (GlobalVariable has no defining instruction;
                            // Alloca vregs use DIRECT_ALLOCA bypass and the vreg may
                            // not be properly initialized under spill pressure).
                            if op.borrow().is_global_variable() {
                                // Global variable address — LEA r10, [global_sym]
                                let gv_name = op.borrow().name.clone();
                                let mut lea = MachineInstr::new(x86_opcodes::LEA);
                                lea.operands.push(MachineOperand::PhysReg(10));
                                lea.operands.push(MachineOperand::Global(gv_name));
                                mbb.instructions.push(lea);
                            } else if !mf.name.starts_with("__") {
                                if let Some(&alloca_off) = mf.alloca_offsets.get(&arg_vid) {
                                    // Non-compiler-rt function: compute alloca address fresh
                                    // from rbp to avoid caller-save clobber between adjacent calls.
                                    let mut mov = MachineInstr::new(x86_opcodes::MOV);
                                    mov.operands.push(MachineOperand::PhysReg(10));
                                    mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                                    mov.size = 0; // 64-bit
                                    mbb.instructions.push(mov);
                                    let mut sub = MachineInstr::new(x86_opcodes::SUB);
                                    sub.operands.push(MachineOperand::PhysReg(10));
                                    sub.push_imm(alloca_off);
                                    sub.size = 0; // 64-bit
                                    mbb.instructions.push(sub);
                                } else if let Some(&arg_vr) = vreg_map.get(&arg_vid) {
                                    let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                    to_r10.operands.push(MachineOperand::PhysReg(10));
                                    to_r10.push_reg(arg_vr);
                                    to_r10.size = arg_size;
                                    mbb.instructions.push(to_r10);
                                } else if op.borrow().is_constant() {
                                    let imm_val: i64 = op.borrow().name.parse().unwrap_or(0);
                                    let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                    to_r10.operands.push(MachineOperand::PhysReg(10));
                                    to_r10.push_imm(imm_val);
                                    to_r10.size = arg_size;
                                    mbb.instructions.push(to_r10);
                                } else {
                                    let imm_val: i64 = op.borrow().name.parse().unwrap_or(0);
                                    let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                    to_r10.operands.push(MachineOperand::PhysReg(10));
                                    to_r10.push_imm(imm_val);
                                    to_r10.size = arg_size;
                                    mbb.instructions.push(to_r10);
                                }
                            } else if let Some(&arg_vr) = vreg_map.get(&arg_vid) {
                                let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                to_r10.operands.push(MachineOperand::PhysReg(10));
                                to_r10.push_reg(arg_vr);
                                to_r10.size = arg_size;
                                mbb.instructions.push(to_r10);
                            } else if op.borrow().is_constant() {
                                let imm_val: i64 = op.borrow().name.parse().unwrap_or(0);
                                let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                to_r10.operands.push(MachineOperand::PhysReg(10));
                                to_r10.push_imm(imm_val);
                                to_r10.size = arg_size;
                                mbb.instructions.push(to_r10);
                            } else {
                                let imm_val: i64 = op.borrow().name.parse().unwrap_or(0);
                                let mut to_r10 = MachineInstr::new(x86_opcodes::MOV);
                                to_r10.operands.push(MachineOperand::PhysReg(10));
                                to_r10.push_imm(imm_val);
                                to_r10.size = arg_size;
                                mbb.instructions.push(to_r10);
                            }

                            // SUB rsp, 8 — make room for captured arg
                            let mut sub_rsp = MachineInstr::new(x86_opcodes::SUB);
                            sub_rsp.operands.push(MachineOperand::PhysReg(4)); // rsp
                            sub_rsp.push_imm(8);
                            sub_rsp.size = 0; // 64-bit
                            mbb.instructions.push(sub_rsp);

                            // STORE [rsp], r10 — save captured arg to stack
                            let mut store = MachineInstr::new(x86_opcodes::STORE);
                            store.operands.push(MachineOperand::PhysReg(4)); // ptr = rsp
                            store.operands.push(MachineOperand::PhysReg(10)); // val = r10
                            store.size = 0; // 64-bit
                            mbb.instructions.push(store);

                            num_int_arg_captures += 1;
                            int_arg_idx += 1;
                        }
                    }

                    // Phase 2: Restore from stack to ABI registers in REVERSE capture order.
                    // Stack is LIFO: last captured arg is at [rsp], first is at [rsp+N*8].
                    // Iterating backwards pops args in correct ABI order:
                    //   arg3 -> rcx, arg2 -> rdx, arg1 -> rsi, arg0 -> rdi
                    for i in (0..num_int_arg_captures).rev() {
                        let dst_phys = int_abi_regs[i];

                        // LOAD r10, [rsp] — load from stack
                        let mut load = MachineInstr::new(x86_opcodes::LOAD);
                        load.operands.push(MachineOperand::PhysReg(10)); // dst = r10
                        load.operands.push(MachineOperand::PhysReg(4)); // ptr = rsp
                        load.size = 0; // 64-bit
                        mbb.instructions.push(load);

                        // MOV ABI_reg, r10 — write to ABI destination
                        let mut to_abi = MachineInstr::new(x86_opcodes::MOV);
                        to_abi.operands.push(MachineOperand::PhysReg(dst_phys));
                        to_abi.operands.push(MachineOperand::PhysReg(10));
                        to_abi.size = 0;
                        mbb.instructions.push(to_abi);

                        // ADD rsp, 8 — pop from stack
                        let mut add_rsp = MachineInstr::new(x86_opcodes::ADD);
                        add_rsp.operands.push(MachineOperand::PhysReg(4)); // rsp
                        add_rsp.push_imm(8);
                        add_rsp.size = 0; // 64-bit
                        mbb.instructions.push(add_rsp);
                    }

                    // Determine if this is a direct call (to a known function)
                    // or an indirect call (through a function pointer).
                    let callee_val = inst.operands[0].borrow();
                    let is_direct = callee_val.subclass == SubclassKind::Function;
                    drop(callee_val);

                    if is_direct {
                        // Direct call: emit CALL with global symbol operand.
                        let mut mi = MachineInstr::new(x86_opcodes::CALL);
                        mi.operands.push(MachineOperand::Global(func_name));
                        mbb.instructions.push(mi);
                    } else {
                        // Indirect call through a function pointer.
                        // The callee operand is an instruction result (e.g. a load
                        // from a function-pointer variable).  Use the vreg from
                        // the value map; the register allocator will assign a
                        // physical register, and rewrite_vregs will convert
                        // MachineOperand::Reg to MachineOperand::PhysReg.
                        let callee_vid = inst.operands[0].borrow().vid as usize;
                        if let Some(&callee_vr) = vreg_map.get(&callee_vid) {
                            let mut mi = MachineInstr::new(x86_opcodes::CALL);
                            mi.operands.push(MachineOperand::Reg(callee_vr));
                            mbb.instructions.push(mi);
                        } else {
                            // Fallback: try direct call with func_name.
                            let mut mi = MachineInstr::new(x86_opcodes::CALL);
                            mi.operands.push(MachineOperand::Global(func_name));
                            mbb.instructions.push(mi);
                        }
                    }

                    // Capture return value into the def vreg
                    // SysV x86-64 ABI: integer return in rax(0), float/double return in xmm0(64)
                    let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                    if let Some(def) = def_vr {
                        if !inst.ty.is_void() {
                            if inst.ty.is_floating_point() {
                                // Float/double return: use MOVD_FROM_XMM to transfer
                                // FROM xmm0 (hardware return reg) TO the def vreg.
                                // MOVD (XMM→GPR) extracts the float bit pattern into
                                // a GPR, which is what soft-float builtins expect.
                                let is_double = inst.ty.is_double_ty();
                                let mut mov = MachineInstr::new(if is_double {
                                    x86_opcodes::MOVQ_FROM_XMM
                                } else {
                                    x86_opcodes::MOVD_FROM_XMM
                                });
                                // MOVD_FROM_XMM convention: operands[0]=XMM(src), operands[1]=GPR(dst)
                                mov.operands.push(MachineOperand::PhysReg(64)); // operands[0] = source = xmm0
                                mov.push_reg(def); // operands[1] = dest = def vreg (GPR)
                                mbb.instructions.push(mov);
                            } else {
                                let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                mov.size = if inst.ty.integer_bit_width() == 32
                                    || inst.ty.integer_bit_width() == 1
                                {
                                    4
                                } else {
                                    0
                                };
                                mov.operands.push(MachineOperand::PhysReg(0)); // eax/rax
                                mbb.instructions.push(mov);
                            }
                        }
                    }
                }
            }

            // === GetElementPtr ===
            // GEP is lowered as a simple pointer copy.  The result pointer
            // value is the same as the input; GEP only changes the type.
            // This matters because subsequent PtrToInt/IntToPtr chains
            // read from the GEP's def vreg.  Without emitting something,
            // the vreg holds garbage when we reach PtrToInt.
            Some(Opcode::GetElementPtr) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let ptr_val = inst.operands[0].borrow();
                // Check for global variables FIRST (before vreg_map lookup),
                // because the vreg allocation phase assigns vregs to ALL
                // operand vids (including globals), which would otherwise
                // cause the MOV path to be taken for global operands.
                // Global variables need LEA to materialize their address.
                if !ptr_val.name.is_empty() && ptr_val.is_global_variable() {
                    if let Some(def) = def_vr {
                        // LEA r10, [global]
                        let mut mi = MachineInstr::new(x86_opcodes::LEA);
                        mi.operands.push(MachineOperand::PhysReg(10));
                        mi.operands
                            .push(MachineOperand::Global(ptr_val.name.clone()));
                        mbb.instructions.push(mi);
                        // MOV def, r10
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                        mov.operands.push(MachineOperand::PhysReg(10));
                        mbb.instructions.push(mov);
                    }
                } else if let Some(def) = def_vr {
                    let ptr_vid = ptr_val.vid as usize;
                    if let Some(&ptr_vr) = vreg_map.get(&ptr_vid) {
                        // Normal case: source operand is a register.
                        let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                        mi.push_reg(ptr_vr);
                        mbb.instructions.push(mi);
                    }
                    // If neither, the def vreg stays uninitialized
                }
            }

            // === Phi ===
            Some(Opcode::Phi) => {
                // Phi nodes are lowered to moves in predecessor blocks
                // For now, assign vreg but emit nothing (handled by regalloc coalescing)
            }

            // === Cast Operations ===
            Some(Opcode::ZExt)
            | Some(Opcode::SExt)
            | Some(Opcode::Trunc)
            | Some(Opcode::BitCast)
            | Some(Opcode::PtrToInt)
            | Some(Opcode::IntToPtr) => {
                let src_vid = inst.operands[0].borrow().vid as usize;
                let src_ty = inst.operands[0].borrow().ty.clone();
                let dst_ty = inst.ty.clone();
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                if let Some(def) = def_vr {
                    if let Some(&src_vr) = vreg_map.get(&src_vid) {
                        let src_bits = src_ty.integer_bit_width();
                        let dst_bits = dst_ty.integer_bit_width();

                        match opcode.unwrap() {
                            Opcode::ZExt => {
                                // Critical for divdf3:
                                //   (rep_t)x_UQ0_hw where half_rep_t is uint32_t
                                //   and rep_t is uint64_t.
                                //
                                // On x86-64, writing a 32-bit destination register
                                // zero-extends into the full 64-bit physical register.
                                // MOV r32, r32 is the correct cheap zext i32 -> i64.
                                if dst_bits == 64 && src_bits > 0 && src_bits <= 32 {
                                    // 32-bit MOV auto-zero-extends to 64-bit on x86-64.
                                    let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                    mi.size = 4;
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                } else {
                                    let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                    mi.size = match dst_bits {
                                        32 | 1 => 4,
                                        64 => 0,
                                        _ => 0,
                                    };
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                }
                            }

                            Opcode::SExt => {
                                // Sign-extend i32 -> i64 using MOVSXD
                                // Sign-extend i8 -> i32/i64 using MOVSX
                                if dst_bits == 64 && src_bits == 32 {
                                    let mut mi =
                                        MachineInstr::new(x86_opcodes::MOVSXD).with_def(def);
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                } else if src_bits == 8 && (dst_bits == 32 || dst_bits == 64) {
                                    // MOVSX r32/r64, r8: sign-extend byte to 32 or 64 bits
                                    let mut mi =
                                        MachineInstr::new(x86_opcodes::MOVSX).with_def(def);
                                    mi.size = match dst_bits {
                                        32 => 4,
                                        64 => 0,
                                        _ => 0,
                                    };
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                } else {
                                    let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                    mi.size = match dst_bits {
                                        32 | 1 => 4,
                                        64 => 0,
                                        _ => 0,
                                    };
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                }
                            }

                            Opcode::Trunc => {
                                // Keep the low bits. For i64 -> i32, a 32-bit MOV
                                // reads the low 32-bit source and writes the dest.
                                let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                mi.size = match dst_bits {
                                    32 | 1 => 4,
                                    64 => 0,
                                    _ => 4,
                                };
                                mi.push_reg(src_vr);
                                mbb.instructions.push(mi);
                            }

                            Opcode::BitCast | Opcode::PtrToInt | Opcode::IntToPtr => {
                                // PtrToInt on a GlobalVariable (or Function) needs the
                                // address materialized via LEA, because the vreg for a
                                // global holds no address — it was only allocated a slot
                                // in vreg_map but never loaded.  Same for BitCast of a
                                // pointer that is a global.  IntToPtr operand is always
                                // an integer, so it never hits this path.
                                let emitted = if opcode == Some(Opcode::PtrToInt)
                                    || opcode == Some(Opcode::BitCast)
                                {
                                    let src_val = inst.operands[0].borrow();
                                    let src_vid = src_val.vid as usize;
                                    if src_val.is_global_variable()
                                        || src_val.subclass == SubclassKind::Function
                                    {
                                        let gv_name = src_val.name.clone();
                                        // LEA r10, [gv_name]
                                        let mut mi = MachineInstr::new(x86_opcodes::LEA);
                                        mi.operands.push(MachineOperand::PhysReg(10));
                                        mi.operands.push(MachineOperand::Global(gv_name));
                                        mbb.instructions.push(mi);
                                        // MOV def, r10 — move address to def vreg
                                        let mut mov =
                                            MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                        mov.operands.push(MachineOperand::PhysReg(10));
                                        mbb.instructions.push(mov);
                                        true
                                    } else if mf.alloca_offsets.contains_key(&src_vid)
                                        && !mf.name.starts_with("__")
                                    {
                                        // PtrToInt/BitCast of an alloca pointer: the alloca
                                        // vreg was defined by the ALLOCA ISel (MOV def, rbp;
                                        // SUB def, offset), but under register pressure the
                                        // vreg may be spilled and the spill/reload may not
                                        // restore the correct value.  Materialize the address
                                        // fresh from rbp, same as the CALL argument capture.
                                        let offset = mf.alloca_offsets[&src_vid];
                                        // MOV r10, rbp
                                        let mut mov_rbp = MachineInstr::new(x86_opcodes::MOV);
                                        mov_rbp.operands.push(MachineOperand::PhysReg(10));
                                        mov_rbp.operands.push(MachineOperand::PhysReg(5));
                                        mov_rbp.size = 0; // 64-bit
                                        mbb.instructions.push(mov_rbp);
                                        // SUB r10, offset
                                        let mut sub = MachineInstr::new(x86_opcodes::SUB);
                                        sub.operands.push(MachineOperand::PhysReg(10));
                                        sub.push_imm(offset);
                                        sub.size = 0; // 64-bit
                                        mbb.instructions.push(sub);
                                        // MOV def, r10 — move address to def vreg
                                        let mut mov =
                                            MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                        mov.operands.push(MachineOperand::PhysReg(10));
                                        mbb.instructions.push(mov);
                                        true
                                    } else {
                                        false
                                    }
                                } else {
                                    false
                                };
                                if !emitted {
                                    let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                                    mi.size = match dst_bits {
                                        32 | 1 => 4,
                                        64 => 0,
                                        _ => 0,
                                    };
                                    mi.push_reg(src_vr);
                                    mbb.instructions.push(mi);
                                }
                            }

                            _ => unreachable!(),
                        }
                    } else if inst.operands[0].borrow().is_constant() {
                        // Source is a constant not in vreg_map — load immediate
                        let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);

                        let mut mi = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                        mi.size = match dst_ty.integer_bit_width() {
                            32 | 1 => 4,
                            64 => 0,
                            _ => 0,
                        };
                        mi.push_imm(imm_val);
                        mbb.instructions.push(mi);
                    }
                }
            }

            // === Division & Remainder (SDiv, UDiv, SRem, URem) ===
            Some(Opcode::UDiv) | Some(Opcode::SDiv) | Some(Opcode::URem) | Some(Opcode::SRem) => {
                let is_rem = matches!(opcode, Some(Opcode::URem) | Some(Opcode::SRem));
                let is_signed = matches!(opcode, Some(Opcode::SDiv) | Some(Opcode::SRem));
                let is_unsigned = matches!(opcode, Some(Opcode::UDiv) | Some(Opcode::URem));
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let op0_vid = inst.operands[0].borrow().vid as usize;
                let op0_ty = inst.operands[0].borrow().ty.clone();
                let op_size = match op0_ty.integer_bit_width() {
                    32 | 1 => 4u8,
                    64 => 0u8,
                    _ => 0u8,
                };
                if let Some(def) = def_vr {
                    // Resolve src0: vreg or constant
                    let src0_vr = if let Some(vr) = vreg_map.get(&op0_vid).copied() {
                        vr
                    } else if op0_vid > 0 {
                        let vr = mf.new_vreg();
                        let imm_val: i64 = inst.operands[0].borrow().name.parse().unwrap_or(0);
                        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                        mov.size = op_size;
                        mov.push_imm(imm_val);
                        mbb.instructions.push(mov);
                        vr
                    } else {
                        // No fallback — skip
                        return;
                    };
                    // Resolve src1: vreg or constant
                    let src1_vr = if inst.operands.len() > 1 {
                        let op1_vid = inst.operands[1].borrow().vid as usize;
                        if let Some(vr) = vreg_map.get(&op1_vid).copied() {
                            vr
                        } else if op1_vid > 0 {
                            let vr = mf.new_vreg();
                            let imm_val: i64 = inst.operands[1].borrow().name.parse().unwrap_or(0);
                            let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vr);
                            mov.size = op_size;
                            mov.push_imm(imm_val);
                            mbb.instructions.push(mov);
                            vr
                        } else {
                            return;
                        }
                    } else {
                        return;
                    };
                    // Step 1: mov eax, op0  (copy dividend to eax/rax)
                    let mut mov_eax = MachineInstr::new(x86_opcodes::MOV);
                    mov_eax.operands.push(MachineOperand::PhysReg(0)); // eax/rax
                    mov_eax.size = op_size;
                    mov_eax.push_reg(src0_vr);
                    mbb.instructions.push(mov_eax);

                    if is_unsigned {
                        // Step 2 (Unsigned): xor edx/rdx, edx/rdx (zero-extend)
                        let mut xor_edx = MachineInstr::new(x86_opcodes::XOR);
                        xor_edx.operands.push(MachineOperand::PhysReg(2)); // edx/rdx
                        xor_edx.operands.push(MachineOperand::PhysReg(2));
                        xor_edx.size = op_size;
                        mbb.instructions.push(xor_edx);
                    } else {
                        // Step 2 (Signed): cdq (32-bit) or cqo (64-bit) sign-extend
                        let ext_op = if op_size == 0 {
                            x86_opcodes::CQO
                        } else {
                            x86_opcodes::CDQ
                        };
                        mbb.instructions.push(MachineInstr::new(ext_op));
                    }

                    // Step 3: div/idiv op1
                    let div_opcode = if is_unsigned {
                        x86_opcodes::DIV
                    } else {
                        x86_opcodes::IDIV
                    };
                    let mut div = MachineInstr::new(div_opcode);
                    div.size = op_size;
                    div.push_reg(src1_vr);
                    mbb.instructions.push(div);

                    // Step 4: mov def, (quotient or remainder)
                    //   DIV/IDIV: quotient in eax/rax, remainder in edx/rdx
                    let src_reg = if is_rem {
                        2 // edx/rdx holds remainder
                    } else {
                        0 // eax/rax holds quotient
                    };
                    let mut mov_def = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                    mov_def.size = op_size;
                    mov_def.operands.push(MachineOperand::PhysReg(src_reg));
                    mbb.instructions.push(mov_def);
                }
            }

            // === Select (ternary/conditional) ===
            Some(Opcode::Select) => {
                // Select: result = cond ? true_val : false_val
                // Operands: [cond, true_val, false_val]
                // The condition is an i1 boolean (from ICmp).
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                if def_vr.is_none() {
                    return;
                }
                let def = def_vr.unwrap();
                let cond_vid = inst.operands[0].borrow().vid as usize;
                let true_vid = inst.operands[1].borrow().vid as usize;
                let false_vid = inst.operands[2].borrow().vid as usize;
                // Use the true_val's type for data size; condition is always i1
                let data_ty = inst.operands[1].borrow().ty.clone();
                let op_size = match data_ty.integer_bit_width() {
                    32 | 1 => 4u8,
                    64 => 0u8,
                    _ => 0u8,
                };

                let cond_vr = vreg_map.get(&cond_vid).copied();
                let true_vr = vreg_map.get(&true_vid).copied();
                let false_vr = vreg_map.get(&false_vid).copied();

                if let (Some(cond_vr), Some(true_vr), Some(false_vr)) = (cond_vr, true_vr, false_vr)
                {
                    // Strategy: branchless CMOV
                    //   MOV def_vr, false_vr       ; default = false value
                    //   CMP cond_vr, 0             ; test condition
                    //   CMOVNE def_vr, true_vr     ; if cond != 0, overwrite with true value

                    // Step 1: MOV def, false_val (default value)
                    let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(def);
                    mov.size = op_size;
                    mov.push_reg(false_vr);
                    mbb.instructions.push(mov);

                    // Step 2: CMP cond, 0 (set condition flags)
                    let mut cmp = MachineInstr::new(x86_opcodes::CMP);
                    cmp.size = 4; // i1 condition is zero-extended to 32-bit
                    cmp.push_reg(cond_vr);
                    cmp.push_imm(0);
                    mbb.instructions.push(cmp);

                    // Step 3: CMOVNE def, true_val (conditionally overwrite)
                    let mut cmov = MachineInstr::new(x86_opcodes::CMOVNE).with_def(def);
                    cmov.size = op_size;
                    cmov.push_reg(true_vr);
                    mbb.instructions.push(cmov);
                }
            }

            // === Floating-Point Binary Operations ===
            Some(Opcode::FAdd) | Some(Opcode::FSub) | Some(Opcode::FMul) | Some(Opcode::FDiv)
            | Some(Opcode::FRem) => {
                let is_double = inst.ty.is_double_ty();
                let mc_opcode = ir_fp_binop_to_x86(opcode.unwrap(), is_double);
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let op0_vid = inst.operands[0].borrow().vid as usize;

                if let Some(def) = def_vr {
                    // Ensure dest is an XMM vreg (not GPR)
                    let xmm_def = Self::ensure_fp_vreg(mbb, def, is_double, mf);

                    // Handle first source operand
                    let src0_xmm = if let Some(&src0) = vreg_map.get(&op0_vid) {
                        Self::ensure_fp_vreg(mbb, src0, is_double, mf)
                    } else if inst.operands[0].borrow().is_constant() {
                        let tmp = mf.new_vreg();
                        let op0_borrowed = inst.operands[0].borrow();
                        Self::materialize_fp_constant(mbb, tmp, &op0_borrowed, mf);
                        tmp
                    } else {
                        def
                    };

                    // Move first source into result vreg (2-address form)
                    // Push both operands explicitly WITHOUT with_def() — see above for why.
                    if src0_xmm != def {
                        let mut mov = MachineInstr::new(if is_double {
                            x86_opcodes::MOVSD
                        } else {
                            x86_opcodes::MOVSS
                        });
                        mov.push_reg(src0_xmm); // operand[0] = source
                        mov.push_reg(xmm_def); // operand[1] = dest
                        mbb.instructions.push(mov);
                    }

                    // Handle the second operand
                    let op1 = &inst.operands[1];
                    let op1_borrowed = op1.borrow();
                    let src1_xmm = if op1_borrowed.is_constant() {
                        let tmp = mf.new_vreg();
                        Self::materialize_fp_constant(mbb, tmp, &op1_borrowed, mf);
                        tmp
                    } else {
                        let op1_vid = op1.borrow().vid as usize;
                        if let Some(&src1) = vreg_map.get(&op1_vid) {
                            Self::ensure_fp_vreg(mbb, src1, is_double, mf)
                        } else {
                            xmm_def
                        }
                    };

                    // Emit the FP operation (e.g., ADDSS)
                    if opcode.unwrap() != Opcode::FRem {
                        let mut mi = MachineInstr::new(mc_opcode);
                        mi.push_reg(src1_xmm); // source (operand[0])
                        mi.push_reg(xmm_def); // dest (operand[1])
                        mbb.instructions.push(mi);
                    }

                    // After the FP op, extract the XMM result back to a GPR
                    // so that subsequent code (loads/stores/returns) can treat
                    // the value as an integer bit pattern in a GPR.
                    let gpr_vreg = mf.new_vreg();
                    let mut extract = MachineInstr::new(if is_double {
                        x86_opcodes::MOVQ_FROM_XMM
                    } else {
                        x86_opcodes::MOVD_FROM_XMM
                    });
                    // MOVQ_FROM_XMM: operands[0]=XMM(src), operands[1]=GPR(dst)
                    extract.push_reg(xmm_def);
                    extract.push_reg(gpr_vreg);
                    mbb.instructions.push(extract);

                    // Remap the IR instruction's def vreg to the GPR vreg
                    vreg_map.insert(inst.vid as usize, gpr_vreg);
                }
            }

            // === Floating-Point Compare ===
            Some(Opcode::FCmp) => {
                let def_vr = vreg_map.get(&(inst.vid as usize)).copied();
                let op0_vid = inst.operands[0].borrow().vid as usize;
                let op1 = &inst.operands[1];

                // Parse predicate: "fcmp.olt", "fcmp.oeq", "fcmp.ult", etc.
                let pred = if inst.name.starts_with("fcmp.") {
                    let after = &inst.name[5..];
                    if let Some(dot) = after.find('.') {
                        &after[..dot]
                    } else {
                        after
                    }
                } else {
                    "oeq"
                };

                // Determine float vs double from the first operand's type
                let is_double = inst.operands[0].borrow().ty.is_double_ty();
                let cmp_opcode = if is_double {
                    x86_opcodes::UCOMISD
                } else {
                    x86_opcodes::UCOMISS
                };

                // Helper: load a GPR vreg into an XMM vreg via MOVQ/MOVD
                fn gpr_to_xmm(
                    mbb: &mut MachineBasicBlock,
                    mf: &mut MachineFunction,
                    gpr_vr: VirtReg,
                    is_double: bool,
                ) -> VirtReg {
                    let xmm_vr = mf.new_vreg();
                    let movx_op = if is_double {
                        x86_opcodes::MOVQ
                    } else {
                        x86_opcodes::MOVD
                    };
                    let mut movx = MachineInstr::new(movx_op);
                    movx.operands.push(MachineOperand::Reg(gpr_vr));
                    movx.operands.push(MachineOperand::Reg(xmm_vr));
                    // NOTE: do NOT set movx.def — rewrite_vregs inserts def at operand[0]
                    // which would corrupt the MOVQ operand order (operand[0]=GPR, operand[1]=XMM).
                    mbb.instructions.push(movx);
                    xmm_vr
                }

                // Resolve operand 0 — always move to XMM
                let src0_vreg = if let Some(&vr) = vreg_map.get(&op0_vid) {
                    gpr_to_xmm(mbb, mf, vr, is_double)
                } else if inst.operands[0].borrow().is_constant() {
                    let gpr_tmp = mf.new_vreg();
                    let op0_bor = inst.operands[0].borrow();
                    Self::materialize_fp_constant(mbb, gpr_tmp, &op0_bor, mf);
                    drop(op0_bor);
                    gpr_to_xmm(mbb, mf, gpr_tmp, is_double)
                } else {
                    return;
                };

                // Resolve operand 1 — always move to XMM
                let src1_vreg = if let Some(&vr) = vreg_map.get(&(op1.borrow().vid as usize)) {
                    gpr_to_xmm(mbb, mf, vr, is_double)
                } else if op1.borrow().is_constant() {
                    let gpr_tmp = mf.new_vreg();
                    let op1_bor = op1.borrow();
                    Self::materialize_fp_constant(mbb, gpr_tmp, &op1_bor, mf);
                    drop(op1_bor);
                    gpr_to_xmm(mbb, mf, gpr_tmp, is_double)
                } else {
                    return;
                };

                // Emit UCOMISS/UCOMISD to set flags
                // Encoder: operand[0]->r/m, operand[1]->reg.
                // Intel: UCOMISD reg,r/m compares reg with r/m: CF=1 if reg < r/m.
                // Push rhs first (r/m), lhs second (reg) so CF=1 when lhs < rhs.
                let mut cmp = MachineInstr::new(cmp_opcode);
                cmp.push_reg(src1_vreg); // r/m field = rhs
                cmp.push_reg(src0_vreg); // reg field = lhs
                mbb.instructions.push(cmp);

                // Map predicate to SETcc opcode
                let setcc_op = fp_pred_to_setcc(pred);

                // Emit SETcc + MOVZX to produce a 32-bit boolean result
                if let Some(def) = def_vr {
                    let mut set = MachineInstr::new(setcc_op).with_def(def);
                    mbb.instructions.push(set);
                    let mut zx = MachineInstr::new(x86_opcodes::MOVZX).with_def(def);
                    zx.push_reg(def);
                    mbb.instructions.push(zx);
                }
            }

            _ => {
                // Unknown opcode — skip
            }
        }
    }

    /// Ensure a vreg is usable as an XMM operand for SSE instructions.
    /// Since LOAD now emits MOVSS_LOAD which writes to XMM, the source vreg
    /// should already be in an XMM register. We just return it directly.
    fn ensure_fp_vreg(
        mbb: &mut MachineBasicBlock,
        vreg: VirtReg,
        _is_double: bool,
        _mf: &mut MachineFunction,
    ) -> VirtReg {
        vreg
    }

    /// Materialize a floating-point constant into a vreg.
    /// The constant name is the raw IEEE 754 bit pattern stored as a decimal
    /// string (from const_float/const_double in constants.rs). Parse it
    /// directly as i64 — DO NOT go through f64 which loses precision for
    /// the large integers used as bit patterns.
    fn materialize_fp_constant(
        mbb: &mut MachineBasicBlock,
        def: VirtReg,
        operand: &std::cell::Ref<'_, Value>,
        mf: &mut MachineFunction,
    ) {
        let val_str = operand.name.clone();
        let is_double = operand.ty.is_double_ty();
        // The constant name is the raw bit pattern as a decimal u64 string.
        // Parse it directly as i64 (signed cast of bit pattern).
        let bits: i64 = val_str.parse().unwrap_or(0);
        // Load the bit pattern into a GPR (rax = physreg 0)
        let mut mov = MachineInstr::new(x86_opcodes::MOV);
        mov.operands.push(MachineOperand::PhysReg(0)); // rax
        mov.size = if is_double { 0u8 } else { 4u8 };
        mov.push_imm(bits);
        mbb.instructions.push(mov);
        // Copy from GPR to def vreg via integer MOV (def vreg holds bit pattern)
        let mut mov_def = MachineInstr::new(x86_opcodes::MOV).with_def(def);
        mov_def.operands.push(MachineOperand::PhysReg(0)); // src = rax
        mbb.instructions.push(mov_def);
    }
}

/// Map FP binary opcode to X86 SSE opcode.
fn ir_fp_binop_to_x86(op: Opcode, is_double: bool) -> u32 {
    match op {
        Opcode::FAdd => {
            if is_double {
                x86_opcodes::ADDSD
            } else {
                x86_opcodes::ADDSS
            }
        }
        Opcode::FSub => {
            if is_double {
                x86_opcodes::SUBSD
            } else {
                x86_opcodes::SUBSS
            }
        }
        Opcode::FMul => {
            if is_double {
                x86_opcodes::MULSD
            } else {
                x86_opcodes::MULSS
            }
        }
        Opcode::FDiv => {
            if is_double {
                x86_opcodes::DIVSD
            } else {
                x86_opcodes::DIVSS
            }
        }
        _ => {
            if is_double {
                x86_opcodes::ADDSD
            } else {
                x86_opcodes::ADDSS
            }
        }
    }
}

/// Map an FP comparison predicate name to a SETcc opcode.
fn fp_pred_to_setcc(pred: &str) -> u32 {
    match pred {
        "oeq" | "ueq" => x86_opcodes::SETE,
        "one" | "une" => x86_opcodes::SETNE,
        "olt" | "ult" => x86_opcodes::SETB,
        "ole" | "ule" => x86_opcodes::SETBE,
        "ogt" | "ugt" => x86_opcodes::SETA,
        "oge" | "uge" => x86_opcodes::SETAE,
        "ord" => x86_opcodes::SETNP, // ordered = no parity flag
        "uno" => x86_opcodes::SETP,  // unordered = parity flag
        _ => x86_opcodes::SETE,
    }
}

/// Map IR binary opcode to X86 machine opcode.
fn ir_binop_to_x86(op: Opcode) -> u32 {
    match op {
        Opcode::Add => x86_opcodes::ADD,
        Opcode::Sub => x86_opcodes::SUB,
        Opcode::Mul => x86_opcodes::MUL, // Note: MUL in x86 only takes one operand; IMUL takes two
        Opcode::And => x86_opcodes::AND,
        Opcode::Or => x86_opcodes::OR,
        Opcode::Xor => x86_opcodes::XOR,
        Opcode::Shl => x86_opcodes::SHL,
        Opcode::LShr => x86_opcodes::SHR,
        Opcode::AShr => x86_opcodes::SAR,
        _ => x86_opcodes::ADD, // fallback
    }
}

// ============================================================================
// Register Allocator (simple, legacy)
// ============================================================================

/// Simple linear-scan register allocator.
pub struct RegisterAllocator {
    pub assignments: HashMap<VirtReg, PhysReg>,
    available: Vec<PhysReg>,
}

impl RegisterAllocator {
    pub fn new() -> Self {
        Self {
            assignments: HashMap::new(),
            // X86-64 GPRs: rax, rcx, rdx, rsi, rdi, r8-r15
            // Callee-saved first (rbx, r14-r15) to survive CALL clobbers,
            // then caller-saved (rax, rcx, rdx, rsi, rdi, r8-r11).
            // NOTE: rbp (5) is excluded — it's the frame pointer.
            //       rsp (4) is excluded — it's the stack pointer.
            available: vec![3, 12, 13, 14, 15, 0, 1, 2, 6, 7, 8, 9, 10, 11],
        }
    }

    pub fn allocate(&mut self, mf: &mut MachineFunction) {
        // First pass: count total unique vregs (defs + operands)
        let mut all_vregs: Vec<VirtReg> = Vec::new();
        for bb in &mf.blocks {
            for mi in &bb.instructions {
                if let Some(def) = mi.def {
                    if !all_vregs.contains(&def) {
                        all_vregs.push(def);
                    }
                }
                for op in &mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        if !all_vregs.contains(&vr) {
                            all_vregs.push(vr);
                        }
                    }
                }
            }
        }

        // Assign unique physregs to each vreg, reusing available pool with no wrap-around
        let mut next_phys = 0usize;
        for &vr in &all_vregs {
            if !self.assignments.contains_key(&vr) {
                let p = if next_phys < self.available.len() {
                    self.available[next_phys]
                } else {
                    // Out of unique registers — reuse from the pool based on vreg identity
                    // This creates a predictable mapping: vr N gets available[N mod len]
                    // Live-range conflicts are possible but the mapping is at least deterministic
                    // Use a scramble to spread consecutive vregs across different physregs,
                    // reducing collision probability compared to plain modulo.
                    self.available[(vr.wrapping_mul(7) as usize) % self.available.len()]
                };
                self.assignments.insert(vr, p);
                next_phys += 1;
            }
        }

        // Second pass: replace all vreg references with physregs
        for bb in &mut mf.blocks {
            for mi in &mut bb.instructions {
                if let Some(def) = mi.def {
                    if let Some(&phys) = self.assignments.get(&def) {
                        mi.operands.insert(0, MachineOperand::PhysReg(phys));
                    }
                }

                for op in &mut mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        if let Some(&phys) = self.assignments.get(&vr) {
                            *op = MachineOperand::PhysReg(phys);
                        }
                    }
                }
            }
        }
    }
}

impl Default for RegisterAllocator {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Assembly Printer
// ============================================================================

/// Assembly printer: emits X86 assembly from MachineFunction.
pub struct AsmPrinter {
    pub output: String,
}

impl AsmPrinter {
    pub fn new() -> Self {
        Self {
            output: String::new(),
        }
    }

    pub fn print_function(&mut self, mf: &MachineFunction) {
        self.output.push_str(&format!("\t.globl {}\n", mf.name));
        self.output
            .push_str(&format!("\t.type {}, @function\n", mf.name));
        self.output.push_str(&format!("{}:\n", mf.name));

        for bb in &mf.blocks {
            if !bb.name.is_empty() && bb.name != "entry" {
                self.output.push_str(&format!(".L{}:\n", bb.name));
            }
            for mi in &bb.instructions {
                self.print_instr(mi);
            }
        }
    }

    fn print_instr(&mut self, mi: &MachineInstr) {
        let mnemonic = crate::mc_streamer::x86_mnemonic(mi.opcode);
        self.output.push_str(&format!("\t{}", mnemonic));

        let mut first = true;
        for op in &mi.operands {
            if first {
                self.output.push('\t');
                first = false;
            } else {
                self.output.push_str(", ");
            }
            match op {
                MachineOperand::PhysReg(r) => self
                    .output
                    .push_str(&format!("%{}", crate::mc_streamer::x86_reg_name(*r))),
                MachineOperand::Reg(r) => self.output.push_str(&format!("%%v{}", r)),
                MachineOperand::Imm(i) => self.output.push_str(&format!("${}", i)),
                MachineOperand::Label(l) => self.output.push_str(&format!(".L{}", l)),
                MachineOperand::Global(g) => self.output.push_str(g),
            }
        }
        self.output.push('\n');
    }
}

impl Default for AsmPrinter {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Convenience: Compile a function
// ============================================================================

/// Compile an IR function to X86-64 assembly text.
pub fn compile_function(func: &ValueRef) -> String {
    let f = func.borrow();
    let mut mf = MachineFunction::new(&f.name);
    InstructionSelector::select(&mut mf, func);
    let mut ra = RegisterAllocator::new();
    ra.allocate(&mut mf);
    let mut printer = AsmPrinter::new();
    printer.print_function(&mf);
    printer.output
}

// ============================================================================
// Target Register Info — Describes physical register file for a target
// ============================================================================

/// Target-specific register information.
///
/// Describes the physical register file for a target architecture:
/// number of GPRs/FPRs, reserved registers, calling convention s aves,
/// and register size in bytes.
#[derive(Debug, Clone)]
pub struct TargetRegInfo {
    /// Number of general-purpose registers.
    pub gpr_count: u32,
    /// Number of floating-point registers.
    pub fpr_count: u32,
    /// Registers reserved for special purposes (e.g., stack pointer).
    pub reserved: Vec<PhysReg>,
    /// Callee-saved registers (the callee must preserve these).
    pub callee_saved: Vec<PhysReg>,
    /// Caller-saved registers (the caller must save if needed).
    pub caller_saved: Vec<PhysReg>,
    /// Size of each register in bytes.
    pub reg_size: u32,
}

impl TargetRegInfo {
    /// Create target register info for X86-64.
    ///
    /// X86-64 has 16 GPRs (rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8-r15)
    /// and 16 XMM registers (xmm0-xmm15).
    /// Registers are numbered: rax=0, rcx=1, rdx=2, rbx=3, rsp=4, rbp=5,
    /// rsi=6, rdi=7, r8=8, r9=9, r10=10, r11=11, r14=12, r13=13, r14=14, r15=15
    pub fn for_x86_64() -> Self {
        Self {
            gpr_count: 16,
            fpr_count: 16,
            reserved: vec![4],                               // rsp is reserved
            callee_saved: vec![3, 5, 12, 13, 14, 15],        // rbx, rbp, r14-r15
            caller_saved: vec![0, 1, 2, 6, 7, 8, 9, 10, 11], // rax, rcx, rdx, rsi, rdi, r8-r11
            reg_size: 8,
        }
    }

    /// Create target register info for AArch64.
    ///
    /// AArch64 has 32 GPRs (x0-x31) and 32 FPRs (v0-v31).
    /// Registers are numbered: x0=0 through x30=30, xzr/sp=31.
    /// Callee-saved: x19-x29. Caller-saved: x0-x18.
    pub fn for_aarch64() -> Self {
        Self {
            gpr_count: 32,
            fpr_count: 32,
            reserved: vec![31],                // sp/xzr
            callee_saved: (19..=29).collect(), // x19-x29
            caller_saved: {
                let mut v: Vec<u32> = (0..=18).collect();
                v.push(30); // x30 = lr
                v
            },
            reg_size: 8,
        }
    }

    /// Create target register info for RISC-V 64 (RV64I).
    ///
    /// RISC-V has 32 GPRs (x0-x31) and 32 FPRs (f0-f31).
    /// Registers are numbered: zero=0, ra=1, sp=2, gp=3, tp=4,
    /// t0-t2=5-7, s0/fp=8, s1=9, a0-a7=10-17, s2-s11=18-27, t3-t6=28-31.
    /// Callee-saved: x8-x9, x18-x27. Caller-saved: x1, x5-x7, x10-x17, x28-x31.
    pub fn for_riscv64() -> Self {
        Self {
            gpr_count: 32,
            fpr_count: 32,
            reserved: vec![0, 2, 3, 4], // zero, sp, gp, tp
            callee_saved: {
                let mut v: Vec<u32> = (8..=9).collect(); // s0-s1
                v.extend(18..=27); // s2-s11
                v
            },
            caller_saved: {
                let mut v: Vec<u32> = vec![1]; // ra
                v.extend(5..=7); // t0-t2
                v.extend(10..=17); // a0-a7
                v.extend(28..=31); // t3-t6
                v
            },
            reg_size: 8,
        }
    }

    /// Check if a physical register is allocatable (not reserved).
    pub fn is_allocatable(&self, reg: PhysReg) -> bool {
        !self.reserved.contains(&reg)
    }

    /// Get the list of allocatable registers (excluding reserved).
    /// Includes GPRs (0-15) and XMM registers (64-79) for x86-64.
    pub fn allocatable_regs(&self) -> Vec<PhysReg> {
        let gprs: Vec<PhysReg> = (0..self.gpr_count)
            .filter(|r| self.is_allocatable(*r))
            .collect();
        // Add XMM registers (64-79) for FP support
        let xmms: Vec<PhysReg> = (64..(64 + self.fpr_count))
            .filter(|r| self.is_allocatable(*r))
            .collect();
        [gprs.as_slice(), xmms.as_slice()].concat()
    }
}

// ============================================================================
// Live Intervals — Data structure for register allocation
// ============================================================================

/// A live interval for a virtual register.
///
/// Tracks the range of instruction indices where a virtual register
/// is live, along with specific use and definition positions.
#[derive(Debug, Clone)]
pub struct LiveInterval {
    /// The virtual register this interval represents.
    pub vreg: VirtReg,
    /// First instruction index where the register becomes live.
    pub start: u32,
    /// Last instruction index where the register is still live.
    pub end: u32,
    /// All use positions (instruction indices).
    pub uses: Vec<u32>,
    /// All definition positions (instruction indices).
    pub defs: Vec<u32>,
}

impl LiveInterval {
    /// Create a new live interval.
    pub fn new(vreg: VirtReg) -> Self {
        Self {
            vreg,
            start: u32::MAX,
            end: 0,
            uses: Vec::new(),
            defs: Vec::new(),
        }
    }

    /// Check if this interval overlaps with another.
    pub fn overlaps(&self, other: &LiveInterval) -> bool {
        self.start <= other.end && other.start <= self.end
    }

    /// Check if this interval covers a given instruction position.
    pub fn covers(&self, pos: u32) -> bool {
        self.start <= pos && pos <= self.end
    }

    /// Check if the register is live at a specific position.
    pub fn live_at(&self, pos: u32) -> bool {
        self.covers(pos)
    }

    /// Get the length of this interval.
    pub fn length(&self) -> u32 {
        if self.end >= self.start {
            self.end - self.start
        } else {
            0
        }
    }

    /// Update the interval bounds from use and def positions.
    pub fn recompute_bounds(&mut self) {
        if let Some(&min_pos) = self.defs.iter().chain(self.uses.iter()).min() {
            self.start = min_pos;
        }
        if let Some(&max_pos) = self.defs.iter().chain(self.uses.iter()).max() {
            self.end = max_pos;
        }
    }
}

// ============================================================================
// Register Allocator Result
// ============================================================================

/// Statistics from the register allocation phase.
#[derive(Debug, Clone)]
pub struct RegAllocResult {
    /// Whether allocation succeeded (all vregs assigned without errors).
    pub success: bool,
    /// Number of spills inserted.
    pub spills: usize,
    /// Number of reloads inserted.
    pub reloads: usize,
    /// Number of copy instructions coalesced away.
    pub copies_coalesced: usize,
}

impl RegAllocResult {
    /// Create a default successful result.
    pub fn success() -> Self {
        Self {
            success: true,
            spills: 0,
            reloads: 0,
            copies_coalesced: 0,
        }
    }

    /// Create a failure result.
    pub fn failure() -> Self {
        Self {
            success: false,
            spills: 0,
            reloads: 0,
            copies_coalesced: 0,
        }
    }
}

// ============================================================================
// Full Register Allocator with Linear Scan and Spilling
// ============================================================================

/// Comprehensive register allocator implementing linear scan with spilling.
///
/// Algorithm overview:
/// 1. Compute live intervals for all virtual registers
/// 2. Sort intervals by start position
/// 3. For each interval, try to find a free physical register
/// 4. If no free register, spill the interval with the farthest end
/// 5. Insert spill/reload code for evicted registers
/// 6. Coalesce copy instructions
/// 7. Rewrite frame indices for stack slots
pub struct RegAlloc {
    /// Mapping from virtual registers to assigned physical registers.
    pub assignments: HashMap<VirtReg, PhysReg>,
    /// Virtual registers that were spilled to the stack.
    pub spilled: Vec<VirtReg>,
    /// Stack frame offsets for spilled registers (negative offsets from rbp).
    pub spill_slots: HashMap<VirtReg, i64>,
    /// Available physical registers for allocation.
    pub available: Vec<PhysReg>,
    /// Current frame offset (negative, grows downward).
    pub frame_offset: i64,
    /// Target register information.
    pub target: TargetRegInfo,
    /// Physical registers that are used explicitly as operands at specific instruction indices.
    /// These physregs are blocked (unavailable for allocation) during those instructions.
    /// Each entry is (physreg, start_global_idx, end_global_idx).
    pub physreg_uses: Vec<(PhysReg, u32, u32)>,
    /// Register class assignment for each virtual register.
    /// Tracks whether a vreg needs a GPR or XMM register.
    pub vreg_classes: HashMap<VirtReg, RegClass>,
}

impl RegAlloc {
    /// Create a new register allocator for the given target.
    pub fn new(target: TargetRegInfo) -> Self {
        Self::new_with_frame_offset(target, 0)
    }

    /// Create a new register allocator with a custom initial frame offset.
    /// Set `initial_frame_offset` to a negative value to start spill slots
    /// below alloca slots (e.g., -((max_alloca_vid + 2) * 8)).
    pub fn new_with_frame_offset(target: TargetRegInfo, initial_frame_offset: i64) -> Self {
        let available = target.allocatable_regs();
        Self {
            assignments: HashMap::new(),
            spilled: Vec::new(),
            spill_slots: HashMap::new(),
            available,
            frame_offset: initial_frame_offset,
            target,
            physreg_uses: Vec::new(),
            vreg_classes: HashMap::new(),
        }
    }

    /// Run full register allocation on a machine function.
    ///
    /// Returns a `RegAllocResult` with statistics about the allocation.
    pub fn allocate(&mut self, mf: &mut MachineFunction) -> RegAllocResult {
        eprintln!("RA_DEBUG: func={} Step 0 compute_vreg_classes", mf.name);
        // Step 0: Compute register class constraints for each vreg
        // (XMM vs GPR) based on instruction usage patterns.
        self.compute_vreg_classes(mf);
        eprintln!("RA_DEBUG: func={} Step 1 compute_live_intervals", mf.name);

        // Step 1: Compute live intervals
        let mut intervals = self.compute_live_intervals(mf);
        eprintln!(
            "RA_DEBUG: func={} intervals count={}",
            mf.name,
            intervals.len()
        );

        // Step 1.5: Extend intervals that span multiple blocks to cover their
        // full block range. Linear block ordering hides loop back-edges: a vreg
        // defined in for.body (high idx) and used in for.cond (low idx) has the
        // use appear before the def in global index order. By extending intervals
        // to span the full block chain, linear scan sees the correct live range.
        {
            let mut global_idx: u32 = 0;
            let mut block_limits: Vec<(u32, u32)> = Vec::new();
            for bb in &mf.blocks {
                let start = global_idx;
                global_idx += bb.instructions.len() as u32;
                let end = global_idx - 1;
                block_limits.push((start, end));
            }

            // Collect set of vregs used as pointer operands in LOAD/STORE.
            // These are alloca-derived pointers that may be used across
            // basic-block boundaries (forward jumps) where the linear index
            // places their use BEFORE later vreg defs.  We conservatively
            // extend such pointer vregs to cover the full function range.
            let mut pointer_vregs: std::collections::HashSet<VirtReg> =
                std::collections::HashSet::new();
            for bb in &mf.blocks {
                for mi in &bb.instructions {
                    match mi.opcode {
                        x86_opcodes::LOAD | x86_opcodes::STORE => {
                            // operands[0] = source/ptr for LOAD, operands[0] = ptr for STORE
                            if let Some(MachineOperand::Reg(vr)) = mi.operands.first() {
                                pointer_vregs.insert(*vr);
                            }
                        }
                        _ => {}
                    }
                }
            }

            let func_start = block_limits.first().map(|&(fs, _)| fs).unwrap_or(0);
            let func_end = block_limits.last().map(|&(_, le)| le).unwrap_or(0);
            if func_start != 0 || func_end != 0 {
                let func_start = func_start;
                let func_end = func_end;
                for li in intervals.iter_mut() {
                    if pointer_vregs.contains(&li.vreg) {
                        // Extend pointer vregs to cover the entire function
                        if func_start < li.start {
                            li.start = func_start;
                        }
                        if func_end > li.end {
                            li.end = func_end;
                        }
                    } else {
                        let mut in_blocks = Vec::new();
                        for (bi, bb) in mf.blocks.iter().enumerate() {
                            for mi in &bb.instructions {
                                if mi.def == Some(li.vreg)
                                    || mi
                                        .operands
                                        .iter()
                                        .any(|op| matches!(op, MachineOperand::Reg(vr) if *vr == li.vreg))
                                {
                                    if !in_blocks.contains(&bi) {
                                        in_blocks.push(bi);
                                    }
                                }
                            }
                        }

                        // If the vreg appears in multiple blocks, extend from the
                        // first block's first instruction to the last block's last
                        // instruction. This handles loop-carried liveness.
                        if in_blocks.len() >= 2 {
                            let first = in_blocks.iter().min().copied().unwrap_or(0);
                            let last = in_blocks.iter().max().copied().unwrap_or(0);
                            if let Some(&(fs, _)) = block_limits.get(first) {
                                if let Some(&(_, le)) = block_limits.get(last) {
                                    if fs < li.start {
                                        li.start = fs;
                                    }
                                    if le > li.end {
                                        li.end = le;
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }

        eprintln!("RA_DEBUG: func={} Step 2 linear_scan", mf.name);
        // Step 2: Run linear scan register allocation
        let success = self.linear_scan_allocate(mf, &mut intervals);
        if !success {
            return RegAllocResult::failure();
        }

        eprintln!("RA_DEBUG: func={} Step 2.5 verify", mf.name);
        // Step 2.5: Verify register allocation correctness
        // Check that no two vregs with overlapping live intervals
        // are assigned the same physical register.
        self.verify_allocation(&intervals);

        // Step 3: Eliminate dead code — disabled because it incorrectly removes
        // instructions whose defs are used in other blocks when registers are
        // reallocated (stealing) across basic blocks.
        // self.eliminate_dead_code(mf);

        eprintln!("RA_DEBUG: func={} Step 4 coalesce", mf.name);
        // Step 4: Coalesce copies
        let coalesced = self.coalesce_copies(mf);

        eprintln!("RA_DEBUG: func={} Step 5 rewrite_vregs", mf.name);
        // Step 5: Rewrite vregs to physregs in all instructions
        self.rewrite_vregs(mf);

        // Step 6: Add callee-saved register spills
        // NOTE: Skipped — the pipeline (module_to_object_bytes) handles
        // prologue/epilogue separately, and its epilogue (mov rsp,rbp; pop rbp)
        // conflicts with add_callee_saved_spills' POP insertion order.
        // self.add_callee_saved_spills(mf);

        eprintln!("RA_DEBUG: func={} Step 7 frame_indices", mf.name);
        // Step 7: Rewrite frame indices
        let fo = self.frame_offset;
        self.rewrite_frame_indices(mf, fo);

        eprintln!(
            "RA_DEBUG: func={} DONE (spills={})",
            mf.name,
            self.spilled.len()
        );
        let spills = self.spilled.len();
        let reloads = self.spilled.len(); // one reload per spill for now

        RegAllocResult {
            success: true,
            spills,
            reloads,
            copies_coalesced: coalesced,
        }
    }

    /// Compute live intervals for all virtual registers in the function.
    ///
    /// Scans every instruction in every block, assigns a global index
    /// to each instruction, and tracks the first definition and last use
    /// of each virtual register.
    pub fn compute_live_intervals(&mut self, mf: &MachineFunction) -> Vec<LiveInterval> {
        self.physreg_uses.clear();
        let mut intervals: HashMap<VirtReg, LiveInterval> = HashMap::new();
        let mut global_idx: u32 = 0;

        for bb in &mf.blocks {
            for mi in &bb.instructions {
                // Record uses
                for op in &mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        let li = intervals.entry(vr).or_insert_with(|| LiveInterval::new(vr));
                        li.uses.push(global_idx);
                        if global_idx < li.start {
                            li.start = global_idx;
                        }
                        if global_idx > li.end {
                            li.end = global_idx;
                        }
                    }
                }

                // Record defs
                if let Some(def) = mi.def {
                    let li = intervals
                        .entry(def)
                        .or_insert_with(|| LiveInterval::new(def));
                    li.defs.push(global_idx);
                    if global_idx < li.start {
                        li.start = global_idx;
                    }
                    if global_idx > li.end {
                        li.end = global_idx;
                    }
                }

                // Record physical register usage (so the allocator knows
                // these physregs are busy at this instruction index)
                // For CALL instructions, mark ALL caller-saved GPRs as busy
                // (they are implicitly clobbered by the call, SysV x86-64 ABI).
                if mi.opcode == x86_opcodes::CALL {
                    // Caller-saved GPRs: rax(0), rcx(1), rdx(2), rsi(6), rdi(7),
                    // r8(8), r9(9), r10(10), r11(11)
                    let caller_saved: [PhysReg; 9] = [0, 1, 2, 6, 7, 8, 9, 10, 11];
                    for &pr in &caller_saved {
                        self.physreg_uses.push((pr, global_idx, global_idx));
                    }
                    // Also mark caller-saved XMM registers (xmm0-xmm15)
                    for xmm in 64..80u32 {
                        self.physreg_uses.push((xmm, global_idx, global_idx));
                    }
                    // Also mark callee-saved GPRs as busy across calls because
                    // the pipeline skips add_callee_saved_spills (Step 6), so
                    // callees may clobber rbx/r14/r15 without saving/restoring.
                    // This forces any vreg assigned to a callee-saved physreg
                    // to spill before the call and reload after, restoring the
                    // value correctly.  See tiny_vec struct field codegen bug.
                    let callee_saved: [PhysReg; 4] = [3, 12, 13, 14]; // rbx, r14-r15
                    for &pr in &callee_saved {
                        self.physreg_uses.push((pr, global_idx, global_idx));
                    }
                }
                for op in &mi.operands {
                    if let MachineOperand::PhysReg(pr) = *op {
                        self.physreg_uses.push((pr, global_idx, global_idx));
                    }
                }

                global_idx += 1;
            }
        }

        // Also include vregs that appear only in def positions
        for bb in &mf.blocks {
            for mi in &bb.instructions {
                if let Some(def) = mi.def {
                    intervals
                        .entry(def)
                        .or_insert_with(|| LiveInterval::new(def));
                }
            }
        }

        intervals.into_values().collect()
    }

    /// Run linear scan register allocation.
    ///
    /// Sorts intervals by start position, maintains an active list
    /// sorted by end position, and allocates physical registers.
    /// When no register is free, reuses the register from the active interval with
    /// the farthest end position without emitting spill/reload code.
    ///
    /// Linear scan register allocation with proper spilling.
    ///
    /// When no physical register is free, the interval with the farthest
    /// end is spilled to a stack slot. The spill/reload code is inserted
    /// during the `rewrite_vregs` phase.
    pub fn linear_scan_allocate(
        &mut self,
        _mf: &mut MachineFunction,
        intervals: &mut Vec<LiveInterval>,
    ) -> bool {
        // Sort intervals by (start, end, vreg) for total deterministic order.
        // Sorting by start alone is non-deterministic when multiple intervals
        // share the same start (HashMap→Vec→collect preserves insertion order,
        // which depends on hash randomization).
        intervals.sort_by_key(|li| (li.start, li.end, li.vreg));

        // Active list: (phys_reg, interval_index)
        let mut active: Vec<(PhysReg, usize)> = Vec::new();

        for i in 0..intervals.len() {
            let li = &intervals[i];

            // Step 1: Expire old intervals
            // Remove intervals from active whose end < current start
            active.retain(|&(_, active_idx)| {
                let active_li = &intervals[active_idx];
                active_li.end >= li.start
            });

            // Step 2: Try to find a free register
            let mut used_regs: HashSet<PhysReg> = active.iter().map(|&(r, _)| r).collect();
            for &(pr, use_start, use_end) in &self.physreg_uses {
                if use_start <= li.end && use_end >= li.start {
                    used_regs.insert(pr);
                }
            }
            let free_reg = self.find_free_reg_for(li.vreg, &used_regs);

            if let Some(reg) = free_reg {
                // Assign register
                self.assignments.insert(li.vreg, reg);
                active.push((reg, i));
            } else {
                // Step 3: No free register — conservatively spill the current
                // interval rather than evicting an active one. Active-interval
                // eviction is unsafe when liveness tracking misses implicit uses
                // (memory operands, CALL argument setup, address temporaries).
                if !self.spill_slots.contains_key(&li.vreg) {
                    self.frame_offset -= 8;
                    self.spill_slots.insert(li.vreg, self.frame_offset);
                    self.spilled.push(li.vreg);
                }
                // No assignment — this vreg lives on the stack
            }
        }

        true
    }

    /// Verify register allocation correctness: check for interference violations.
    /// No two vregs with overlapping live intervals should share a physreg.
    fn verify_allocation(&self, intervals: &[LiveInterval]) {
        for i in 0..intervals.len() {
            for j in (i + 1)..intervals.len() {
                let a = &intervals[i];
                let b = &intervals[j];

                // Check for interval overlap
                let overlap = a.start <= b.end && b.start <= a.end;
                if !overlap {
                    continue;
                }

                let Some(ra) = self.assignments.get(&a.vreg) else {
                    continue;
                };
                let Some(rb) = self.assignments.get(&b.vreg) else {
                    continue;
                };

                if ra == rb {
                    // Only warn, don't panic — we may have spill clusters
                    // where one vreg is spilled before the conflict point.
                    // The verifier is conservative here.
                    panic!(
                        "RA interference: vregs {:?} and {:?} overlap ({}..{}/{}..{}) both assigned {:?}",
                        a.vreg, b.vreg, a.start, a.end, b.start, b.end, ra
                    );
                }
            }
        }
    }

    /// Spill a virtual register: assign a stack slot and insert spill/reload code.
    ///
    /// Returns the stack frame offset for the spill slot.
    pub fn spill_vreg(
        &mut self,
        mf: &mut MachineFunction,
        vreg: VirtReg,
        intervals: &[LiveInterval],
    ) -> i64 {
        if self.spill_slots.contains_key(&vreg) {
            return self.spill_slots[&vreg];
        }

        // Allocate a new spill slot
        self.frame_offset -= self.target.reg_size as i64;
        let offset = self.frame_offset;
        self.spill_slots.insert(vreg, offset);
        self.spilled.push(vreg);

        // Find the interval for this vreg
        for li in intervals {
            if li.vreg == vreg {
                // Insert spill after each def
                for &def_pos in &li.defs {
                    self.insert_spill(mf, vreg, def_pos as usize + 1);
                }

                // Insert reload before each use
                for &use_pos in &li.uses {
                    // Skip if the use position is also a def (redundant)
                    if !li.defs.contains(&use_pos) {
                        self.insert_reload(mf, vreg, use_pos as usize);
                    }
                }
                break;
            }
        }

        offset
    }

    /// Insert a spill (store) of a virtual register to its stack slot,
    /// before the instruction at the given global index.
    pub fn insert_spill(&mut self, mf: &mut MachineFunction, vreg: VirtReg, before_inst: usize) {
        let mut global_idx: usize = 0;
        let offset = self
            .spill_slots
            .get(&vreg)
            .copied()
            .unwrap_or(self.frame_offset);

        // Pre-allocate a temp scratch vreg assigned to r11.
        // We use PUSH to save vreg to the CPU stack (avoids reg-sharing conflicts),
        // compute address in vreg, POP the saved value into r11, then STORE.
        let tmp = mf.new_vreg();
        self.assignments.insert(tmp, 11);

        for bb in &mut mf.blocks {
            let mut insert_idx = None;
            for (i, _) in bb.instructions.iter().enumerate() {
                if global_idx == before_inst {
                    insert_idx = Some(i);
                    break;
                }
                global_idx += 1;
            }

            if let Some(pos) = insert_idx {
                // 1. PUSH vreg  — save value to CPU stack
                let mut push = MachineInstr::new(x86_opcodes::PUSH);
                push.push_reg(vreg);
                bb.instructions.insert(pos, push);
                // 2. MOV vreg, rbp  — compute frame base
                let mut base = MachineInstr::new(x86_opcodes::MOV).with_def(vreg);
                base.operands.push(MachineOperand::PhysReg(5));
                bb.instructions.insert(pos + 1, base);
                // 3. ADD vreg, offset  — compute [rbp+offset] in vreg
                let mut adj = MachineInstr::new(x86_opcodes::ADD).with_def(vreg);
                adj.push_imm(offset);
                bb.instructions.insert(pos + 2, adj);
                // 4. POP tmp  — restore saved value into r11
                let mut pop = MachineInstr::new(x86_opcodes::POP);
                pop.operands.push(MachineOperand::Reg(tmp));
                bb.instructions.insert(pos + 3, pop);
                // 5. STORE [vreg], tmp  — store saved value to [rbp+offset]
                let mut store = MachineInstr::new(x86_opcodes::STORE);
                store.push_reg(vreg); // ptr = rbp+offset
                store.push_reg(tmp); // val = original value
                bb.instructions.insert(pos + 4, store);
                return;
            }

            // Advance past this block's instructions
            global_idx += bb.instructions.len();
        }
    }

    /// Insert a reload (load) of a virtual register from its stack slot,
    /// before the instruction at the given global index.
    pub fn insert_reload(&mut self, mf: &mut MachineFunction, vreg: VirtReg, before_inst: usize) {
        let mut global_idx: usize = 0;
        let offset = self
            .spill_slots
            .get(&vreg)
            .copied()
            .unwrap_or(self.frame_offset);

        for bb in &mut mf.blocks {
            let mut insert_idx = None;
            for (i, _) in bb.instructions.iter().enumerate() {
                if global_idx == before_inst {
                    insert_idx = Some(i);
                    break;
                }
                global_idx += 1;
            }

            if let Some(pos) = insert_idx {
                // MOV vreg, [rbp + offset]  — load from stack slot
                // Use LEA to compute address into a temp reg, then LOAD
                // For now, MOV vreg, rbp; ADD vreg, offset; LOAD vreg, [vreg]
                let mut p = pos;
                let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(vreg);
                mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                bb.instructions.insert(p, mov);
                p += 1;
                let mut add = MachineInstr::new(x86_opcodes::ADD).with_def(vreg);
                add.push_imm(offset);
                bb.instructions.insert(p, add);
                p += 1;
                let mut load = MachineInstr::new(x86_opcodes::LOAD).with_def(vreg);
                load.push_reg(vreg); // address in vreg
                bb.instructions.insert(p, load);
                return;
            }

            global_idx += bb.instructions.len();
        }
    }

    /// Find a free physical register not in the used set at a given position.
    /// Considers the register class of the vreg (if known) and only returns
    /// registers of the matching class (GPR or XMM).
    fn find_free_reg_in(
        &self,
        _intervals: &[LiveInterval],
        _at_pos: u32,
        used: &HashSet<PhysReg>,
    ) -> Option<PhysReg> {
        // If we have class info for any vreg in `used`, try to find a register
        // from the complementary pool. Default to GPR pool if unknown.
        let candidates = self.regs_for_class(RegClass::Gpr64);
        candidates.iter().copied().find(|r| !used.contains(r))
    }

    /// Find a free physical register for a specific virtual register,
    /// considering its register class constraint.
    fn find_free_reg_for(&self, vreg: VirtReg, used: &HashSet<PhysReg>) -> Option<PhysReg> {
        let class = self
            .vreg_classes
            .get(&vreg)
            .copied()
            .unwrap_or(RegClass::Gpr64);
        let candidates = self.regs_for_class(class);
        candidates.iter().copied().find(|r| !used.contains(r))
    }

    /// Get the list of allocatable physical registers that match a given register class.
    fn regs_for_class(&self, class: RegClass) -> Vec<PhysReg> {
        match class {
            RegClass::Xmm => self
                .available
                .iter()
                .copied()
                .filter(|r| *r >= 64 && *r < 80)
                .collect(),
            _ => self.available.iter().copied().filter(|r| *r < 16).collect(),
        }
    }

    /// Compute register class for each virtual register based on instruction usage.
    /// Scans all machine instructions to determine whether each vreg needs:
    ///   - XMM (used in SSE register-to-register ops like MOVSS, ADDSS)
    ///   - GPR (used in standard integer ops like MOV, ADD, LOAD, STORE)
    ///
    /// A vreg that is used in both contexts gets GPR (default).
    pub fn compute_vreg_classes(&mut self, mf: &MachineFunction) {
        // SSE binary opcodes that require XMM operands for BOTH operands
        let sse_binary_ops: std::collections::HashSet<u32> = [
            x86_opcodes::MOVSS,
            x86_opcodes::MOVSD,
            x86_opcodes::ADDSS,
            x86_opcodes::ADDSD,
            x86_opcodes::SUBSS,
            x86_opcodes::SUBSD,
            x86_opcodes::MULSS,
            x86_opcodes::MULSD,
            x86_opcodes::DIVSS,
            x86_opcodes::DIVSD,
            x86_opcodes::UCOMISS,
            x86_opcodes::UCOMISD,
            x86_opcodes::XORPS,
            x86_opcodes::XORPD,
        ]
        .iter()
        .copied()
        .collect();

        // SSE load/store: operands[0] is XMM, operands[1] is GPR
        let sse_mem_ops: std::collections::HashSet<u32> = [
            x86_opcodes::MOVSS_LOAD,
            x86_opcodes::MOVSD_LOAD,
            x86_opcodes::MOVSS_STORE,
            x86_opcodes::MOVSD_STORE,
        ]
        .iter()
        .copied()
        .collect();

        // SSE GPR→XMM: operands[0] is XMM(dest), operands[1] is GPR(src)
        let sse_gpr_to_xmm_ops: std::collections::HashSet<u32> =
            [x86_opcodes::CVTSI2SS, x86_opcodes::CVTSI2SD]
                .iter()
                .copied()
                .collect();

        // SSE XMM→GPR: operands[0] is GPR(dest), operands[1] is XMM(src)
        let sse_xmm_to_gpr_ops: std::collections::HashSet<u32> =
            [x86_opcodes::CVTTSS2SI, x86_opcodes::CVTTSD2SI]
                .iter()
                .copied()
                .collect();

        // MOVD_FROM_XMM/MOVQ_FROM_XMM: operands[0]=XMM(src), operands[1]=GPR(dst)
        let movd_from_xmm_ops: std::collections::HashSet<u32> =
            [x86_opcodes::MOVD_FROM_XMM, x86_opcodes::MOVQ_FROM_XMM]
                .iter()
                .copied()
                .collect();

        // MOVD/MOVQ GPR→XMM: operands[0]=GPR(src), operands[1]=XMM(dst)
        let movd_to_xmm_ops: std::collections::HashSet<u32> =
            [x86_opcodes::MOVD, x86_opcodes::MOVQ]
                .iter()
                .copied()
                .collect();

        for bb in &mf.blocks {
            for mi in &bb.instructions {
                let opcode = mi.opcode;
                if sse_binary_ops.contains(&opcode) {
                    // Both operands must be XMM
                    for op in &mi.operands {
                        if let MachineOperand::Reg(vr) = *op {
                            self.vreg_classes.insert(vr, RegClass::Xmm);
                        }
                    }
                    if let Some(def) = mi.def {
                        self.vreg_classes.insert(def, RegClass::Xmm);
                    }
                } else if sse_mem_ops.contains(&opcode) {
                    // operands[0] is XMM
                    for (i, op) in mi.operands.iter().enumerate() {
                        if i == 0 {
                            if let MachineOperand::Reg(vr) = *op {
                                self.vreg_classes.insert(vr, RegClass::Xmm);
                            }
                        }
                    }
                    if let Some(def) = mi.def {
                        self.vreg_classes.insert(def, RegClass::Xmm);
                    }
                } else if sse_gpr_to_xmm_ops.contains(&opcode) {
                    // operands[0] is XMM(dest)
                    for (i, op) in mi.operands.iter().enumerate() {
                        if i == 0 {
                            if let MachineOperand::Reg(vr) = *op {
                                self.vreg_classes.insert(vr, RegClass::Xmm);
                            }
                        }
                    }
                    if let Some(def) = mi.def {
                        self.vreg_classes.insert(def, RegClass::Xmm);
                    }
                } else if sse_xmm_to_gpr_ops.contains(&opcode) {
                    // operands[1] is XMM(src)
                    for (i, op) in mi.operands.iter().enumerate() {
                        if i == 1 {
                            if let MachineOperand::Reg(vr) = *op {
                                self.vreg_classes.insert(vr, RegClass::Xmm);
                            }
                        }
                    }
                } else if movd_from_xmm_ops.contains(&opcode) {
                    // MOVD_FROM_XMM: operands[0]=XMM(src), operands[1]=GPR(dst)
                    for (i, op) in mi.operands.iter().enumerate() {
                        if i == 0 {
                            if let MachineOperand::Reg(vr) = *op {
                                self.vreg_classes.insert(vr, RegClass::Xmm);
                            }
                        }
                    }
                } else if movd_to_xmm_ops.contains(&opcode) {
                    // MOVD/MOVQ: operands[0]=GPR(src), operands[1]=XMM(dst)
                    for (i, op) in mi.operands.iter().enumerate() {
                        if i == 1 {
                            if let MachineOperand::Reg(vr) = *op {
                                self.vreg_classes.insert(vr, RegClass::Xmm);
                            }
                        }
                    }
                    if let Some(def) = mi.def {
                        self.vreg_classes.insert(def, RegClass::Xmm);
                    }
                }
            }
        }
    }

    /// Find a free physical register at a position, considering all active intervals.
    pub fn find_free_reg(&self, intervals: &[LiveInterval], at_pos: u32) -> Option<PhysReg> {
        let used: HashSet<PhysReg> = intervals
            .iter()
            .filter(|li| li.live_at(at_pos))
            .filter_map(|li| self.assignments.get(&li.vreg))
            .copied()
            .collect();
        self.find_free_reg_in(intervals, at_pos, &used)
    }

    /// Choose a virtual register to evict (spill) from the active set.
    ///
    /// Returns the virtual register whose live interval extends farthest
    /// past the current position — this minimizes future reloads.
    pub fn evict_register(&self, intervals: &[LiveInterval], at_pos: u32) -> VirtReg {
        intervals
            .iter()
            .filter(|li| li.live_at(at_pos))
            .max_by_key(|li| li.end)
            .map(|li| li.vreg)
            .unwrap_or(0)
    }

    /// Eliminate redundant MOV instructions (copy coalescing).
    ///
    /// If a MOV defines a register and that register is only used as
    /// a source in a subsequent instruction, and both have the same
    /// physical register assignment, the MOV can be removed.
    pub fn coalesce_copies(&mut self, mf: &mut MachineFunction) -> usize {
        let mut coalesced = 0;

        for bb in &mut mf.blocks {
            let mut to_remove: HashSet<usize> = HashSet::new();

            for i in 0..bb.instructions.len() {
                let mi = &bb.instructions[i];
                if mi.opcode == x86_opcodes::MOV {
                    // Check if this is a simple reg-to-reg copy
                    if let Some(def) = mi.def {
                        if mi.operands.len() == 1 {
                            if let MachineOperand::Reg(src) = mi.operands[0] {
                                // If both vregs map to the same physreg, coalesce
                                let def_phys = self.assignments.get(&def);
                                let src_phys = self.assignments.get(&src);
                                if let (Some(&dp), Some(&sp)) = (def_phys, src_phys) {
                                    if dp == sp {
                                        to_remove.insert(i);
                                    }
                                }
                            }
                        }
                    }
                }
            }

            // Remove in reverse order
            let mut indices: Vec<usize> = to_remove.into_iter().collect();
            indices.sort_by(|a, b| b.cmp(a));
            for idx in indices {
                bb.instructions.remove(idx);
                coalesced += 1;
            }
        }

        coalesced
    }

    /// Rewrite frame indices: replace virtual frame references with
    /// actual stack offsets using the frame pointer.
    pub fn rewrite_frame_indices(&mut self, mf: &mut MachineFunction, frame_offset: i64) {
        for bb in &mut mf.blocks {
            for _mi in &mut bb.instructions {
                // For now, this is a stub — full implementation would
                // replace virtual frame index operands with [rbp + offset]
                // and adjust rsp-relative addressing.

                // If we have any spill slots, emit prologue/epilogue
                // adjustments are handled by add_callee_saved_spills
                let _ = frame_offset;
            }
        }
    }

    /// Then replaces all `Reg(vr)` operands with `PhysReg(phys)`.
    ///
    /// For spilled vregs (in `spill_slots` but no assignment), uses dedicated
    /// scratch registers (r12 for address, r10/r11 for value) and inserts
    /// MOV-based reload/store sequences to/from the stack slot.
    ///
    /// SPILL_ADDR is r12 because:
    ///   1. r12 is already reserved in the pipeline (SIB escape) so the
    ///      allocator never assigns it to vregs.
    ///   2. r12 is NOT in the SysV x86-64 ABI argument list
    ///      (rdi/rsi/rdx/rcx/r8/r9 are the integer arg regs), so spill code
    ///      can safely use r12 without clobbering CALL argument registers.
    ///   3. Previously SPILL_ADDR was rdx(2), which caused spill stores to
    ///      clobber the 3rd CALL argument (arg2 in rdx).
    ///
    /// r10 and r11 are chosen as value scratches because:
    ///   1. They are caller-saved (no callee-save prologue/epilogue needed).
    ///   2. They are NOT in the SysV x86-64 ABI argument list.
    ///   3. They do not conflict with SPILL_ADDR (r12).
    ///   4. They must be reserved from normal register allocation (done in
    ///      the pipeline's reg_info.reserved list).
    fn rewrite_vregs(&self, mf: &mut MachineFunction) {
        // SPILL_ADDR: r12(12) — frame address computation for spill stores.
        // r12 is already reserved in the pipeline (SIB escape), so it's never
        // used by the allocator.  Critically, r12 is NOT used by the SysV x86-64
        // ABI argument-passing convention (rdi/rsi/rdx/rcx/r8/r9 are the arg
        // regs), so spill code can safely use r12 without clobbering CALL args.
        // Previously SPILL_ADDR was rdx(2), which collided with the 3rd integer
        // CALL argument register, causing spill stores to clobber arg2 values.
        const SPILL_ADDR: PhysReg = 12; // r12 — address computation ONLY
        const SCRATCH_POOL: [PhysReg; 2] = [10, 11]; // r10, r11 — value reload/restore

        for bb in &mut mf.blocks {
            let mut new_insts: Vec<MachineInstr> = Vec::new();

            for mi in &bb.instructions {
                // --- Step 1: Map each spilled vreg to a unique scratch register ---
                let mut spilled_to_scratch: std::collections::HashMap<VirtReg, PhysReg> =
                    std::collections::HashMap::new();
                let mut scratch_idx = 0usize;

                // Collect spilled vregs from operands (source operands)
                for op in &mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        if !self.assignments.contains_key(&vr)
                            && self.spill_slots.contains_key(&vr)
                            && !spilled_to_scratch.contains_key(&vr)
                        {
                            // Allocate the next register from SCRATCH_POOL.
                            // SPILL_ADDR is NOT in SCRATCH_POOL, so it can
                            // never be used as a value scratch.
                            if scratch_idx >= SCRATCH_POOL.len() {
                                panic!(
                                    "rewrite_vregs: ran out of scratch regs at idx {} (need {}), max {}",
                                    scratch_idx, scratch_idx + 1, SCRATCH_POOL.len()
                                );
                            }
                            let scratch = SCRATCH_POOL[scratch_idx];
                            scratch_idx += 1;
                            spilled_to_scratch.insert(vr, scratch);
                        }
                    }
                }

                // Also collect the def vreg if it's spilled (from mi.def)
                let def_scratch = mi.def.and_then(|def| {
                    if !self.assignments.contains_key(&def) && self.spill_slots.contains_key(&def) {
                        if !spilled_to_scratch.contains_key(&def) {
                            if scratch_idx >= SCRATCH_POOL.len() {
                                panic!(
                                    "rewrite_vregs: ran out of scratch regs for def {} (need {}), max {}",
                                    def, scratch_idx + 1, SCRATCH_POOL.len()
                                );
                            }
                            let scratch = SCRATCH_POOL[scratch_idx];
                            scratch_idx += 1;
                            spilled_to_scratch.insert(def, scratch);
                        }
                        spilled_to_scratch.get(&def).copied()
                    } else {
                        None
                    }
                });

                // For instructions without mi.def, check if the instruction
                // has an implicit def (the last Reg operand, per the old ISel
                // convention, for SSE two-address operations like ADDSS where
                // the destination register is the last operand).
                //
                // IMPORTANT: do NOT infer implicit defs for instructions where
                // the last Reg operand is clearly a SOURCE, not a destination:
                //   - MOV PhysReg, reg       (explicit PhysReg destination)
                //   - STORE [ptr], val       (both operands are sources)
                //   - LOAD reg, [ptr]        (has with_def(def), so mi.def is Some)
                //   - CMP, TEST              (both operands are sources)
                //   - CALL func              (last operand is the function name)
                // Treating a source operand as an implicit def causes
                // unnecessary spill stores that waste code space and can
                // interact badly with SPILL_ADDR-based address computation.
                let implicit_def: Option<VirtReg> = if mi.def.is_none() {
                    // Skip instructions that have a PhysReg operand[0]
                    // (explicit hardware destination — last Reg is a source).
                    let has_physreg_dst = mi
                        .operands
                        .first()
                        .map_or(false, |op| matches!(op, MachineOperand::PhysReg(_)));
                    if has_physreg_dst {
                        None
                    } else {
                        mi.operands.iter().rev().find_map(|op| {
                            if let MachineOperand::Reg(vr) = *op {
                                Some(vr)
                            } else {
                                None
                            }
                        })
                    }
                } else {
                    None
                };
                let implicit_def_is_spilled: bool = implicit_def.is_some_and(|def| {
                    !self.assignments.contains_key(&def) && self.spill_slots.contains_key(&def)
                });

                // --- Step 2: Insert reloads for spilled vreg uses ---
                // For each spilled operand, emit:
                //   MOV scratch, rbp
                //   ADD scratch, offset
                //   LOAD scratch, [scratch]
                // This loads the spilled value into the scratch register.
                // The LOAD instruction reads [scratch] for the address BEFORE
                // writing the result, so self-referential LOAD (dst = ptr) is
                // correct x86 behavior: mov scratch, [scratch].
                for op in &mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        if let Some(&scratch) = spilled_to_scratch.get(&vr) {
                            let offset = self.spill_slots[&vr];
                            // MOV scratch, rbp
                            let mut mov = MachineInstr::new(x86_opcodes::MOV);
                            mov.operands.push(MachineOperand::PhysReg(scratch));
                            mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                            mov.size = 0;
                            new_insts.push(mov);
                            // ADD scratch, offset
                            let mut add = MachineInstr::new(x86_opcodes::ADD);
                            add.operands.push(MachineOperand::PhysReg(scratch));
                            add.push_imm(offset);
                            add.size = 0;
                            new_insts.push(add);
                            // LOAD scratch, [scratch]
                            let mut load = MachineInstr::new(x86_opcodes::LOAD);
                            load.operands.push(MachineOperand::PhysReg(scratch)); // dst
                            load.operands.push(MachineOperand::PhysReg(scratch)); // ptr
                            new_insts.push(load);
                        }
                    }
                }

                // --- Step 3: Clone and rewrite operands ---
                let mut rewritten = mi.clone();
                for op in &mut rewritten.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        if let Some(&phys) = self.assignments.get(&vr) {
                            *op = MachineOperand::PhysReg(phys);
                        } else if let Some(&scratch) = spilled_to_scratch.get(&vr) {
                            *op = MachineOperand::PhysReg(scratch);
                        }
                    }
                }

                // Handle def (mi.def-based) — already emits store for spilled defs.
                // Also emit store for the implicit def if it's spilled.
                // This handles instructions without mi.def (e.g. MULSD src, dst)
                // where the def vreg is the last operand. Previously, no store was
                // emitted for these spilled defs, so loading from the spill slot later
                // would return garbage.
                let mut emitted = false;
                if implicit_def_is_spilled {
                    if let Some(def) = implicit_def {
                        let scratch = spilled_to_scratch[&def];
                        let offset = self.spill_slots[&def];

                        let mut mov = MachineInstr::new(x86_opcodes::MOV);
                        mov.operands.push(MachineOperand::PhysReg(SPILL_ADDR)); // dst
                        mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                        mov.size = 0;
                        let mut add = MachineInstr::new(x86_opcodes::ADD);
                        add.operands.push(MachineOperand::PhysReg(SPILL_ADDR));
                        add.push_imm(offset);
                        add.size = 0;
                        let mut store = MachineInstr::new(x86_opcodes::STORE);
                        store.operands.push(MachineOperand::PhysReg(SPILL_ADDR)); // ptr
                        store.operands.push(MachineOperand::PhysReg(scratch)); // val

                        new_insts.push(rewritten.clone());
                        new_insts.push(mov);
                        new_insts.push(add);
                        new_insts.push(store);
                        emitted = true;
                    }
                }

                if let Some(def) = rewritten.def {
                    if let Some(&phys) = self.assignments.get(&def) {
                        // Non-spilled def -- insert assigned physreg at position 0
                        rewritten.operands.insert(0, MachineOperand::PhysReg(phys));
                    } else if self.spill_slots.contains_key(&def) {
                        // Spilled def -- use the def_scratch computed above
                        let scratch = def_scratch.unwrap_or(0);
                        rewritten
                            .operands
                            .insert(0, MachineOperand::PhysReg(scratch));
                        rewritten.def = None;

                        // Insert store after: MOV addr, rbp; ADD addr, offset; STORE [addr], val
                        let offset = self.spill_slots[&def];
                        let mut mov = MachineInstr::new(x86_opcodes::MOV);
                        mov.operands.push(MachineOperand::PhysReg(SPILL_ADDR)); // dst
                        mov.operands.push(MachineOperand::PhysReg(5)); // rbp
                        mov.size = 0;
                        let mut add = MachineInstr::new(x86_opcodes::ADD);
                        add.operands.push(MachineOperand::PhysReg(SPILL_ADDR));
                        add.push_imm(offset);
                        add.size = 0;
                        let mut store = MachineInstr::new(x86_opcodes::STORE);
                        store.operands.push(MachineOperand::PhysReg(SPILL_ADDR)); // ptr
                        store.operands.push(MachineOperand::PhysReg(scratch)); // val

                        if !emitted {
                            new_insts.push(rewritten);
                            new_insts.push(mov);
                            new_insts.push(add);
                            new_insts.push(store);
                        }
                        continue; // Skip the default push below
                    }
                }

                if !emitted {
                    new_insts.push(rewritten);
                }
            }

            bb.instructions = new_insts;
        }
    }

    /// Add callee-saved register spill/restore code in prologue/epilogue.
    ///
    /// For each callee-saved register that is used in this function,
    /// insert a PUSH in the prologue (first block) and a POP in each
    /// return point.
    pub fn add_callee_saved_spills(&mut self, mf: &mut MachineFunction) {
        // Determine which callee-saved regs are actually used
        let used_callee_saved: HashSet<PhysReg> = self
            .target
            .callee_saved
            .iter()
            .copied()
            .filter(|r| {
                // Check if any instruction uses this physreg
                for bb in &mf.blocks {
                    for mi in &bb.instructions {
                        for op in &mi.operands {
                            if *op == MachineOperand::PhysReg(*r) {
                                return true;
                            }
                        }
                    }
                }
                false
            })
            .collect();

        if used_callee_saved.is_empty() || mf.blocks.is_empty() {
            return;
        }

        // Insert PUSH at the start of the first block for each used callee-saved reg
        let mut sorted_regs: Vec<PhysReg> = used_callee_saved.into_iter().collect();
        sorted_regs.sort();

        for &reg in sorted_regs.iter().rev() {
            let mut push = MachineInstr::new(x86_opcodes::PUSH);
            push.operands.push(MachineOperand::PhysReg(reg));
            mf.blocks[0].instructions.insert(0, push);
        }

        // Insert POP before each RET instruction
        for bb in &mut mf.blocks {
            let mut pop_indices = Vec::new();
            for (i, mi) in bb.instructions.iter().enumerate() {
                if mi.opcode == x86_opcodes::RET {
                    pop_indices.push(i);
                }
            }

            // Insert POPs in reverse order before each RET
            for &ret_idx in pop_indices.iter().rev() {
                for &reg in &sorted_regs {
                    let mut pop = MachineInstr::new(x86_opcodes::POP);
                    pop.operands.push(MachineOperand::PhysReg(reg));
                    bb.instructions.insert(ret_idx, pop);
                }
            }
        }
    }

    /// Eliminate dead code: remove instructions whose definitions
    /// are never used after register allocation.
    pub fn eliminate_dead_code(&mut self, mf: &mut MachineFunction) {
        for bb in &mut mf.blocks {
            let mut used_vregs: HashSet<VirtReg> = HashSet::new();

            // Collect all vregs that are used as operands
            for mi in &bb.instructions {
                for op in &mi.operands {
                    if let MachineOperand::Reg(vr) = *op {
                        used_vregs.insert(vr);
                    }
                }
            }

            // Remove instructions whose def is never used
            bb.instructions.retain(|mi| {
                if let Some(def) = mi.def {
                    used_vregs.contains(&def)
                        || mi.opcode == x86_opcodes::RET
                        || mi.opcode == x86_opcodes::JMP
                        || mi.opcode == x86_opcodes::JNE
                        || mi.opcode == x86_opcodes::CALL
                        || mi.opcode == x86_opcodes::PUSH
                        || mi.opcode == x86_opcodes::POP
                } else {
                    true
                }
            });
        }
    }
}

// ============================================================================
// Live Range Segment — A single continuous segment in a live range
// ============================================================================

/// A live range segment defines a contiguous interval [start, end]
/// where a virtual register is live. Live ranges can have multiple
/// segments due to holes caused by spills or control flow.
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
pub struct LiveRangeSegment {
    /// Start of the segment (inclusive).
    pub start: u32,
    /// End of the segment (inclusive).
    pub end: u32,
}

impl LiveRangeSegment {
    /// Create a new segment.
    pub fn new(start: u32, end: u32) -> Self {
        Self { start, end }
    }

    /// Check if this segment overlaps with another.
    pub fn overlaps(&self, other: &LiveRangeSegment) -> bool {
        self.start <= other.end && other.start <= self.end
    }

    /// Check if this segment contains a position.
    pub fn contains(&self, pos: u32) -> bool {
        self.start <= pos && pos <= self.end
    }

    /// Check if this segment is valid (start <= end).
    pub fn is_valid(&self) -> bool {
        self.start <= self.end
    }

    /// Get the length of this segment.
    pub fn length(&self) -> u32 {
        self.end.saturating_sub(self.start) + 1
    }

    /// Try to merge two adjacent or overlapping segments.
    pub fn try_merge(a: &LiveRangeSegment, b: &LiveRangeSegment) -> Option<LiveRangeSegment> {
        if a.end + 1 >= b.start && b.end + 1 >= a.start {
            Some(LiveRangeSegment {
                start: a.start.min(b.start),
                end: a.end.max(b.end),
            })
        } else {
            None
        }
    }
}

// ============================================================================
// Live Range — A set of segments for a virtual register
// ============================================================================

/// A comprehensive live range consisting of one or more segments.
/// Supports value number tracking for connected components.
#[derive(Debug, Clone)]
pub struct LiveRange {
    /// The virtual register.
    pub vreg: VirtReg,
    /// Segments sorted by start position.
    pub segments: Vec<LiveRangeSegment>,
    /// Value number for each segment (for coalescing).
    pub value_numbers: Vec<u32>,
    /// Whether this range has been computed.
    pub computed: bool,
}

impl LiveRange {
    /// Create a new empty live range.
    pub fn new(vreg: VirtReg) -> Self {
        Self {
            vreg,
            segments: Vec::new(),
            value_numbers: Vec::new(),
            computed: false,
        }
    }

    /// Add a segment to the range.
    pub fn add_segment(&mut self, seg: LiveRangeSegment, vn: u32) {
        self.segments.push(seg);
        self.value_numbers.push(vn);
        self.sort_and_merge();
    }

    /// Sort segments by start and merge overlapping/adjacent ones
    /// that share the same value number.
    pub fn sort_and_merge(&mut self) {
        if self.segments.len() <= 1 {
            return;
        }

        // Pair segments with their value numbers and sort
        let mut pairs: Vec<(LiveRangeSegment, u32)> = self
            .segments
            .iter()
            .zip(self.value_numbers.iter())
            .map(|(s, v)| (*s, *v))
            .collect();
        pairs.sort_by_key(|(s, _)| s.start);

        let mut merged_segments = Vec::new();
        let mut merged_vns = Vec::new();

        let mut cur_seg = pairs[0].0;
        let mut cur_vn = pairs[0].1;

        for (seg, vn) in pairs.into_iter().skip(1) {
            // Only merge if same value number
            if vn == cur_vn {
                if let Some(merged) = LiveRangeSegment::try_merge(&cur_seg, &seg) {
                    cur_seg = merged;
                    continue;
                }
            }
            merged_segments.push(cur_seg);
            merged_vns.push(cur_vn);
            cur_seg = seg;
            cur_vn = vn;
        }

        merged_segments.push(cur_seg);
        merged_vns.push(cur_vn);

        self.segments = merged_segments;
        self.value_numbers = merged_vns;
    }

    /// Check if the register is live at a given position.
    pub fn live_at(&self, pos: u32) -> bool {
        self.segments.iter().any(|seg| seg.contains(pos))
    }

    /// Check if this live range overlaps with another.
    pub fn overlaps(&self, other: &LiveRange) -> bool {
        for a in &self.segments {
            for b in &other.segments {
                if a.overlaps(b) {
                    return true;
                }
            }
        }
        false
    }

    /// Get the first point where the register is live.
    pub fn begin_index(&self) -> Option<u32> {
        self.segments.first().map(|s| s.start)
    }

    /// Get the last point where the register is live.
    pub fn end_index(&self) -> Option<u32> {
        self.segments.last().map(|s| s.end)
    }

    /// Find the value number at a given position.
    pub fn value_number_at(&self, pos: u32) -> Option<u32> {
        self.segments
            .iter()
            .zip(self.value_numbers.iter())
            .find(|(seg, _)| seg.contains(pos))
            .map(|(_, vn)| *vn)
    }
}

// ============================================================================
// LiveRangeCalc — Building live range segments from def-use chains
// ============================================================================

/// LiveRangeCalc builds live range segments by processing
/// definition and use points of virtual registers across blocks.
pub struct LiveRangeCalc {
    /// Cached live ranges.
    pub ranges: HashMap<VirtReg, LiveRange>,
    /// Next value number to assign.
    pub next_value_number: u32,
}

impl LiveRangeCalc {
    /// Create a new LiveRangeCalc.
    pub fn new() -> Self {
        Self {
            ranges: HashMap::new(),
            next_value_number: 0,
        }
    }

    /// Reset the calculator for a new function.
    pub fn reset(&mut self) {
        self.ranges.clear();
        self.next_value_number = 0;
    }

    /// Allocate a new value number.
    pub fn get_next_value_number(&mut self) -> u32 {
        let vn = self.next_value_number;
        self.next_value_number += 1;
        vn
    }

    /// Create a new segment from def to use for a register.
    pub fn create_dead_def(&mut self, vreg: VirtReg, def_pos: u32) {
        let vn = self.get_next_value_number();
        let range = self
            .ranges
            .entry(vreg)
            .or_insert_with(|| LiveRange::new(vreg));
        range.add_segment(LiveRangeSegment::new(def_pos, def_pos), vn);
    }

    /// Extend a segment from a definition point to a use point.
    pub fn extend_to_use(&mut self, vreg: VirtReg, def_pos: u32, use_pos: u32) {
        // Check if there's an existing segment covering def_pos before
        // doing the entry operation, to avoid double mutable borrow.
        let existing_vn = self.ranges.get(&vreg).and_then(|r| {
            r.segments
                .iter()
                .zip(r.value_numbers.iter())
                .find(|(s, _)| s.start <= def_pos && def_pos <= s.end)
                .map(|(_, vn)| *vn)
        });

        let vn = if let Some(vn) = existing_vn {
            vn
        } else {
            self.get_next_value_number()
        };

        let range = self
            .ranges
            .entry(vreg)
            .or_insert_with(|| LiveRange::new(vreg));

        // Extend to use point
        range.segments.push(LiveRangeSegment::new(def_pos, use_pos));
        range.value_numbers.push(vn);
        range.sort_and_merge();
    }

    /// Extend a segment from a definition through to the end of a block.
    pub fn extend_to_block_end(&mut self, vreg: VirtReg, def_pos: u32, block_end: u32) {
        self.extend_to_use(vreg, def_pos, block_end);
    }

    /// Add a segment from a use-only occurrence (no def in block).
    pub fn add_use_only(&mut self, vreg: VirtReg, use_pos: u32) {
        let vn = self.get_next_value_number();
        let range = self
            .ranges
            .entry(vreg)
            .or_insert_with(|| LiveRange::new(vreg));
        range.add_segment(LiveRangeSegment::new(use_pos, use_pos), vn);
    }

    /// Get the completed live range for a virtual register.
    pub fn get_range(&self, vreg: VirtReg) -> Option<&LiveRange> {
        self.ranges.get(&vreg)
    }

    /// Get mutable access to a live range.
    pub fn get_range_mut(&mut self, vreg: VirtReg) -> Option<&mut LiveRange> {
        self.ranges.get_mut(&vreg)
    }

    /// Build live ranges for all registers in the function.
    pub fn compute_all(&mut self, mf: &MachineFunction) {
        self.reset();

        for (block_idx, block) in mf.blocks.iter().enumerate() {
            let block_pos = block_idx as u32;

            for (instr_idx, instr) in block.instructions.iter().enumerate() {
                let instr_pos = (block_idx as u32) * 10000 + instr_idx as u32;

                // Process definitions
                if let Some(def_vreg) = instr.def {
                    self.create_dead_def(def_vreg, instr_pos);
                }

                // Process uses
                for op in &instr.operands {
                    if let MachineOperand::Reg(vreg) = *op {
                        self.extend_to_use(vreg, instr_pos, instr_pos);
                    }
                }
            }

            // Extend live ranges through successor blocks if needed
            let block_end = (block_idx as u32) * 10000 + 9999;
            for instr in &block.instructions {
                if let Some(def_vreg) = instr.def {
                    if block.successors.len() == 1 {
                        self.extend_to_block_end(def_vreg, (block_idx as u32) * 10000, block_end);
                    }
                    if !block.successors.is_empty() {
                        self.extend_to_block_end(def_vreg, (block_idx as u32) * 10000, block_end);
                    }
                }
            }
        }
    }

    /// Prune dead segments from all live ranges.
    pub fn prune_dead(&mut self) {
        for range in self.ranges.values_mut() {
            range.segments.retain(|s| s.is_valid());
        }
    }
}

impl Default for LiveRangeCalc {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// ConnectedVNInfo — Value Number tracking with connectivity
// ============================================================================

/// ConnectedVNInfo tracks value numbers and their connectivity
/// across copy instructions. Used for copy coalescing analysis.
#[derive(Debug, Clone)]
pub struct ConnectedVNInfo {
    /// Virtual register being tracked.
    pub vreg: VirtReg,
    /// Current value number.
    pub value_number: u32,
    /// Set of registers connected via copies (same value number).
    pub connected: HashSet<VirtReg>,
    /// Whether this value number is known to be a constant.
    pub is_constant: bool,
    /// The constant value if is_constant.
    pub constant_value: Option<i64>,
    /// Whether this VN has been computed definitively.
    pub resolved: bool,
}

impl ConnectedVNInfo {
    /// Create a new VN info entry.
    pub fn new(vreg: VirtReg, value_number: u32) -> Self {
        Self {
            vreg,
            value_number,
            connected: HashSet::new(),
            is_constant: false,
            constant_value: None,
            resolved: false,
        }
    }

    /// Connect two registers as sharing the same value.
    pub fn connect(&mut self, other: VirtReg) {
        self.connected.insert(other);
    }

    /// Check if this register is connected to another.
    pub fn is_connected_to(&self, other: VirtReg) -> bool {
        self.connected.contains(&other)
    }

    /// Mark this value as a known constant.
    pub fn set_constant(&mut self, value: i64) {
        self.is_constant = true;
        self.constant_value = Some(value);
        self.resolved = true;
    }

    /// Get the constant value if known.
    pub fn get_constant(&self) -> Option<i64> {
        if self.is_constant {
            self.constant_value
        } else {
            None
        }
    }
}

/// ValueNumberMap maintains the global mapping from virtual registers
/// to their value numbers, tracking connectivity across copies.
#[derive(Debug, Clone)]
pub struct ValueNumberMap {
    /// Mapping from vreg to its VN info.
    pub entries: HashMap<VirtReg, ConnectedVNInfo>,
    /// Next available value number.
    pub next_vn: u32,
    /// Union-find parent for value number equivalence classes.
    pub parent: HashMap<u32, u32>,
}

impl ValueNumberMap {
    /// Create a new value number map.
    pub fn new() -> Self {
        Self {
            entries: HashMap::new(),
            next_vn: 0,
            parent: HashMap::new(),
        }
    }

    /// Get the canonical value number for a given virtual register.
    pub fn get_value_number(&mut self, vreg: VirtReg) -> u32 {
        if let Some(entry) = self.entries.get(&vreg) {
            self.find_canonical(entry.value_number)
        } else {
            let vn = self.next_vn;
            self.next_vn += 1;
            let entry = ConnectedVNInfo::new(vreg, vn);
            self.entries.insert(vreg, entry);
            self.parent.insert(vn, vn);
            vn
        }
    }

    /// Union two value numbers (they are equivalent via a copy).
    pub fn union_values(&mut self, a: VirtReg, b: VirtReg) {
        let vn_a = self.get_value_number(a);
        let vn_b = self.get_value_number(b);
        self.union(vn_a, vn_b);

        // Update connectivity
        if let Some(entry) = self.entries.get_mut(&a) {
            entry.connect(b);
        }
        if let Some(entry) = self.entries.get_mut(&b) {
            entry.connect(a);
        }
    }

    /// Find the canonical (root) value number.
    fn find_canonical(&self, vn: u32) -> u32 {
        let mut current = vn;
        while let Some(&parent) = self.parent.get(&current) {
            if parent == current {
                break;
            }
            current = parent;
        }
        current
    }

    /// Union two value numbers.
    fn union(&mut self, a: u32, b: u32) {
        let root_a = self.find_canonical(a);
        let root_b = self.find_canonical(b);
        if root_a != root_b {
            self.parent.insert(root_b, root_a);
        }
    }

    /// Check if two registers have the same value number.
    pub fn same_value(&self, a: VirtReg, b: VirtReg) -> bool {
        if let (Some(ea), Some(eb)) = (self.entries.get(&a), self.entries.get(&b)) {
            self.find_canonical(ea.value_number) == self.find_canonical(eb.value_number)
        } else {
            false
        }
    }

    /// Set a register as containing a known constant value.
    pub fn set_constant(&mut self, vreg: VirtReg, value: i64) {
        let vn = self.get_value_number(vreg);
        if let Some(entry) = self.entries.get_mut(&vreg) {
            entry.set_constant(value);
        }
    }

    /// Get the constant value for a register, if known.
    pub fn get_constant(&self, vreg: VirtReg) -> Option<i64> {
        self.entries.get(&vreg)?.get_constant()
    }
}

impl Default for ValueNumberMap {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// SlotIndex — Fine-grained instruction indexing with slot management
// ============================================================================

/// A SlotIndex uniquely identifies a point within the instruction stream.
/// Each instruction occupies a range of slots: def slot, use slots, and
/// potentially internal slots for complex instructions.
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub struct SlotIndex {
    /// The instruction index.
    pub instr: u32,
    /// The slot within the instruction (0 = early-clobber def,
    /// 1 = normal def, 2 = uses, 3+ = internal).
    pub slot: u32,
}

impl SlotIndex {
    /// Create a new slot index.
    pub fn new(instr: u32, slot: u32) -> Self {
        Self { instr, slot }
    }

    /// Get the base instruction index (slot 0).
    pub fn base(instr: u32) -> Self {
        Self { instr, slot: 0 }
    }

    /// Get the definition slot for an instruction.
    pub fn def(instr: u32) -> Self {
        Self { instr, slot: 1 }
    }

    /// Get the use slot for an instruction.
    pub fn uses(instr: u32) -> Self {
        Self { instr, slot: 2 }
    }

    /// Check if this is a definition slot.
    pub fn is_def(&self) -> bool {
        self.slot == 1
    }

    /// Check if this is a use slot.
    pub fn is_use(&self) -> bool {
        self.slot == 2
    }

    /// Check if this is the base (early) slot.
    pub fn is_base(&self) -> bool {
        self.slot == 0
    }

    /// Get the previous slot index.
    pub fn prev(&self) -> Self {
        if self.slot > 0 {
            Self {
                instr: self.instr,
                slot: self.slot - 1,
            }
        } else if self.instr > 0 {
            Self {
                instr: self.instr - 1,
                slot: 3,
            }
        } else {
            *self
        }
    }

    /// Get the next slot index.
    pub fn next(&self) -> Self {
        if self.slot < 3 {
            Self {
                instr: self.instr,
                slot: self.slot + 1,
            }
        } else {
            Self {
                instr: self.instr + 1,
                slot: 0,
            }
        }
    }
}

/// SlotIndexes manages the assignment of SlotIndex values to machine
/// instructions within a function.
#[derive(Debug, Clone)]
pub struct SlotIndexes {
    /// Next available instruction index.
    pub next_index: u32,
    /// Mapping from instruction positions (block_idx, instr_idx) to slot index.
    pub index_map: HashMap<(usize, usize), SlotIndex>,
    /// Total number of instructions indexed.
    pub instruction_count: u32,
}

impl SlotIndexes {
    /// Create a new empty slot indexes.
    pub fn new() -> Self {
        Self {
            next_index: 0,
            index_map: HashMap::new(),
            instruction_count: 0,
        }
    }

    /// Allocate slot indexes for all instructions in a function.
    pub fn index_function(&mut self, mf: &MachineFunction) {
        self.next_index = 0;
        self.index_map.clear();
        self.instruction_count = 0;

        for (block_idx, block) in mf.blocks.iter().enumerate() {
            for (instr_idx, _instr) in block.instructions.iter().enumerate() {
                let idx = self.next_index;
                let si = SlotIndex::base(idx);
                self.index_map.insert((block_idx, instr_idx), si);
                self.next_index += 1;
                self.instruction_count += 1;
            }
        }
    }

    /// Get the slot index for an instruction at the given position.
    pub fn get_index(&self, block_idx: usize, instr_idx: usize) -> Option<SlotIndex> {
        self.index_map.get(&(block_idx, instr_idx)).copied()
    }

    /// Get the definition slot for an instruction.
    pub fn get_def_index(&self, block_idx: usize, instr_idx: usize) -> Option<SlotIndex> {
        self.index_map
            .get(&(block_idx, instr_idx))
            .map(|si| SlotIndex::def(si.instr))
    }

    /// Get the use slot for an instruction.
    pub fn get_use_index(&self, block_idx: usize, instr_idx: usize) -> Option<SlotIndex> {
        self.index_map
            .get(&(block_idx, instr_idx))
            .map(|si| SlotIndex::uses(si.instr))
    }

    /// Check if a slot index is valid.
    pub fn is_valid(&self, si: SlotIndex) -> bool {
        si.instr < self.next_index
    }

    /// Get the total indexed range.
    pub fn total_slots(&self) -> u32 {
        self.next_index * 4 // 4 slots per instruction
    }
}

impl Default for SlotIndexes {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// LiveVariables — Compute liveness information for all registers
// ============================================================================

/// Liveness information for a single virtual register within a block.
#[derive(Debug, Clone)]
pub struct BlockLiveness {
    /// Whether the register is live-in (used before any def).
    pub live_in: bool,
    /// Whether the register is live-out (used after last def).
    pub live_out: bool,
    /// Whether the register is killed (last use) in this block.
    pub killed: bool,
    /// First use position in the block.
    pub first_use: Option<u32>,
    /// Last use position in the block.
    pub last_use: Option<u32>,
    /// Definition positions in the block.
    pub defs: Vec<u32>,
}

impl Default for BlockLiveness {
    fn default() -> Self {
        Self {
            live_in: false,
            live_out: false,
            killed: false,
            first_use: None,
            last_use: None,
            defs: Vec::new(),
        }
    }
}

/// LiveVariables pass computes liveness information for all virtual
/// registers across all basic blocks in a machine function.
///
/// The analysis uses a standard iterative dataflow algorithm:
///   1. For each block, compute local def/use sets.
///   2. Propagate liveness across CFG edges using fixed-point iteration.
///   3. The result provides live-in/live-out sets per block.
pub struct LiveVariables {
    /// Per-block, per-register liveness info.
    pub block_liveness: Vec<HashMap<VirtReg, BlockLiveness>>,
    /// Global live ranges.
    pub ranges: HashMap<VirtReg, LiveRange>,
    /// Whether the analysis has been computed.
    pub computed: bool,
    /// Slot indexes for the function.
    pub slot_indexes: SlotIndexes,
    /// Value number map.
    pub value_numbers: ValueNumberMap,
}

impl LiveVariables {
    /// Create a new LiveVariables pass.
    pub fn new() -> Self {
        Self {
            block_liveness: Vec::new(),
            ranges: HashMap::new(),
            computed: false,
            slot_indexes: SlotIndexes::new(),
            value_numbers: ValueNumberMap::new(),
        }
    }

    /// Run the live variable analysis on a machine function.
    pub fn run_on_function(&mut self, mf: &MachineFunction) {
        self.block_liveness = vec![HashMap::new(); mf.blocks.len()];
        self.ranges.clear();
        self.slot_indexes.index_function(mf);

        // Step 1: Compute local def/use sets for each block
        for (block_idx, block) in mf.blocks.iter().enumerate() {
            for (instr_idx, instr) in block.instructions.iter().enumerate() {
                // Record uses
                for op in &instr.operands {
                    if let MachineOperand::Reg(vreg) = *op {
                        let entry = self.block_liveness[block_idx].entry(vreg).or_default();
                        let pos = instr_idx as u32;
                        if entry.first_use.is_none() {
                            entry.first_use = Some(pos);
                        }
                        entry.last_use = Some(pos);
                    }
                }

                // Record defs
                if let Some(def_vreg) = instr.def {
                    let entry = self.block_liveness[block_idx].entry(def_vreg).or_default();
                    entry.defs.push(instr_idx as u32);
                }
            }
        }

        // Step 2: Fixed-point iteration for live-in / live-out
        let mut changed = true;
        let mut iterations = 0;

        while changed && iterations < 100 {
            changed = false;
            iterations += 1;

            // Backward dataflow: iterate blocks in reverse
            for block_idx in (0..mf.blocks.len()).rev() {
                let block = &mf.blocks[block_idx];

                // Compute live-out from successors' live-in
                let mut live_out: HashSet<VirtReg> = HashSet::new();
                for &succ_idx in &block.successors {
                    if succ_idx < self.block_liveness.len() {
                        for (&vreg, info) in &self.block_liveness[succ_idx] {
                            if info.live_in {
                                live_out.insert(vreg);
                            }
                        }
                    }
                }

                // Update live-out and check for changes
                let block_info = &mut self.block_liveness[block_idx];
                for &vreg in &live_out {
                    let entry = block_info.entry(vreg).or_default();
                    if !entry.live_out {
                        entry.live_out = true;
                        changed = true;
                    }
                }

                // Compute live-in: used locally or live-out and not defined
                for (&vreg, info) in block_info.clone().iter() {
                    let was_live_in = info.live_in;
                    let has_use = info.first_use.is_some();
                    let has_def = !info.defs.is_empty();
                    let is_live_out = info.live_out;

                    let new_live_in = has_use || (is_live_out && !has_def);
                    let entry = block_info.entry(vreg).or_default();
                    if entry.live_in != new_live_in {
                        entry.live_in = new_live_in;
                        changed = true;
                    }
                }

                // Also add live-out registers that aren't in the map yet
                for &vreg in &live_out {
                    block_info.entry(vreg).or_default();
                }
            }
        }

        // Step 3: Kill flags: mark last use in each block
        for block_idx in 0..mf.blocks.len() {
            let mut last_use_by_reg: HashMap<VirtReg, u32> = HashMap::new();
            for (instr_idx, instr) in mf.blocks[block_idx].instructions.iter().enumerate() {
                for op in &instr.operands {
                    if let MachineOperand::Reg(vreg) = *op {
                        last_use_by_reg.insert(vreg, instr_idx as u32);
                    }
                }
            }

            for (&vreg, &last_pos) in &last_use_by_reg {
                if let Some(entry) = self.block_liveness[block_idx].get_mut(&vreg) {
                    if entry.last_use == Some(last_pos) && !entry.live_out {
                        entry.killed = true;
                    }
                }
            }
        }

        // Step 4: Build global live ranges
        self.build_global_ranges(mf);
        self.computed = true;
    }

    /// Build global LiveRange objects from per-block liveness.
    fn build_global_ranges(&mut self, mf: &MachineFunction) {
        let mut range_calc = LiveRangeCalc::new();
        range_calc.compute_all(mf);
        self.ranges = range_calc.ranges;
    }

    /// Check if a virtual register is live-in to a block.
    pub fn is_live_in(&self, block_idx: usize, vreg: VirtReg) -> bool {
        self.block_liveness
            .get(block_idx)
            .and_then(|map| map.get(&vreg))
            .map(|info| info.live_in)
            .unwrap_or(false)
    }

    /// Check if a virtual register is live-out of a block.
    pub fn is_live_out(&self, block_idx: usize, vreg: VirtReg) -> bool {
        self.block_liveness
            .get(block_idx)
            .and_then(|map| map.get(&vreg))
            .map(|info| info.live_out)
            .unwrap_or(false)
    }

    /// Check if a register is killed (last use) in a block.
    pub fn is_killed(&self, block_idx: usize, vreg: VirtReg) -> bool {
        self.block_liveness
            .get(block_idx)
            .and_then(|map| map.get(&vreg))
            .map(|info| info.killed)
            .unwrap_or(false)
    }

    /// Get the live range for a virtual register.
    pub fn get_range(&self, vreg: VirtReg) -> Option<&LiveRange> {
        self.ranges.get(&vreg)
    }

    /// Get all virtual registers live-out of a block.
    pub fn live_out_set(&self, block_idx: usize) -> Vec<VirtReg> {
        self.block_liveness
            .get(block_idx)
            .map(|map| {
                map.iter()
                    .filter(|(_, info)| info.live_out)
                    .map(|(&vreg, _)| vreg)
                    .collect()
            })
            .unwrap_or_default()
    }

    /// Get all virtual registers live-in to a block.
    pub fn live_in_set(&self, block_idx: usize) -> Vec<VirtReg> {
        self.block_liveness
            .get(block_idx)
            .map(|map| {
                map.iter()
                    .filter(|(_, info)| info.live_in)
                    .map(|(&vreg, _)| vreg)
                    .collect()
            })
            .unwrap_or_default()
    }
}

impl Default for LiveVariables {
    fn default() -> Self {
        Self::new()
    }
}

// ============================================================================
// Target ISel Interface — Abstract instruction selection
// ============================================================================

/// Target-specific instruction selector interface.
///
/// Each backend (X86, AArch64, RISC-V) implements this trait to
/// provide instruction selection and register/frame information.
pub trait TargetISel {
    /// Perform instruction selection: lower IR to machine instructions.
    fn select(&self, mf: &mut MachineFunction, func: &ValueRef);

    /// Get target register information.
    fn get_target_reg_info(&self) -> TargetRegInfo;

    /// Get the frame lowering strategy for this target.
    fn get_frame_lowering(&self) -> Box<dyn FrameLowering>;
}

/// Frame lowering: emit function prologue and epilogue sequences.
///
/// Each target has its own conventions for stack frame setup:
/// - X86-64: push rbp; mov rbp, rsp; sub rsp, N ... leave; ret
/// - AArch64: stp fp, lr, [sp, #-N]! ... ldp fp, lr, [sp], #N; ret
/// - RISC-V: addi sp, sp, -N ... addi sp, sp, N; ret
pub trait FrameLowering {
    /// Emit the function prologue (before first user instruction).
    fn emit_prologue(&self, mf: &mut MachineFunction) -> Vec<MachineInstr>;

    /// Emit the function epilogue (before each return).
    fn emit_epilogue(&self, mf: &mut MachineFunction) -> Vec<MachineInstr>;

    /// Check if this function needs a frame pointer (rbp/fp).
    fn needs_frame_pointer(&self, func: &ValueRef) -> bool;
}

// ============================================================================
// X86-64 Frame Lowering
// ============================================================================

/// X86-64 frame lowering implementation.
pub struct X86FrameLowering;

impl FrameLowering for X86FrameLowering {
    fn emit_prologue(&self, _mf: &mut MachineFunction) -> Vec<MachineInstr> {
        let mut instrs = Vec::new();

        // push rbp
        let mut push_rbp = MachineInstr::new(x86_opcodes::PUSH);
        push_rbp.operands.push(MachineOperand::PhysReg(5));
        instrs.push(push_rbp);

        // mov rbp, rsp
        let mut mov = MachineInstr::new(x86_opcodes::MOV);
        mov.operands.push(MachineOperand::PhysReg(5));
        mov.operands.push(MachineOperand::PhysReg(4));
        instrs.push(mov);

        instrs
    }

    fn emit_epilogue(&self, _mf: &mut MachineFunction) -> Vec<MachineInstr> {
        let mut instrs = Vec::new();

        // leave (equivalent to mov rsp, rbp; pop rbp)
        let mut pop_rbp = MachineInstr::new(x86_opcodes::POP);
        pop_rbp.operands.push(MachineOperand::PhysReg(5));
        instrs.push(pop_rbp);

        instrs
    }

    fn needs_frame_pointer(&self, func: &ValueRef) -> bool {
        // Simple heuristic: check if function has alloca or variable-length arrays
        let f = func.borrow();
        for op in &f.operands {
            let bb = op.borrow();
            if bb.is_basic_block() {
                for inst_val in &bb.operands {
                    let inst = inst_val.borrow();
                    if let Some(Opcode::Alloca) = inst.get_opcode() {
                        return true;
                    }
                }
            }
        }
        false
    }
}

// ============================================================================
// X86-64 Target ISel
// ============================================================================

/// X86-64 target instruction selector.
pub struct X86TargetISel;

impl TargetISel for X86TargetISel {
    fn select(&self, mf: &mut MachineFunction, func: &ValueRef) {
        InstructionSelector::select(mf, func);
    }

    fn get_target_reg_info(&self) -> TargetRegInfo {
        TargetRegInfo::for_x86_64()
    }

    fn get_frame_lowering(&self) -> Box<dyn FrameLowering> {
        Box::new(X86FrameLowering)
    }
}

// ============================================================================
// Convenience Pipeline — One-shot compilation with full regalloc
// ============================================================================

/// Compile a function through the full pipeline:
/// 1. Instruction selection
/// 2. Register allocation with spilling
/// 3. Prologue/epilogue insertion
/// 4. Frame index rewriting
/// 5. Assembly printing
///
/// Returns the assembly text for the compiled function.
pub fn compile_function_with_pipeline(func: &ValueRef, isel: &dyn TargetISel) -> String {
    let f = func.borrow();
    let mut mf = MachineFunction::new(&f.name);

    // Step 1: Instruction selection
    isel.select(&mut mf, func);

    // Step 2: Register allocation with spilling
    let target_info = isel.get_target_reg_info();
    let mut regalloc = RegAlloc::new(target_info);
    let result = regalloc.allocate(&mut mf);

    // Step 3: Insert prologue/epilogue
    let frame_lowering = isel.get_frame_lowering();
    let prologue = frame_lowering.emit_prologue(&mut mf);
    let epilogue = frame_lowering.emit_epilogue(&mut mf);

    // Insert prologue at start of first block
    if !mf.blocks.is_empty() {
        for instr in prologue.into_iter().rev() {
            mf.blocks[0].instructions.insert(0, instr);
        }
    }

    // Insert epilogue before each RET
    for bb in &mut mf.blocks {
        let ret_indices: Vec<usize> = bb
            .instructions
            .iter()
            .enumerate()
            .filter(|(_, mi)| mi.opcode == x86_opcodes::RET)
            .map(|(i, _)| i)
            .collect();
        for &ret_idx in ret_indices.iter().rev() {
            for instr in epilogue.iter().rev() {
                bb.instructions.insert(ret_idx, instr.clone());
            }
        }
    }

    // Step 4: Frame index rewriting is done inside regalloc.allocate

    // Step 5: Print assembly
    let mut printer = AsmPrinter::new();
    printer.print_function(&mf);

    let _ = result; // result available for diagnostics
    printer.output
}

// ============================================================================
// Greedy Register Allocator — optimized register assignment with splitting
// ============================================================================

/// Greedy register allocator that improves upon linear scan by making
/// smarter assignment decisions, splitting live ranges when profitable,
/// and using spill cost heuristics to minimize spill code.
///
/// Algorithm overview:
/// 1. Build interference graph from live intervals
/// 2. Sort virtual registers by priority (spill cost / live range length)
/// 3. For each unassigned vreg:
///    a. Try to find a free physical register
///    b. If none, consider splitting the live range
///    c. If splitting not profitable, evict the cheapest assigned register
///    d. If eviction fails, spill the vreg
/// 4. Coalesce copies where possible
/// 5. Perform register class assignment and cross-class copies
pub struct GreedyRegAlloc {
    /// Assignments: virtual register -> physical register
    pub assignments: HashMap<VirtReg, PhysReg>,
    /// Physical registers that are available for allocation.
    pub available: Vec<PhysReg>,
    /// Current assignments: physical register -> virtual register.
    pub phys_to_vreg: HashMap<PhysReg, VirtReg>,
    /// Spill cost for each virtual register.
    pub spill_costs: HashMap<VirtReg, f64>,
    /// Interference graph for the function.
    pub interference: InterferenceGraph,
    /// Live intervals for all virtual registers.
    pub intervals: Vec<LiveInterval>,
    /// Stack frame offset for spilled registers.
    pub frame_offset: i64,
    /// Spill slot assignments.
    pub spill_slots: HashMap<VirtReg, i64>,
    /// Number of copies coalesced.
    pub copies_coalesced: usize,
    /// Number of live ranges split.
    pub ranges_split: usize,
    /// Number of registers spilled.
    pub regs_spilled: usize,
}

/// Interference graph for greedy register allocation.
///
/// Tracks which pairs of virtual registers interfere (have overlapping
/// live ranges), and maintains degree counts for each register.
#[derive(Debug, Clone)]
pub struct InterferenceGraph {
    /// Adjacency list: vreg -> set of interfering vregs.
    pub edges: HashMap<VirtReg, HashSet<VirtReg>>,
    /// Degree (number of interferences) for each vreg.
    pub degree: HashMap<VirtReg, usize>,
    /// Whether the graph has been built.
    pub built: bool,
}

impl InterferenceGraph {
    /// Create a new empty interference graph.
    pub fn new() -> Self {
        InterferenceGraph {
            edges: HashMap::new(),
            degree: HashMap::new(),
            built: false,
        }
    }

    /// Add an interference between two virtual registers.
    pub fn add_interference(&mut self, a: VirtReg, b: VirtReg) {
        if a == b {
            return;
        }
        self.edges.entry(a).or_default().insert(b);
        self.edges.entry(b).or_default().insert(a);
        *self.degree.entry(a).or_default() += 1;
        *self.degree.entry(b).or_default() += 1;
    }

    /// Check if two virtual registers interfere.
    pub fn interfere(&self, a: VirtReg, b: VirtReg) -> bool {
        self.edges
            .get(&a)
            .map(|neighbors| neighbors.contains(&b))
            .unwrap_or(false)
    }

    /// Build the interference graph from a set of live intervals.
    pub fn build_from_intervals(&mut self, intervals: &[LiveInterval]) {
        self.edges.clear();
        self.degree.clear();

        for i in 0..intervals.len() {
            let li_a = &intervals[i];
            for j in (i + 1)..intervals.len() {
                let li_b = &intervals[j];
                if li_a.overlaps(li_b) {
                    self.add_interference(li_a.vreg, li_b.vreg);
                }
            }
        }

        self.built = true;
    }

    /// Get the degree of a virtual register.
    pub fn get_degree(&self, vreg: VirtReg) -> usize {
        self.degree.get(&vreg).copied().unwrap_or(0)
    }

    /// Remove a virtual register from the graph (when coalesced).
    pub fn remove_register(&mut self, vreg: VirtReg) {
        if let Some(neighbors) = self.edges.remove(&vreg) {
            for &neighbor in &neighbors {
                if let Some(neighbor_edges) = self.edges.get_mut(&neighbor) {
                    neighbor_edges.remove(&vreg);
                }
                if let Some(deg) = self.degree.get_mut(&neighbor) {
                    *deg = deg.saturating_sub(1);
                }
            }
        }
        self.degree.remove(&vreg);
    }

    /// Get all neighbors of a virtual register.
    pub fn neighbors(&self, vreg: VirtReg) -> Vec<VirtReg> {
        self.edges
            .get(&vreg)
            .map(|set| set.iter().copied().collect())
            .unwrap_or_default()
    }
}

impl Default for InterferenceGraph {
    fn default() -> Self {
        InterferenceGraph::new()
    }
}

impl GreedyRegAlloc {
    /// Create a new greedy register allocator.
    pub fn new(target: TargetRegInfo) -> Self {
        let available = target.allocatable_regs();
        GreedyRegAlloc {
            assignments: HashMap::new(),
            available,
            phys_to_vreg: HashMap::new(),
            spill_costs: HashMap::new(),
            interference: InterferenceGraph::new(),
            intervals: Vec::new(),
            frame_offset: 0,
            spill_slots: HashMap::new(),
            copies_coalesced: 0,
            ranges_split: 0,
            regs_spilled: 0,
        }
    }

    /// Run greedy register allocation on a machine function.
    pub fn allocate(&mut self, mf: &mut MachineFunction) -> RegAllocResult {
        // Step 1: Compute live intervals
        let mut regalloc = RegAlloc::new(TargetRegInfo::for_x86_64());
        self.intervals = regalloc.compute_live_intervals(mf);

        // Step 2: Build interference graph
        self.interference.build_from_intervals(&self.intervals);

        // Step 3: Compute spill costs
        self.compute_spill_costs(mf);

        // Step 4: Sort by priority (register priority heuristic)
        let mut sorted: Vec<usize> = (0..self.intervals.len()).collect();
        sorted.sort_by(|&a, &b| {
            let cost_a = self
                .spill_costs
                .get(&self.intervals[a].vreg)
                .unwrap_or(&0.0);
            let cost_b = self
                .spill_costs
                .get(&self.intervals[b].vreg)
                .unwrap_or(&0.0);
            cost_b
                .partial_cmp(cost_a)
                .unwrap_or(std::cmp::Ordering::Equal)
        });

        // Step 5: Assign registers greedily
        for idx in sorted {
            let vreg = self.intervals[idx].vreg;
            if self.assignments.contains_key(&vreg) {
                continue;
            }
            let li_copy = self.intervals[idx].clone();
            self.try_assign_with_split_and_evict(&li_copy, mf);
        }

        // Step 6: Coalesce copies
        self.coalesce_copies_greedy(mf);

        let spills = self.regs_spilled;
        RegAllocResult {
            success: true,
            spills,
            reloads: spills,
            copies_coalesced: self.copies_coalesced,
        }
    }

    /// Try to assign a physical register to a virtual register, with
    /// live range splitting and eviction as fallback strategies.
    fn try_assign_with_split_and_evict(&mut self, li: &LiveInterval, mf: &mut MachineFunction) {
        // Strategy 1: Try to find a free register
        if let Some(phys) = self.find_best_free_reg(li) {
            self.assign(li.vreg, phys);
            return;
        }

        // Strategy 2: Try live range splitting
        if self.should_split(li) {
            let split_points = self.find_split_points(li);
            if !split_points.is_empty() {
                if self.split_and_assign(li, &split_points, mf) {
                    self.ranges_split += 1;
                    return;
                }
            }
        }

        // Strategy 3: Evict the cheapest interfering register
        if let Some(phys) = self.evict_cheapest(li) {
            self.assign(li.vreg, phys);
            return;
        }

        // Strategy 4: Spill the register
        self.spill_register(li, mf);
    }

    /// Find the best free physical register for a virtual register.
    /// Returns None if no register is free for the entire live range.
    fn find_best_free_reg(&self, li: &LiveInterval) -> Option<PhysReg> {
        let interfering: HashSet<PhysReg> = self
            .interference
            .neighbors(li.vreg)
            .iter()
            .filter_map(|&vreg| self.assignments.get(&vreg))
            .copied()
            .collect();

        self.available
            .iter()
            .filter(|r| !interfering.contains(r))
            .copied()
            .next()
    }

    /// Assign a physical register to a virtual register.
    fn assign(&mut self, vreg: VirtReg, phys: PhysReg) {
        self.assignments.insert(vreg, phys);
        self.phys_to_vreg.insert(phys, vreg);
    }

    /// Unassign a physical register (during eviction).
    fn unassign(&mut self, phys: PhysReg) {
        if let Some(vreg) = self.phys_to_vreg.remove(&phys) {
            self.assignments.remove(&vreg);
        }
    }

    /// Determine if live range splitting is likely profitable.
    fn should_split(&self, li: &LiveInterval) -> bool {
        // Split if the live range is long and has many uses
        let length = li.length();
        length > 50 && li.uses.len() >= 3
    }

    /// Find optimal split points in a live interval.
    ///
    /// Split points are chosen at gaps between uses where the register
    /// is not live. The best split point minimizes the sum of lengths
    /// of the resulting sub-ranges.
    fn find_split_points(&self, li: &LiveInterval) -> Vec<u32> {
        let mut points = Vec::new();

        if li.uses.len() < 2 {
            return points;
        }

        // Sort uses to find gaps
        let mut sorted_uses = li.uses.clone();
        sorted_uses.sort();
        sorted_uses.dedup();

        // Find gaps > 5 instructions between consecutive uses
        for window in sorted_uses.windows(2) {
            let gap = window[1] - window[0];
            if gap > 10 {
                // Split at the midpoint of the gap
                points.push(window[0] + gap / 2);
            }
        }

        points
    }

    /// Split a live range at the given points and attempt to assign
    /// different physical registers to each segment.
    fn split_and_assign(
        &mut self,
        li: &LiveInterval,
        split_points: &[u32],
        mf: &mut MachineFunction,
    ) -> bool {
        if split_points.is_empty() {
            return false;
        }

        // For simplicity, use the first split point
        let split_at = split_points[0];

        // Create a new virtual register for the second half
        let new_vreg = self.make_new_vreg(mf);

        // Create live intervals for the split parts
        let first_half = LiveInterval {
            vreg: li.vreg,
            start: li.start,
            end: split_at,
            uses: li
                .uses
                .iter()
                .filter(|&&u| u <= split_at)
                .copied()
                .collect(),
            defs: li
                .defs
                .iter()
                .filter(|&&d| d <= split_at)
                .copied()
                .collect(),
        };

        let second_half = LiveInterval {
            vreg: new_vreg,
            start: split_at + 1,
            end: li.end,
            uses: li.uses.iter().filter(|&&u| u > split_at).copied().collect(),
            defs: li.defs.iter().filter(|&&d| d > split_at).copied().collect(),
        };

        // Try to assign both halves
        let first_phys = self.find_best_free_reg_for_part(&first_half);
        let second_phys = self.find_best_free_reg_for_part(&second_half);

        if let (Some(p1), Some(p2)) = (first_phys, second_phys) {
            self.assign(li.vreg, p1);
            self.assign(new_vreg, p2);

            // Insert a copy between the two halves at the split point
            self.insert_split_copy(li.vreg, new_vreg, split_at, mf);
            return true;
        }

        false
    }

    /// Find a free physical register for a partial live range.
    fn find_best_free_reg_for_part(&self, li: &LiveInterval) -> Option<PhysReg> {
        // Check which assigned registers are live during this interval
        let mut live_regs = HashSet::new();
        for (&vreg, &phys) in &self.assignments {
            // Check if vreg's original interval overlaps with li
            for interval in &self.intervals {
                if interval.vreg == vreg && interval.overlaps(li) {
                    live_regs.insert(phys);
                    break;
                }
            }
        }

        self.available
            .iter()
            .filter(|r| !live_regs.contains(r))
            .copied()
            .next()
    }

    /// Create a new virtual register and return its ID.
    fn make_new_vreg(&self, mf: &mut MachineFunction) -> VirtReg {
        mf.virt_reg_counter += 1;
        mf.virt_reg_counter
    }

    /// Insert a COPY instruction between two split virtual registers.
    fn insert_split_copy(&self, src: VirtReg, dst: VirtReg, at_pos: u32, mf: &mut MachineFunction) {
        let mut copy = MachineInstr::new(x86_opcodes::MOV);
        copy.operands.push(MachineOperand::Reg(src));
        copy.def = Some(dst);

        // Insert at the appropriate position in the block
        for bb in &mut mf.blocks {
            if bb.instructions.len() as u32 > at_pos {
                bb.instructions.insert(at_pos as usize, copy.clone());
                break;
            }
        }
    }

    /// Evict the cheapest interfering register to make room.
    fn evict_cheapest(&mut self, li: &LiveInterval) -> Option<PhysReg> {
        let neighbors = self.interference.neighbors(li.vreg);

        let mut best_phys: Option<PhysReg> = None;
        let mut best_cost = f64::MAX;

        for &neighbor in &neighbors {
            if let Some(&phys) = self.assignments.get(&neighbor) {
                let cost = self.spill_costs.get(&neighbor).unwrap_or(&f64::MAX);
                if *cost < best_cost {
                    best_cost = *cost;
                    best_phys = Some(phys);
                }
            }
        }

        if let Some(phys) = best_phys {
            self.unassign(phys);
        }

        best_phys
    }

    /// Spill a virtual register to the stack.
    fn spill_register(&mut self, li: &LiveInterval, mf: &mut MachineFunction) {
        // Assign a spill slot
        let slot_offset = self.frame_offset;
        self.spill_slots.insert(li.vreg, slot_offset);
        self.frame_offset -= 8; // 8 bytes per slot (GPR)

        // Insert spill code at each def point
        for &def_pos in &li.defs {
            self.insert_spill_at(li.vreg, slot_offset, def_pos, mf);
        }

        // Insert reload code at each use point
        for &use_pos in &li.uses {
            self.insert_reload_at(li.vreg, slot_offset, use_pos, mf);
        }

        self.regs_spilled += 1;
    }

    /// Insert a spill (store) instruction at a position.
    fn insert_spill_at(&self, vreg: VirtReg, offset: i64, pos: u32, mf: &mut MachineFunction) {
        // MOV [RBP + offset], vreg
        let mut spill = MachineInstr::new(x86_opcodes::MOV);
        spill.operands.push(MachineOperand::PhysReg(5)); // RBP
        spill.operands.push(MachineOperand::Imm(offset));
        spill.operands.push(MachineOperand::Reg(vreg));

        for bb in &mut mf.blocks {
            let len = bb.instructions.len() as u32;
            if pos < len {
                bb.instructions.insert(pos as usize, spill);
                break;
            }
        }
    }

    /// Insert a reload (load) instruction at a position.
    fn insert_reload_at(&self, vreg: VirtReg, offset: i64, pos: u32, mf: &mut MachineFunction) {
        // vreg = MOV [RBP + offset]
        let mut reload = MachineInstr::new(x86_opcodes::MOV);
        reload.operands.push(MachineOperand::PhysReg(5)); // RBP
        reload.operands.push(MachineOperand::Imm(offset));
        reload.def = Some(vreg);

        for bb in &mut mf.blocks {
            let len = bb.instructions.len() as u32;
            if pos < len {
                bb.instructions.insert(pos as usize, reload);
                break;
            }
        }
    }
}

// ============================================================================
// Spill Cost Computation — weight-based heuristic for greedy allocator
// ============================================================================

impl GreedyRegAlloc {
    /// Compute spill costs for all virtual registers.
    ///
    /// The spill cost is a weighted sum of:
    /// - Loop depth: uses inside loops are more expensive to spill
    /// - Use count: more uses = more reloads = higher cost
    /// - Def count: more defs = more stores = higher cost
    /// - Live range length: longer ranges = more reloads
    /// - Rematerialization possibility: rematerializable values are cheaper
    ///   to spill because they can be recomputed instead of reloaded
    pub fn compute_spill_costs(&mut self, mf: &MachineFunction) {
        // Estimate loop depth (simple heuristic: use position in function)
        let total_blocks = mf.blocks.len() as f64;

        for li in &self.intervals {
            let use_count = li.uses.len() as f64;
            let def_count = li.defs.len() as f64;
            let range_length = li.length() as f64;

            // Base cost: uses + defs weighted by range length
            let base_cost = (use_count * 2.0 + def_count) * (1.0 + range_length / 100.0);

            // Loop depth bonus: registers used more centrally cost more
            let position_ratio = li.start as f64 / (mf.blocks.len() as f64 * 10.0).max(1.0);
            let _ = total_blocks; // for future loop depth analysis

            // Rematerialization check: if vreg is defined by a simple
            // instruction (e.g., MOV immediate), it's cheaper to spill
            let is_rematerializable = self.is_rematerializable(li.vreg, mf);
            let remat_factor = if is_rematerializable { 0.3 } else { 1.0 };

            let cost = base_cost * (1.0 + position_ratio) * remat_factor;
            self.spill_costs.insert(li.vreg, cost);
        }
    }

    /// Check if a virtual register can be rematerialized instead of
    /// spilled/reloaded. A register is rematerializable if it's defined
    /// by a cheap instruction whose operands are always available.
    fn is_rematerializable(&self, vreg: VirtReg, mf: &MachineFunction) -> bool {
        for bb in &mf.blocks {
            for mi in &bb.instructions {
                if mi.def == Some(vreg) {
                    // Check if this is a MOV immediate or LEA of constant
                    return mi.opcode == x86_opcodes::MOV
                        && mi.operands.len() >= 2
                        && matches!(mi.operands[1], MachineOperand::Imm(_));
                }
            }
        }
        false
    }
}

// ============================================================================
// LiveRangeSplit — optimal split point selection for register allocation
// ============================================================================

/// Live range splitting analysis.
///
/// When a live range cannot be assigned a single register, it can be
/// split into multiple sub-ranges, each assigned a different register.
/// The split points are chosen at gaps between uses to minimize copy
/// instructions.
#[derive(Debug, Clone)]
pub struct LiveRangeSplit {
    /// The original virtual register being split.
    pub vreg: VirtReg,
    /// Split points (instruction indices).
    pub split_points: Vec<u32>,
    /// New virtual registers created for split segments.
    pub new_vregs: Vec<VirtReg>,
}

impl LiveRangeSplit {
    /// Create a new split analysis.
    pub fn new(vreg: VirtReg) -> Self {
        LiveRangeSplit {
            vreg,
            split_points: Vec::new(),
            new_vregs: Vec::new(),
        }
    }

    /// Find optimal split points for a live interval.
    ///
    /// The algorithm looks for "gaps" between uses where the register
    /// is not live. A gap is a sequence of instructions where the
    /// register has no uses or defs. The best split point is in the
    /// middle of the largest gap.
    pub fn compute_split_points(&mut self, interval: &LiveInterval, min_gap: u32) {
        let mut uses = interval.uses.clone();
        uses.sort();
        uses.dedup();

        if uses.len() < 2 {
            return;
        }

        // Find all gaps
        let mut gaps: Vec<(u32, u32)> = Vec::new(); // (gap_start, gap_size)
        for w in uses.windows(2) {
            let gap_size = w[1] - w[0];
            if gap_size >= min_gap {
                gaps.push((w[0], gap_size));
            }
        }

        // Sort by gap size descending, take the best ones
        gaps.sort_by(|a, b| b.1.cmp(&a.1));

        for &(gap_start, _) in &gaps {
            // Split in the middle of the gap
            let split_point = gap_start + min_gap / 2;
            self.split_points.push(split_point);

            // Limit number of splits
            if self.split_points.len() >= 3 {
                break;
            }
        }

        self.split_points.sort();
    }

    /// Check if splitting is likely beneficial.
    pub fn is_profitable(&self, interval: &LiveInterval) -> bool {
        if self.split_points.is_empty() {
            return false;
        }

        // Splitting is profitable if the live range is long and
        // we found at least one good gap
        interval.length() > 20 && !self.split_points.is_empty()
    }
}

// ============================================================================
// Register Priority — heuristic for selecting which vreg to allocate next
// ============================================================================

/// Register priority computation for greedy allocation.
///
/// Virtual registers with higher priority are allocated first because
/// they are more constrained (higher spill cost, more uses, longer
/// live ranges).
#[derive(Debug, Clone)]
pub struct RegisterPriority {
    /// Priority score for each virtual register.
    pub priorities: HashMap<VirtReg, f64>,
}

impl RegisterPriority {
    /// Create a new priority calculator.
    pub fn new() -> Self {
        RegisterPriority {
            priorities: HashMap::new(),
        }
    }

    /// Compute priorities for all virtual registers.
    pub fn compute(&mut self, intervals: &[LiveInterval], spill_costs: &HashMap<VirtReg, f64>) {
        // Priority = spill_cost * (1 + use_count / 10) / (1 + range_length / 100)
        // Higher priority values mean the register should be allocated earlier
        for li in intervals {
            let cost = spill_costs.get(&li.vreg).copied().unwrap_or(1.0);
            let use_factor = 1.0 + li.uses.len() as f64 / 10.0;
            let range_penalty = 1.0 + li.length() as f64 / 100.0;
            let priority = cost * use_factor / range_penalty;
            self.priorities.insert(li.vreg, priority);
        }
    }

    /// Get the priority of a virtual register.
    pub fn get_priority(&self, vreg: VirtReg) -> f64 {
        self.priorities.get(&vreg).copied().unwrap_or(0.0)
    }

    /// Sort virtual registers by descending priority.
    pub fn sort_by_priority(&self, intervals: &mut [LiveInterval]) {
        intervals.sort_by(|a, b| {
            let pa = self.get_priority(a.vreg);
            let pb = self.get_priority(b.vreg);
            pb.partial_cmp(&pa).unwrap_or(std::cmp::Ordering::Equal)
        });
    }
}

impl Default for RegisterPriority {
    fn default() -> Self {
        RegisterPriority::new()
    }
}

// ============================================================================
// Eviction Cost — analysis for picking which register to evict
// ============================================================================

/// Eviction cost analysis for greedy register allocation.
///
/// When no physical register is free, the allocator must evict an
/// already-assigned register. The eviction cost estimates how expensive
/// it would be to spill each candidate, and the cheapest is chosen.
#[derive(Debug, Clone)]
pub struct EvictionCost {
    /// Cost to evict each virtual register (by vreg).
    pub costs: HashMap<VirtReg, f64>,
}

impl EvictionCost {
    /// Create a new eviction cost calculator.
    pub fn new() -> Self {
        EvictionCost {
            costs: HashMap::new(),
        }
    }

    /// Compute eviction costs for all assigned registers.
    ///
    /// Eviction cost is based on:
    /// - Current spill cost of the register (lower = cheaper to evict)
    /// - How recently the register was assigned (recent = cheaper)
    /// - Number of remaining uses (fewer = cheaper)
    pub fn compute(
        &mut self,
        assigned: &HashMap<VirtReg, PhysReg>,
        intervals: &[LiveInterval],
        spill_costs: &HashMap<VirtReg, f64>,
        current_position: u32,
    ) {
        self.costs.clear();

        for (&vreg, _) in assigned {
            // Find the live interval for this vreg
            let interval = intervals.iter().find(|li| li.vreg == vreg);

            if let Some(li) = interval {
                // Base cost from spill analysis
                let base_cost = spill_costs.get(&vreg).copied().unwrap_or(100.0);

                // Remaining uses: fewer uses left = cheaper to evict now
                let remaining_uses = li
                    .uses
                    .iter()
                    .filter(|&&pos| pos >= current_position)
                    .count() as f64;

                // Cost adjusted by remaining uses
                let adjusted = base_cost * (remaining_uses / li.uses.len().max(1) as f64);

                self.costs.insert(vreg, adjusted);
            }
        }
    }

    /// Get the cheapest virtual register to evict.
    pub fn cheapest_to_evict(&self) -> Option<VirtReg> {
        self.costs
            .iter()
            .min_by(|(_, a), (_, b)| a.partial_cmp(b).unwrap_or(std::cmp::Ordering::Equal))
            .map(|(&vreg, _)| vreg)
    }
}

impl Default for EvictionCost {
    fn default() -> Self {
        EvictionCost::new()
    }
}

// ============================================================================
// Register Class Assignment — select best register class per virtual reg
// ============================================================================

/// Register class assignment for virtual registers.
///
/// Each virtual register belongs to a register class (e.g., GPR32, GPR64,
/// XMM, YMM). The register allocator must respect class constraints and
/// insert cross-class copies when a value moves between classes.
#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
pub enum RegClass {
    /// 64-bit general-purpose register (RAX-R15).
    Gpr64,
    /// 32-bit general-purpose register (EAX-R15D).
    Gpr32,
    /// 16-bit general-purpose register (AX-R15W).
    Gpr16,
    /// 8-bit general-purpose register (AL-R15B).
    Gpr8,
    /// 128-bit XMM register (XMM0-XMM15).
    Xmm,
    /// 256-bit YMM register (YMM0-YMM15).
    Ymm,
    /// 512-bit ZMM register (ZMM0-ZMM31).
    Zmm,
}

/// Register class assignment information for a virtual register.
#[derive(Debug, Clone)]
pub struct RegClassAssignment {
    /// The assigned register class.
    pub class: RegClass,
    /// Whether this assignment requires a cross-class copy.
    pub needs_copy: bool,
    /// Source register for the copy (if needed).
    pub copy_src: Option<VirtReg>,
}

/// Cross-class copy insertion logic.
#[derive(Debug, Clone)]
pub struct CrossClassCopyHandler {
    /// Cross-class copies to insert.
    pub copies: Vec<(VirtReg, VirtReg, RegClass, RegClass)>,
}

impl CrossClassCopyHandler {
    /// Create a new handler.
    pub fn new() -> Self {
        CrossClassCopyHandler { copies: Vec::new() }
    }

    /// Check if a cross-class copy is needed between two register classes.
    pub fn needs_cross_class_copy(from: RegClass, to: RegClass) -> bool {
        use RegClass::*;
        match (from, to) {
            // Sub-register copies don't need explicit instructions
            // (handled by register aliasing)
            (Gpr64, Gpr32) | (Gpr64, Gpr16) | (Gpr64, Gpr8) => false,
            (Gpr32, Gpr16) | (Gpr32, Gpr8) => false,
            (Gpr16, Gpr8) => false,
            // Up-casts are also handled by aliasing if on the same
            // architectural register
            (Gpr32, Gpr64) | (Gpr16, Gpr64) | (Gpr8, Gpr64) => false,
            // Cross-domain copies (GPR <-> XMM) need instructions
            (Gpr64, Xmm) | (Gpr32, Xmm) => true,
            (Xmm, Gpr64) | (Xmm, Gpr32) => true,
            // Vector size conversions may need explicit instructions
            (Xmm, Ymm) | (Ymm, Xmm) => false, // aliased in hardware
            (Ymm, Zmm) | (Zmm, Ymm) => false,
            _ => from != to,
        }
    }

    /// Record a cross-class copy that needs insertion.
    pub fn add_copy(
        &mut self,
        src: VirtReg,
        dst: VirtReg,
        from_class: RegClass,
        to_class: RegClass,
    ) {
        if Self::needs_cross_class_copy(from_class, to_class) {
            self.copies.push((src, dst, from_class, to_class));
        }
    }

    /// Emit cross-class copy instructions.
    pub fn emit_copies(&self, mf: &mut MachineFunction) {
        for &(src, dst, from_class, to_class) in &self.copies {
            let opcode = match (from_class, to_class) {
                (RegClass::Gpr64, RegClass::Xmm) => x86_opcodes::MOV, // MOVQ
                (RegClass::Xmm, RegClass::Gpr64) => x86_opcodes::MOV, // MOVQ
                _ => x86_opcodes::MOV,
            };

            let mut copy_instr = MachineInstr::new(opcode);
            copy_instr.operands.push(MachineOperand::Reg(src));
            copy_instr.def = Some(dst);

            // Insert at end of first block (conservative)
            if let Some(bb) = mf.blocks.first_mut() {
                bb.instructions.push(copy_instr);
            }
        }
    }
}

impl Default for CrossClassCopyHandler {
    fn default() -> Self {
        CrossClassCopyHandler::new()
    }
}

// ============================================================================
// Coalescing during Greedy RA — prefer same register for COPY-connected vregs
// ============================================================================

impl GreedyRegAlloc {
    /// Perform copy coalescing during greedy register allocation.
    ///
    /// When two virtual registers are connected by a COPY instruction
    /// (MOV vreg1, vreg2), they should ideally be assigned the same
    /// physical register so the copy can be eliminated.
    fn coalesce_copies_greedy(&mut self, mf: &mut MachineFunction) {
        let mut coalesced = 0usize;

        // Find all COPY pairs (MOV src, dst where both are virtual regs)
        let mut copy_pairs: Vec<(VirtReg, VirtReg)> = Vec::new();
        for bb in &mf.blocks {
            for mi in &bb.instructions {
                if mi.opcode == x86_opcodes::MOV && mi.operands.len() >= 2 {
                    if let (MachineOperand::Reg(src), Some(dst)) = (mi.operands[0].clone(), mi.def)
                    {
                        copy_pairs.push((src, dst));
                    }
                }
            }
        }

        // For each copy pair, try to assign the same physical register
        for (src, dst) in copy_pairs {
            // Check if both are assigned
            let src_phys = self.assignments.get(&src).copied();
            let dst_phys = self.assignments.get(&dst).copied();

            match (src_phys, dst_phys) {
                (Some(sp), Some(dp)) if sp != dp => {
                    // Both assigned to different registers - check if we
                    // can reassign one to match the other
                    if !self.interference.interfere(src, dst) {
                        // Safe to merge: reassign dst to src's register
                        self.assignments.insert(dst, sp);
                        self.phys_to_vreg.insert(sp, dst);
                        coalesced += 1;
                    }
                }
                (Some(sp), None) => {
                    // Only src assigned - assign dst to same register
                    let used_by_src: HashSet<PhysReg> = {
                        let mut s = HashSet::new();
                        s.insert(sp);
                        s
                    };
                    let free = self.available.iter().find(|r| !used_by_src.contains(r));
                    if let Some(&free_reg) = free {
                        self.assign(dst, free_reg);
                        coalesced += 1;
                    } else {
                        self.assign(dst, sp);
                        coalesced += 1;
                    }
                }
                (None, Some(dp)) => {
                    // Only dst assigned - assign src to same register
                    self.assign(src, dp);
                    coalesced += 1;
                }
                (None, None) => {
                    // Neither assigned - pick a free register for both
                    if let Some(&reg) = self.available.first() {
                        self.assign(src, reg);
                        self.assign(dst, reg);
                        coalesced += 1;
                    }
                }
                (Some(_), Some(_)) => {
                    // Already same register - nothing to do
                }
            }
        }

        self.copies_coalesced = coalesced;
    }
}

// ============================================================================
// Tests — Existing tests preserved
// ============================================================================

#[cfg(test)]
mod tests {
    use super::*;
    use crate::context::LLVMContext;
    use crate::function;
    use crate::instruction;

    fn build_simple_func() -> ValueRef {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("test", ctx.i32(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let ret = instruction::ret_val(crate::constants::const_i32(42));
        entry.borrow_mut().push_operand(ret);
        func.borrow_mut().push_operand(entry);
        func
    }

    #[test]
    fn test_compile_simple_function() {
        let func = build_simple_func();
        let asm = compile_function(&func);
        assert!(asm.contains(".globl test"));
        assert!(asm.contains("ret"));
    }

    #[test]
    fn test_compile_empty_function() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("empty", ctx.void_ty(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let ret = instruction::ret_void();
        entry.borrow_mut().push_operand(ret);
        func.borrow_mut().push_operand(entry);

        let asm = compile_function(&func);
        assert!(asm.contains("ret"));
    }

    #[test]
    fn test_compile_function_with_add() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("add_test", ctx.i32(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let a = crate::constants::const_i32(10);
        let b = crate::constants::const_i32(20);
        let add = instruction::add(a, b);
        add.borrow_mut().name = "sum".into();
        entry.borrow_mut().push_operand(add.clone());
        let ret = instruction::ret_val(add);
        entry.borrow_mut().push_operand(ret);
        func.borrow_mut().push_operand(entry);

        let asm = compile_function(&func);
        assert!(asm.contains("add"), "Should contain add: {}", asm);
        assert!(asm.contains("ret"));
    }

    #[test]
    fn test_compile_branch() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("branch_test", ctx.void_ty(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let then_bb = crate::basic_block::new_basic_block("then");
        let else_bb = crate::basic_block::new_basic_block("else");

        let cond = crate::constants::const_bool(true);
        entry.borrow_mut().push_operand(instruction::br_cond(
            cond,
            then_bb.clone(),
            else_bb.clone(),
        ));

        then_bb.borrow_mut().push_operand(instruction::ret_void());
        else_bb.borrow_mut().push_operand(instruction::ret_void());

        func.borrow_mut().push_operand(entry);
        func.borrow_mut().push_operand(then_bb);
        func.borrow_mut().push_operand(else_bb);

        let asm = compile_function(&func);
        assert!(asm.contains("jmp") || asm.contains("jne") || asm.contains("je"));
    }

    #[test]
    fn test_selector_handles_alloca() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("alloca_test", ctx.void_ty(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let alloca = instruction::alloca(ctx.i32());
        alloca.borrow_mut().name = "p".into();
        entry.borrow_mut().push_operand(alloca);
        entry.borrow_mut().push_operand(instruction::ret_void());
        func.borrow_mut().push_operand(entry);

        let asm = compile_function(&func);
        // Should not panic; may or may not contain specific instructions
        assert!(asm.len() > 0);
    }

    #[test]
    fn test_compile_with_icmp() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("cmp_test", ctx.i1(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let a = crate::constants::const_i32(5);
        let b = crate::constants::const_i32(10);
        let icmp = instruction::icmp(crate::opcode::ICmpPred::Eq, a, b);
        icmp.borrow_mut().name = "cmp".into();
        entry.borrow_mut().push_operand(icmp.clone());
        entry.borrow_mut().push_operand(instruction::ret_val(icmp));
        func.borrow_mut().push_operand(entry);

        let asm = compile_function(&func);
        assert!(asm.contains("cmp"));
    }
}

// ============================================================================
// New Tests — Register Allocator, TargetInfo, Pipeline, ISel
// ============================================================================

#[cfg(test)]
mod regalloc_tests {
    use super::*;
    use crate::context::LLVMContext;
    use crate::function;
    use crate::instruction;

    fn build_add_func() -> ValueRef {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("add_func", ctx.i32(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let a = crate::constants::const_i32(10);
        let b = crate::constants::const_i32(20);
        let add = instruction::add(a, b);
        add.borrow_mut().name = "result".into();
        entry.borrow_mut().push_operand(add.clone());
        entry.borrow_mut().push_operand(instruction::ret_val(add));
        func.borrow_mut().push_operand(entry);
        func
    }

    fn build_multi_block_func() -> ValueRef {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("multi", ctx.i32(), &[ctx.i32()]);
        let entry = crate::basic_block::new_basic_block("entry");
        let then_bb = crate::basic_block::new_basic_block("then");
        let else_bb = crate::basic_block::new_basic_block("else");

        let cond = crate::constants::const_bool(true);
        entry.borrow_mut().push_operand(instruction::br_cond(
            cond,
            then_bb.clone(),
            else_bb.clone(),
        ));

        let a = crate::constants::const_i32(1);
        let b = crate::constants::const_i32(2);
        let add = instruction::add(a, b);
        then_bb.borrow_mut().push_operand(add.clone());
        then_bb.borrow_mut().push_operand(instruction::ret_val(add));

        let c = crate::constants::const_i32(3);
        else_bb.borrow_mut().push_operand(instruction::ret_val(c));

        func.borrow_mut().push_operand(entry);
        func.borrow_mut().push_operand(then_bb);
        func.borrow_mut().push_operand(else_bb);
        func
    }

    // === TargetRegInfo Tests ===

    #[test]
    fn test_target_reg_info_for_x86_64() {
        let info = TargetRegInfo::for_x86_64();
        assert_eq!(info.gpr_count, 16);
        assert_eq!(info.fpr_count, 16);
        assert_eq!(info.reg_size, 8);
        assert!(info.reserved.contains(&4)); // rsp
        assert!(info.callee_saved.contains(&3)); // rbx
    }

    #[test]
    fn test_target_reg_info_for_aarch64() {
        let info = TargetRegInfo::for_aarch64();
        assert_eq!(info.gpr_count, 32);
        assert_eq!(info.reg_size, 8);
        assert!(info.reserved.contains(&31)); // sp/xzr
        assert!(info.callee_saved.contains(&19));
    }

    #[test]
    fn test_target_reg_info_for_riscv64() {
        let info = TargetRegInfo::for_riscv64();
        assert_eq!(info.gpr_count, 32);
        assert_eq!(info.reg_size, 8);
        assert!(info.reserved.contains(&0)); // zero
        assert!(info.callee_saved.contains(&8)); // s0
    }

    #[test]
    fn test_target_reg_info_is_allocatable() {
        let info = TargetRegInfo::for_x86_64();
        assert!(!info.is_allocatable(4)); // rsp is reserved
        assert!(info.is_allocatable(0)); // rax is allocatable
    }

    #[test]
    fn test_target_reg_info_allocatable_regs() {
        let info = TargetRegInfo::for_x86_64();
        let regs = info.allocatable_regs();
        assert!(!regs.contains(&4)); // rsp excluded
        assert!(!regs.is_empty());
    }

    // === LiveInterval Tests ===

    #[test]
    fn test_live_interval_new() {
        let li = LiveInterval::new(0);
        assert_eq!(li.vreg, 0);
        assert_eq!(li.start, u32::MAX);
        assert_eq!(li.end, 0);
        assert!(li.uses.is_empty());
        assert!(li.defs.is_empty());
    }

    #[test]
    fn test_live_interval_overlaps() {
        let a = LiveInterval {
            vreg: 0,
            start: 0,
            end: 10,
            uses: vec![5],
            defs: vec![0],
        };
        let b = LiveInterval {
            vreg: 1,
            start: 5,
            end: 15,
            uses: vec![10],
            defs: vec![5],
        };
        assert!(a.overlaps(&b));
    }

    #[test]
    fn test_live_interval_no_overlap() {
        let a = LiveInterval {
            vreg: 0,
            start: 0,
            end: 5,
            uses: vec![3],
            defs: vec![0],
        };
        let b = LiveInterval {
            vreg: 1,
            start: 10,
            end: 15,
            uses: vec![12],
            defs: vec![10],
        };
        assert!(!a.overlaps(&b));
    }

    #[test]
    fn test_live_interval_live_at() {
        let li = LiveInterval {
            vreg: 0,
            start: 5,
            end: 20,
            uses: vec![10],
            defs: vec![5],
        };
        assert!(li.live_at(10));
        assert!(!li.live_at(0));
        assert!(li.live_at(5));
        assert!(li.live_at(20));
    }

    #[test]
    fn test_live_interval_recompute_bounds() {
        let mut li = LiveInterval::new(7);
        li.defs = vec![5, 15];
        li.uses = vec![10, 20];
        li.recompute_bounds();
        assert_eq!(li.start, 5);
        assert_eq!(li.end, 20);
    }

    // === RegAlloc Tests ===

    #[test]
    fn test_regalloc_new() {
        let target = TargetRegInfo::for_x86_64();
        let ra = RegAlloc::new(target);
        assert!(ra.assignments.is_empty());
        assert!(ra.spilled.is_empty());
        assert_eq!(ra.frame_offset, 0);
    }

    #[test]
    fn test_regalloc_allocate_simple() {
        let func = build_add_func();
        let mut mf = MachineFunction::new("test");
        InstructionSelector::select(&mut mf, &func);

        let target = TargetRegInfo::for_x86_64();
        let mut ra = RegAlloc::new(target);
        let result = ra.allocate(&mut mf);

        assert!(result.success);
        assert!(!ra.assignments.is_empty());
    }

    #[test]
    fn test_regalloc_compute_live_intervals() {
        let func = build_add_func();
        let mut mf = MachineFunction::new("test");
        InstructionSelector::select(&mut mf, &func);

        let target = TargetRegInfo::for_x86_64();
        let mut ra = RegAlloc::new(target);
        let intervals = ra.compute_live_intervals(&mf);

        assert!(!intervals.is_empty());
    }

    #[test]
    fn test_regalloc_coalesce_copies() {
        let target = TargetRegInfo::for_x86_64();
        let mut ra = RegAlloc::new(target);

        let mut mf = MachineFunction::new("coalesce_test");
        let v0 = mf.new_vreg();
        let v1 = mf.new_vreg();
        ra.assignments.insert(v0, 0);
        ra.assignments.insert(v1, 0);

        // mov v1, v0 — should be coalesced since both map to phys reg 0
        let mut mov = MachineInstr::new(x86_opcodes::MOV).with_def(v1);
        mov.push_reg(v0);

        let bb = MachineBasicBlock {
            name: "entry".into(),
            instructions: vec![mov],
            successors: vec![],
            ..Default::default()
        };
        mf.push_block(bb);

        let coalesced = ra.coalesce_copies(&mut mf);
        assert_eq!(coalesced, 1);
        assert!(mf.blocks[0].instructions.is_empty());
    }

    #[test]
    fn test_regalloc_eliminate_dead_code() {
        let target = TargetRegInfo::for_x86_64();
        let mut ra = RegAlloc::new(target);

        let mut mf = MachineFunction::new("dead_test");
        let v0 = mf.new_vreg();
        let v1 = mf.new_vreg();

        // Instruction that defines v0 but v0 is never used
        let dead_mov = MachineInstr::new(x86_opcodes::MOV).with_def(v0);

        // Live: defines v1, uses v1 in next instruction
        let live_mov = MachineInstr::new(x86_opcodes::MOV).with_def(v1);
        let mut use_mov = MachineInstr::new(x86_opcodes::ADD).with_def(mf.new_vreg());
        use_mov.push_reg(v1);

        let bb = MachineBasicBlock {
            name: "entry".into(),
            instructions: vec![dead_mov, live_mov, use_mov],
            successors: vec![],
            ..Default::default()
        };
        mf.push_block(bb);

        ra.eliminate_dead_code(&mut mf);

        // Dead mov should be removed
        assert_eq!(mf.blocks[0].instructions.len(), 2);
    }

    // === RegAllocResult Tests ===

    #[test]
    fn test_regalloc_result_success() {
        let result = RegAllocResult::success();
        assert!(result.success);
        assert_eq!(result.spills, 0);
        assert_eq!(result.reloads, 0);
        assert_eq!(result.copies_coalesced, 0);
    }

    #[test]
    fn test_regalloc_result_failure() {
        let result = RegAllocResult::failure();
        assert!(!result.success);
    }

    // === TargetISel Tests ===

    #[test]
    fn test_x86_target_isel_select() {
        let isel = X86TargetISel;
        let func = build_add_func();
        let mut mf = MachineFunction::new("isel_test");
        isel.select(&mut mf, &func);
        assert!(!mf.blocks.is_empty());
    }

    #[test]
    fn test_x86_target_isel_reg_info() {
        let isel = X86TargetISel;
        let info = isel.get_target_reg_info();
        assert_eq!(info.gpr_count, 16);
    }

    #[test]
    fn test_x86_target_isel_frame_lowering() {
        let isel = X86TargetISel;
        let fl = isel.get_frame_lowering();
        let func = build_add_func();
        assert!(!fl.needs_frame_pointer(&func));
    }

    // === FrameLowering Tests ===

    #[test]
    fn test_x86_frame_lowering_prologue() {
        let fl = X86FrameLowering;
        let mut mf = MachineFunction::new("test");
        let prologue = fl.emit_prologue(&mut mf);
        assert!(!prologue.is_empty());
        assert_eq!(prologue[0].opcode, x86_opcodes::PUSH);
    }

    #[test]
    fn test_x86_frame_lowering_epilogue() {
        let fl = X86FrameLowering;
        let mut mf = MachineFunction::new("test");
        let epilogue = fl.emit_epilogue(&mut mf);
        assert!(!epilogue.is_empty());
    }

    #[test]
    fn test_x86_frame_lowering_needs_frame_pointer_with_alloca() {
        let mut ctx = LLVMContext::new();
        let func = function::new_function("alloca_func", ctx.void_ty(), &[]);
        let entry = crate::basic_block::new_basic_block("entry");
        let alloca = instruction::alloca(ctx.i32());
        entry.borrow_mut().push_operand(alloca);
        entry.borrow_mut().push_operand(instruction::ret_void());
        func.borrow_mut().push_operand(entry);

        let fl = X86FrameLowering;
        assert!(fl.needs_frame_pointer(&func));
    }

    // === Pipeline Tests ===

    #[test]
    fn test_compile_function_with_pipeline() {
        let func = build_add_func();
        let isel = X86TargetISel;
        let asm = compile_function_with_pipeline(&func, &isel);
        assert!(asm.contains(".globl add_func"));
        assert!(asm.contains("ret"));
    }

    #[test]
    fn test_compile_function_with_pipeline_multi_block() {
        let func = build_multi_block_func();
        let isel = X86TargetISel;
        let asm = compile_function_with_pipeline(&func, &isel);
        assert!(asm.contains(".globl multi"));
        assert!(asm.len() > 0);
    }
}