#ifndef HTP_OPS_H
#define HTP_OPS_H
#include <assert.h>
enum htp_status {
HTP_STATUS_OK = 1,
HTP_STATUS_INTERNAL_ERR = 2,
HTP_STATUS_NO_SUPPORT = 3,
HTP_STATUS_INVAL_PARAMS = 4,
HTP_STATUS_VTCM_TOO_SMALL = 5,
};
enum htp_data_type {
HTP_TYPE_F32 = 0,
HTP_TYPE_F16 = 1,
HTP_TYPE_Q4_0 = 2,
HTP_TYPE_Q4_1 = 3,
HTP_TYPE_Q8_0 = 8,
HTP_TYPE_Q2_K = 10,
HTP_TYPE_Q3_K = 11,
HTP_TYPE_Q4_K = 12,
HTP_TYPE_Q5_K = 13,
HTP_TYPE_Q6_K = 14,
HTP_TYPE_IQ4_NL = 20,
HTP_TYPE_I32 = 26,
HTP_TYPE_I64 = 27,
HTP_TYPE_BF16 = 30,
HTP_TYPE_MXFP4 = 39,
HTP_TYPE_Q1_0 = 41,
HTP_TYPE_Q2_0 = 42,
HTP_TYPE_INVALID
};
enum htp_op_code {
HTP_OP_MUL = 0,
HTP_OP_ADD = 1,
HTP_OP_SUB = 2,
HTP_OP_DIV = 3,
HTP_OP_MUL_MAT,
HTP_OP_MUL_MAT_ID,
HTP_OP_MUL_MAT_NX,
HTP_OP_MUL_MAT_ID_NX,
HTP_OP_MUL_MAT_ADD,
HTP_OP_RMS_NORM,
HTP_OP_RMS_NORM_MUL,
HTP_OP_UNARY_SILU,
HTP_OP_UNARY_GELU,
HTP_OP_UNARY_SIGMOID,
HTP_OP_UNARY_EXP,
HTP_OP_UNARY_NEG,
HTP_OP_UNARY_SOFTPLUS,
HTP_OP_UNARY_TANH,
HTP_OP_UNARY_ABS,
HTP_OP_UNARY_LOG,
HTP_OP_UNARY_RELU,
HTP_OP_UNARY_STEP,
HTP_OP_GLU_SWIGLU,
HTP_OP_GLU_SWIGLU_OAI,
HTP_OP_GLU_GEGLU,
HTP_OP_GLU_GEGLU_QUICK,
HTP_OP_SOFTMAX,
HTP_OP_ADD_ID,
HTP_OP_ROPE,
HTP_OP_FLASH_ATTN_EXT,
HTP_OP_SET_ROWS,
HTP_OP_GET_ROWS,
HTP_OP_SCALE,
HTP_OP_CPY,
HTP_OP_CPY_FENCE,
HTP_OP_ARGSORT,
HTP_OP_TOP_K,
HTP_OP_SQR,
HTP_OP_SQRT,
HTP_OP_SUM,
HTP_OP_SUM_ROWS,
HTP_OP_SSM_CONV,
HTP_OP_REPEAT,
HTP_OP_CUMSUM,
HTP_OP_FILL,
HTP_OP_DIAG,
HTP_OP_SOLVE_TRI,
HTP_OP_L2_NORM,
HTP_OP_GATED_DELTA_NET,
HTP_OP_TRI,
HTP_OP_PAD,
HTP_OP_NORM,
HTP_OP_CONCAT,
HTP_OP_CLAMP,
HTP_OP_LEAKY_RELU,
HTP_OP_IM2COL,
HTP_OP_CONV_2D,
HTP_OP_CONV_2D_DW,
HTP_OP_FENCE,
HTP_OP_ALLREDUCE,
HTP_OP_ALLREDUCE_ADD,
HTP_OP_GLU_SWIGLU_CLAMP,
HTP_OP_MDEV_GROUP,
HTP_OP_ROLL,
HTP_OP_ARGMAX,
HTP_OP_UNARY_GELU_ERF,
HTP_OP_GLU_GEGLU_ERF,
HTP_OP_POOL_2D,
HTP_OP_POOL_1D,
HTP_OP_UNARY_GELU_QUICK,
HTP_OP_IM2COL_3D,
HTP_OP_HADAMARD,
HTP_OP_GLU_REGLU,
HTP_OP_GLU_SIGMOID,
HTP_OP_UNARY_CEIL,
HTP_OP_UNARY_SGN,
HTP_OP_UPSCALE,
HTP_OP_INVALID
};
#define HTP_OP_MAX_DIMS 4
#define HTP_OP_MAX_INPUTS 10
#define HTP_OP_MAX_OUTPUTS 4
#define HTP_OP_MAX_PARAMS 16
#define HTP_OP_MAX_KERN_PARAMS 32
#define HTP_OP_MAX_BUFS 64
#define HTP_OP_MAX_TENSORS 65534
#define HTP_FENCE_TIMEOUT (1000000000ULL)
#define HTP_FENCE_SLOT_SIZE 128
#define HTP_OP_MAX_VMEM_DEFAULT (3355443200u)
#define HTP_MMAP_MAX_VMEM (2147483648u)
#define HTP_DDR_SPAD_SIZE (512 * 1024)
enum htp_tensor_flags {
HTP_TENSOR_WEIGHT = (1U << 0), HTP_TENSOR_TILED = (1U << 1), HTP_TENSOR_FENCE = (1U << 2), HTP_TENSOR_FUSEABLE = (1U << 3), };
enum htp_buf_flags {
HTP_BUF_EXTENDED = (1U << 0),
};
struct htp_tensor {
uint64_t data; uint32_t size; uint32_t flags; uint32_t type; uint16_t bi; uint16_t ti; uint32_t ne[HTP_OP_MAX_DIMS]; uint32_t nb[HTP_OP_MAX_DIMS]; };
struct htp_buf_desc {
uint64_t base; uint64_t size; uint32_t flags; uint32_t fd; };
enum htp_op_flags {
HTP_OPFLAGS_STUB = (1U << 0),
};
struct htp_op_desc {
uint32_t opcode; uint32_t flags; int32_t params[HTP_OP_MAX_PARAMS]; int32_t kernel_params[HTP_OP_MAX_KERN_PARAMS]; uint16_t src[HTP_OP_MAX_INPUTS]; uint16_t dst[HTP_OP_MAX_OUTPUTS]; uint16_t pad[2]; };
#ifndef HTP_MAX_NTHREADS
#define HTP_MAX_NTHREADS 10
#endif
#define HTP_TRACE_MAX_EVENTS 256
enum htp_profiler_mode {
HTP_PROF_DISABLED = 0,
HTP_PROF_BASIC = 1,
HTP_PROF_PMU = 2,
HTP_PROF_TRACE = 3,
};
enum htp_power_mode {
HTP_POWER_MODE_LOW_POWER_SAVER = 0,
HTP_POWER_MODE_POWER_SAVER = 1,
HTP_POWER_MODE_HIGH_POWER_SAVER = 2,
HTP_POWER_MODE_LOW_BALANCED = 3,
HTP_POWER_MODE_BALANCED = 4,
HTP_POWER_MODE_HIGH_PERFORMANCE = 5,
HTP_POWER_MODE_SUSTAINED_HIGH_PERFORMANCE = 6,
HTP_POWER_MODE_BURST = 7,
HTP_POWER_MODE_COUNT
};
enum htp_trace_event_id {
HTP_TRACE_EVT_DMA = 0,
HTP_TRACE_EVT_L2FLUSH = 1,
HTP_TRACE_EVT_INIT = 2,
HTP_TRACE_EVT_BUFF = 3,
HTP_TRACE_EVT_FENCE = 4,
HTP_TRACE_EVT_HVX_COMP = 20,
HTP_TRACE_EVT_HVX_A_QUANT = 21,
HTP_TRACE_EVT_HVX_A_PREP = 22,
HTP_TRACE_EVT_HVX_W_DEQUANT = 23,
HTP_TRACE_EVT_HVX_W_PREP = 24,
HTP_TRACE_EVT_HVX_O_PROC = 25,
HTP_TRACE_EVT_HVX_FA_QK = 26,
HTP_TRACE_EVT_HVX_FA_SFM = 27,
HTP_TRACE_EVT_HVX_FA_Q_PREP = 28,
HTP_TRACE_EVT_HVX_FA_K_PREP = 29,
HTP_TRACE_EVT_HVX_FA_V_PREP = 30,
HTP_TRACE_EVT_HVX_GDN_PREP = 31,
HTP_TRACE_EVT_HVX_GDN_SOLVE = 32,
HTP_TRACE_EVT_HVX_GDN_V_PREP = 33,
HTP_TRACE_EVT_HVX_GDN_D_PREP = 34,
HTP_TRACE_EVT_HVX_GDN_OUT = 35,
HTP_TRACE_EVT_HVX_GDN_STATE = 36,
HTP_TRACE_EVT_HVX_GDN_REM = 37,
HTP_TRACE_EVT_HMX_COMP = 40,
};
struct htp_trace_desc {
uint32_t cycles; uint16_t id; uint16_t info; };
#define HTP_PROF_PMU_NCNT 8
struct htp_prof_desc {
uint32_t opcode; uint32_t usecs; uint32_t cycles_start; uint32_t cycles_stop; uint32_t pmu[HTP_PROF_PMU_NCNT]; };
struct htp_opbatch_req {
uint64_t seq; uint32_t n_bufs; uint32_t n_tensors; uint32_t n_ops; uint32_t n_traces; };
struct htp_opbatch_rsp {
uint64_t seq; uint64_t cycles_start; uint64_t cycles_stop; uint32_t status; uint32_t n_bufs; uint32_t n_tensors; uint32_t n_ops; uint32_t usecs; uint32_t n_traces[HTP_MAX_NTHREADS + 1];
};
#endif