Rust Litex HAL

A Rust embedded HAL crate for LiteX cores. It contains basic HAL traits for GPIO, UART, SPI, and delay.

More info and instructions on my blog and example project in this repo

The repository also contains an example that you can run on Verilator using litex_sim.

Compiling and simulating the example

Compilation

The following dependencies are required to generate Rust code for peripherals (also called Peripheral Access Crate or PAC) and build the example for it.

Rust target for RISCV 32I

Our example use VexRiscv, so to be able to compile them you need to add riscv32i-unknown-none-elf target for Rust.

rustup target add riscv32i-unknown-none-elf

Python

For LiteX scripts.

• ArchLinux:

sudo pacman -S python

• Ubuntu:

sudo apt install python3

• Universal LiteX script

Official instructions.

LiteX

To build cores and optionally simulate it using verilator.

Official instructions.

Simulation on litex_sim

The following dependencies are required if you want to run the example on litex_sim.

Cross compiler for RISCV 32I

To compile VexRiscv soft core. RISCV 64 can also build RISCV 32.

• ArchLinux:

sudo pacman -S riscv64-elf-gcc

• Ubuntu:

sudo apt install gcc-riscv64-unknown-elf

Verilator

Simulator to run simulation.

• ArchLinux:

sudo pacman -S verilator

• Ubuntu:

sudo apt install verilator

Simulation

To run the simulation execute the following command:

cargo xtask simulate --example counter

You can also pass --release to the simulation command.