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//! Abstract Syntax Tree (AST) for the Limen graph DSL.
//!
//! This module defines the in-memory representation produced by the parser
//! (`parse` module) and consumed by the validator (`validate` module) and the
//! code emitter (`gen` module).
//!
//! ## Notes
//! - Indices (`idx`, `from_node`, `to_node`, etc.) are parsed as raw numbers.
//! Structural constraints (contiguous ranges, port bounds, payload agreement,
//! queue uniformity) are enforced in `validate`, not here.
//! - `syn::TypePath`, `syn::Type`, and `syn::Expr` allow the DSL to embed
//! Rust paths, types, and expressions verbatim (for node/edge types,
//! payload types, and policies).
use ;
/// A complete graph definition: visibility, type name, nodes, and edges.
/// A single node declaration.
///
/// The node describes its concrete implementation type and its I/O shape.
/// Optional metadata includes a human-readable name and an ingress policy.
/// The latter creates a *synthetic* ingress edge for source nodes
/// (`in_ports == 0 && out_ports > 0`), consumed by the generator.
/// A single edge declaration.
///
/// Each edge binds one upstream node’s output port to one downstream node’s
/// input port, specifying the queue type, payload type, and policy.
///
/// The generator also creates **synthetic** ingress edges (not represented by
/// `EdgeDef`) for nodes that declare `ingress_policy_opt`; those are handled
/// internally during code emission.