#[allow(non_camel_case_types)]
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub enum Opcode {
PHI,
INLINEASM,
INLINEASM_BR,
CFI_INSTRUCTION,
EH_LABEL,
GC_LABEL,
ANNOTATION_LABEL,
KILL,
EXTRACT_SUBREG,
INSERT_SUBREG,
IMPLICIT_DEF,
INIT_UNDEF,
SUBREG_TO_REG,
COPY_TO_REGCLASS,
DBG_VALUE,
DBG_VALUE_LIST,
DBG_INSTR_REF,
DBG_PHI,
DBG_LABEL,
REG_SEQUENCE,
COPY,
COPY_LANEMASK,
BUNDLE,
LIFETIME_START,
LIFETIME_END,
PSEUDO_PROBE,
ARITH_FENCE,
STACKMAP,
FENTRY_CALL,
PATCHPOINT,
LOAD_STACK_GUARD,
PREALLOCATED_SETUP,
PREALLOCATED_ARG,
STATEPOINT,
LOCAL_ESCAPE,
FAULTING_OP,
PATCHABLE_OP,
PATCHABLE_FUNCTION_ENTER,
PATCHABLE_RET,
PATCHABLE_FUNCTION_EXIT,
PATCHABLE_TAIL_CALL,
PATCHABLE_EVENT_CALL,
PATCHABLE_TYPED_EVENT_CALL,
ICALL_BRANCH_FUNNEL,
FAKE_USE,
MEMBARRIER,
JUMP_TABLE_DEBUG_INFO,
RELOC_NONE,
CONVERGENCECTRL_ENTRY,
CONVERGENCECTRL_ANCHOR,
CONVERGENCECTRL_LOOP,
CONVERGENCECTRL_GLUE,
G_ASSERT_SEXT,
G_ASSERT_ZEXT,
G_ASSERT_ALIGN,
G_ADD,
G_SUB,
G_MUL,
G_SDIV,
G_UDIV,
G_SREM,
G_UREM,
G_SDIVREM,
G_UDIVREM,
G_AND,
G_OR,
G_XOR,
G_ABDS,
G_ABDU,
G_UAVGFLOOR,
G_UAVGCEIL,
G_SAVGFLOOR,
G_SAVGCEIL,
G_IMPLICIT_DEF,
G_PHI,
G_FRAME_INDEX,
G_GLOBAL_VALUE,
G_PTRAUTH_GLOBAL_VALUE,
G_CONSTANT_POOL,
G_EXTRACT,
G_UNMERGE_VALUES,
G_INSERT,
G_MERGE_VALUES,
G_BUILD_VECTOR,
G_BUILD_VECTOR_TRUNC,
G_CONCAT_VECTORS,
G_PTRTOINT,
G_INTTOPTR,
G_BITCAST,
G_FREEZE,
G_CONSTANT_FOLD_BARRIER,
G_INTRINSIC_FPTRUNC_ROUND,
G_INTRINSIC_TRUNC,
G_INTRINSIC_ROUND,
G_INTRINSIC_LRINT,
G_INTRINSIC_LLRINT,
G_INTRINSIC_ROUNDEVEN,
G_READCYCLECOUNTER,
G_READSTEADYCOUNTER,
G_LOAD,
G_SEXTLOAD,
G_ZEXTLOAD,
G_INDEXED_LOAD,
G_INDEXED_SEXTLOAD,
G_INDEXED_ZEXTLOAD,
G_STORE,
G_INDEXED_STORE,
G_ATOMIC_CMPXCHG_WITH_SUCCESS,
G_ATOMIC_CMPXCHG,
G_ATOMICRMW_XCHG,
G_ATOMICRMW_ADD,
G_ATOMICRMW_SUB,
G_ATOMICRMW_AND,
G_ATOMICRMW_NAND,
G_ATOMICRMW_OR,
G_ATOMICRMW_XOR,
G_ATOMICRMW_MAX,
G_ATOMICRMW_MIN,
G_ATOMICRMW_UMAX,
G_ATOMICRMW_UMIN,
G_ATOMICRMW_FADD,
G_ATOMICRMW_FSUB,
G_ATOMICRMW_FMAX,
G_ATOMICRMW_FMIN,
G_ATOMICRMW_FMAXIMUM,
G_ATOMICRMW_FMINIMUM,
G_ATOMICRMW_UINC_WRAP,
G_ATOMICRMW_UDEC_WRAP,
G_ATOMICRMW_USUB_COND,
G_ATOMICRMW_USUB_SAT,
G_FENCE,
G_PREFETCH,
G_BRCOND,
G_BRINDIRECT,
G_INVOKE_REGION_START,
G_INTRINSIC,
G_INTRINSIC_W_SIDE_EFFECTS,
G_INTRINSIC_CONVERGENT,
G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
G_ANYEXT,
G_TRUNC,
G_TRUNC_SSAT_S,
G_TRUNC_SSAT_U,
G_TRUNC_USAT_U,
G_CONSTANT,
G_FCONSTANT,
G_VASTART,
G_VAARG,
G_SEXT,
G_SEXT_INREG,
G_ZEXT,
G_SHL,
G_LSHR,
G_ASHR,
G_FSHL,
G_FSHR,
G_ROTR,
G_ROTL,
G_ICMP,
G_FCMP,
G_SCMP,
G_UCMP,
G_SELECT,
G_UADDO,
G_UADDE,
G_USUBO,
G_USUBE,
G_SADDO,
G_SADDE,
G_SSUBO,
G_SSUBE,
G_UMULO,
G_SMULO,
G_UMULH,
G_SMULH,
G_UADDSAT,
G_SADDSAT,
G_USUBSAT,
G_SSUBSAT,
G_USHLSAT,
G_SSHLSAT,
G_SMULFIX,
G_UMULFIX,
G_SMULFIXSAT,
G_UMULFIXSAT,
G_SDIVFIX,
G_UDIVFIX,
G_SDIVFIXSAT,
G_UDIVFIXSAT,
G_FADD,
G_FSUB,
G_FMUL,
G_FMA,
G_FMAD,
G_FDIV,
G_FREM,
G_FMODF,
G_FPOW,
G_FPOWI,
G_FEXP,
G_FEXP2,
G_FEXP10,
G_FLOG,
G_FLOG2,
G_FLOG10,
G_FLDEXP,
G_FFREXP,
G_FNEG,
G_FPEXT,
G_FPTRUNC,
G_FPTOSI,
G_FPTOUI,
G_SITOFP,
G_UITOFP,
G_FPTOSI_SAT,
G_FPTOUI_SAT,
G_FABS,
G_FCOPYSIGN,
G_IS_FPCLASS,
G_FCANONICALIZE,
G_FMINNUM,
G_FMAXNUM,
G_FMINNUM_IEEE,
G_FMAXNUM_IEEE,
G_FMINIMUM,
G_FMAXIMUM,
G_FMINIMUMNUM,
G_FMAXIMUMNUM,
G_GET_FPENV,
G_SET_FPENV,
G_RESET_FPENV,
G_GET_FPMODE,
G_SET_FPMODE,
G_RESET_FPMODE,
G_GET_ROUNDING,
G_SET_ROUNDING,
G_PTR_ADD,
G_PTRMASK,
G_SMIN,
G_SMAX,
G_UMIN,
G_UMAX,
G_ABS,
G_LROUND,
G_LLROUND,
G_BR,
G_BRJT,
G_VSCALE,
G_INSERT_SUBVECTOR,
G_EXTRACT_SUBVECTOR,
G_INSERT_VECTOR_ELT,
G_EXTRACT_VECTOR_ELT,
G_SHUFFLE_VECTOR,
G_SPLAT_VECTOR,
G_STEP_VECTOR,
G_VECTOR_COMPRESS,
G_CTTZ,
G_CTTZ_ZERO_UNDEF,
G_CTLZ,
G_CTLZ_ZERO_UNDEF,
G_CTPOP,
G_BSWAP,
G_BITREVERSE,
G_FCEIL,
G_FCOS,
G_FSIN,
G_FSINCOS,
G_FTAN,
G_FACOS,
G_FASIN,
G_FATAN,
G_FATAN2,
G_FCOSH,
G_FSINH,
G_FTANH,
G_FSQRT,
G_FFLOOR,
G_FRINT,
G_FNEARBYINT,
G_ADDRSPACE_CAST,
G_BLOCK_ADDR,
G_JUMP_TABLE,
G_DYN_STACKALLOC,
G_STACKSAVE,
G_STACKRESTORE,
G_STRICT_FADD,
G_STRICT_FSUB,
G_STRICT_FMUL,
G_STRICT_FDIV,
G_STRICT_FREM,
G_STRICT_FMA,
G_STRICT_FSQRT,
G_STRICT_FLDEXP,
G_READ_REGISTER,
G_WRITE_REGISTER,
G_MEMCPY,
G_MEMCPY_INLINE,
G_MEMMOVE,
G_MEMSET,
G_BZERO,
G_TRAP,
G_DEBUGTRAP,
G_UBSANTRAP,
G_VECREDUCE_SEQ_FADD,
G_VECREDUCE_SEQ_FMUL,
G_VECREDUCE_FADD,
G_VECREDUCE_FMUL,
G_VECREDUCE_FMAX,
G_VECREDUCE_FMIN,
G_VECREDUCE_FMAXIMUM,
G_VECREDUCE_FMINIMUM,
G_VECREDUCE_ADD,
G_VECREDUCE_MUL,
G_VECREDUCE_AND,
G_VECREDUCE_OR,
G_VECREDUCE_XOR,
G_VECREDUCE_SMAX,
G_VECREDUCE_SMIN,
G_VECREDUCE_UMAX,
G_VECREDUCE_UMIN,
G_SBFX,
G_UBFX,
ADDSri,
ADDSrr,
ADDSrsi,
ADDSrsr,
ADJCALLSTACKDOWN,
ADJCALLSTACKUP,
ASRi,
ASRr,
ASRs1,
B,
BCCZi64,
BCCi64,
BLX_noip,
BLX_pred_noip,
BL_PUSHLR,
BMOVPCB_CALL,
BMOVPCRX_CALL,
BR_JTadd,
BR_JTm_i12,
BR_JTm_rs,
BR_JTr,
BX_CALL,
CMP_SWAP_16,
CMP_SWAP_32,
CMP_SWAP_64,
CMP_SWAP_8,
CONSTPOOL_ENTRY,
COPY_STRUCT_BYVAL_I32,
ITasm,
Int_eh_sjlj_dispatchsetup,
Int_eh_sjlj_longjmp,
Int_eh_sjlj_setjmp,
Int_eh_sjlj_setjmp_nofp,
Int_eh_sjlj_setup_dispatch,
JUMPTABLE_ADDRS,
JUMPTABLE_INSTS,
JUMPTABLE_TBB,
JUMPTABLE_TBH,
KCFI_CHECK_ARM,
KCFI_CHECK_Thumb1,
KCFI_CHECK_Thumb2,
LDMIA_RET,
LDRBT_POST,
LDRConstPool,
LDRHTii,
LDRLIT_ga_abs,
LDRLIT_ga_pcrel,
LDRLIT_ga_pcrel_ldr,
LDRSBTii,
LDRSHTii,
LDRT_POST,
LEApcrel,
LEApcrelJT,
LOADDUAL,
LSLi,
LSLr,
LSRi,
LSRr,
LSRs1,
MEMCPY,
MLAv5,
MOVCCi,
MOVCCi16,
MOVCCi32imm,
MOVCCr,
MOVCCsi,
MOVCCsr,
MOVPCRX,
MOVTi16_ga_pcrel,
MOV_ga_pcrel,
MOV_ga_pcrel_ldr,
MOVi16_ga_pcrel,
MOVi32imm,
MQPRCopy,
MQQPRLoad,
MQQPRStore,
MQQQQPRLoad,
MQQQQPRStore,
MULv5,
MVE_MEMCPYLOOPINST,
MVE_MEMSETLOOPINST,
MVNCCi,
PICADD,
PICLDR,
PICLDRB,
PICLDRH,
PICLDRSB,
PICLDRSH,
PICSTR,
PICSTRB,
PICSTRH,
RORi,
RORr,
RRX,
RRXi,
RSBSri,
RSBSrsi,
RSBSrsr,
SEH_EpilogEnd,
SEH_EpilogStart,
SEH_Nop,
SEH_Nop_Ret,
SEH_PrologEnd,
SEH_SaveFRegs,
SEH_SaveLR,
SEH_SaveRegs,
SEH_SaveRegs_Ret,
SEH_SaveSP,
SEH_StackAlloc,
SMLALv5,
SMULLv5,
SPACE,
STOREDUAL,
STRBT_POST,
STRBi_preidx,
STRBr_preidx,
STRH_preidx,
STRT_POST,
STRi_preidx,
STRr_preidx,
SUBS_PC_LR,
SUBSri,
SUBSrr,
SUBSrsi,
SUBSrsr,
SpeculationBarrierISBDSBEndBB,
SpeculationBarrierSBEndBB,
TAILJMPd,
TAILJMPr,
TAILJMPr4,
TCRETURNdi,
TCRETURNri,
TCRETURNrinotr12,
TPsoft,
UMLALv5,
UMULLv5,
VLD1LNdAsm_16,
VLD1LNdAsm_32,
VLD1LNdAsm_8,
VLD1LNdWB_fixed_Asm_16,
VLD1LNdWB_fixed_Asm_32,
VLD1LNdWB_fixed_Asm_8,
VLD1LNdWB_register_Asm_16,
VLD1LNdWB_register_Asm_32,
VLD1LNdWB_register_Asm_8,
VLD2LNdAsm_16,
VLD2LNdAsm_32,
VLD2LNdAsm_8,
VLD2LNdWB_fixed_Asm_16,
VLD2LNdWB_fixed_Asm_32,
VLD2LNdWB_fixed_Asm_8,
VLD2LNdWB_register_Asm_16,
VLD2LNdWB_register_Asm_32,
VLD2LNdWB_register_Asm_8,
VLD2LNqAsm_16,
VLD2LNqAsm_32,
VLD2LNqWB_fixed_Asm_16,
VLD2LNqWB_fixed_Asm_32,
VLD2LNqWB_register_Asm_16,
VLD2LNqWB_register_Asm_32,
VLD3DUPdAsm_16,
VLD3DUPdAsm_32,
VLD3DUPdAsm_8,
VLD3DUPdWB_fixed_Asm_16,
VLD3DUPdWB_fixed_Asm_32,
VLD3DUPdWB_fixed_Asm_8,
VLD3DUPdWB_register_Asm_16,
VLD3DUPdWB_register_Asm_32,
VLD3DUPdWB_register_Asm_8,
VLD3DUPqAsm_16,
VLD3DUPqAsm_32,
VLD3DUPqAsm_8,
VLD3DUPqWB_fixed_Asm_16,
VLD3DUPqWB_fixed_Asm_32,
VLD3DUPqWB_fixed_Asm_8,
VLD3DUPqWB_register_Asm_16,
VLD3DUPqWB_register_Asm_32,
VLD3DUPqWB_register_Asm_8,
VLD3LNdAsm_16,
VLD3LNdAsm_32,
VLD3LNdAsm_8,
VLD3LNdWB_fixed_Asm_16,
VLD3LNdWB_fixed_Asm_32,
VLD3LNdWB_fixed_Asm_8,
VLD3LNdWB_register_Asm_16,
VLD3LNdWB_register_Asm_32,
VLD3LNdWB_register_Asm_8,
VLD3LNqAsm_16,
VLD3LNqAsm_32,
VLD3LNqWB_fixed_Asm_16,
VLD3LNqWB_fixed_Asm_32,
VLD3LNqWB_register_Asm_16,
VLD3LNqWB_register_Asm_32,
VLD3dAsm_16,
VLD3dAsm_32,
VLD3dAsm_8,
VLD3dWB_fixed_Asm_16,
VLD3dWB_fixed_Asm_32,
VLD3dWB_fixed_Asm_8,
VLD3dWB_register_Asm_16,
VLD3dWB_register_Asm_32,
VLD3dWB_register_Asm_8,
VLD3qAsm_16,
VLD3qAsm_32,
VLD3qAsm_8,
VLD3qWB_fixed_Asm_16,
VLD3qWB_fixed_Asm_32,
VLD3qWB_fixed_Asm_8,
VLD3qWB_register_Asm_16,
VLD3qWB_register_Asm_32,
VLD3qWB_register_Asm_8,
VLD4DUPdAsm_16,
VLD4DUPdAsm_32,
VLD4DUPdAsm_8,
VLD4DUPdWB_fixed_Asm_16,
VLD4DUPdWB_fixed_Asm_32,
VLD4DUPdWB_fixed_Asm_8,
VLD4DUPdWB_register_Asm_16,
VLD4DUPdWB_register_Asm_32,
VLD4DUPdWB_register_Asm_8,
VLD4DUPqAsm_16,
VLD4DUPqAsm_32,
VLD4DUPqAsm_8,
VLD4DUPqWB_fixed_Asm_16,
VLD4DUPqWB_fixed_Asm_32,
VLD4DUPqWB_fixed_Asm_8,
VLD4DUPqWB_register_Asm_16,
VLD4DUPqWB_register_Asm_32,
VLD4DUPqWB_register_Asm_8,
VLD4LNdAsm_16,
VLD4LNdAsm_32,
VLD4LNdAsm_8,
VLD4LNdWB_fixed_Asm_16,
VLD4LNdWB_fixed_Asm_32,
VLD4LNdWB_fixed_Asm_8,
VLD4LNdWB_register_Asm_16,
VLD4LNdWB_register_Asm_32,
VLD4LNdWB_register_Asm_8,
VLD4LNqAsm_16,
VLD4LNqAsm_32,
VLD4LNqWB_fixed_Asm_16,
VLD4LNqWB_fixed_Asm_32,
VLD4LNqWB_register_Asm_16,
VLD4LNqWB_register_Asm_32,
VLD4dAsm_16,
VLD4dAsm_32,
VLD4dAsm_8,
VLD4dWB_fixed_Asm_16,
VLD4dWB_fixed_Asm_32,
VLD4dWB_fixed_Asm_8,
VLD4dWB_register_Asm_16,
VLD4dWB_register_Asm_32,
VLD4dWB_register_Asm_8,
VLD4qAsm_16,
VLD4qAsm_32,
VLD4qAsm_8,
VLD4qWB_fixed_Asm_16,
VLD4qWB_fixed_Asm_32,
VLD4qWB_fixed_Asm_8,
VLD4qWB_register_Asm_16,
VLD4qWB_register_Asm_32,
VLD4qWB_register_Asm_8,
VMOVD0,
VMOVDcc,
VMOVHcc,
VMOVQ0,
VMOVScc,
VST1LNdAsm_16,
VST1LNdAsm_32,
VST1LNdAsm_8,
VST1LNdWB_fixed_Asm_16,
VST1LNdWB_fixed_Asm_32,
VST1LNdWB_fixed_Asm_8,
VST1LNdWB_register_Asm_16,
VST1LNdWB_register_Asm_32,
VST1LNdWB_register_Asm_8,
VST2LNdAsm_16,
VST2LNdAsm_32,
VST2LNdAsm_8,
VST2LNdWB_fixed_Asm_16,
VST2LNdWB_fixed_Asm_32,
VST2LNdWB_fixed_Asm_8,
VST2LNdWB_register_Asm_16,
VST2LNdWB_register_Asm_32,
VST2LNdWB_register_Asm_8,
VST2LNqAsm_16,
VST2LNqAsm_32,
VST2LNqWB_fixed_Asm_16,
VST2LNqWB_fixed_Asm_32,
VST2LNqWB_register_Asm_16,
VST2LNqWB_register_Asm_32,
VST3LNdAsm_16,
VST3LNdAsm_32,
VST3LNdAsm_8,
VST3LNdWB_fixed_Asm_16,
VST3LNdWB_fixed_Asm_32,
VST3LNdWB_fixed_Asm_8,
VST3LNdWB_register_Asm_16,
VST3LNdWB_register_Asm_32,
VST3LNdWB_register_Asm_8,
VST3LNqAsm_16,
VST3LNqAsm_32,
VST3LNqWB_fixed_Asm_16,
VST3LNqWB_fixed_Asm_32,
VST3LNqWB_register_Asm_16,
VST3LNqWB_register_Asm_32,
VST3dAsm_16,
VST3dAsm_32,
VST3dAsm_8,
VST3dWB_fixed_Asm_16,
VST3dWB_fixed_Asm_32,
VST3dWB_fixed_Asm_8,
VST3dWB_register_Asm_16,
VST3dWB_register_Asm_32,
VST3dWB_register_Asm_8,
VST3qAsm_16,
VST3qAsm_32,
VST3qAsm_8,
VST3qWB_fixed_Asm_16,
VST3qWB_fixed_Asm_32,
VST3qWB_fixed_Asm_8,
VST3qWB_register_Asm_16,
VST3qWB_register_Asm_32,
VST3qWB_register_Asm_8,
VST4LNdAsm_16,
VST4LNdAsm_32,
VST4LNdAsm_8,
VST4LNdWB_fixed_Asm_16,
VST4LNdWB_fixed_Asm_32,
VST4LNdWB_fixed_Asm_8,
VST4LNdWB_register_Asm_16,
VST4LNdWB_register_Asm_32,
VST4LNdWB_register_Asm_8,
VST4LNqAsm_16,
VST4LNqAsm_32,
VST4LNqWB_fixed_Asm_16,
VST4LNqWB_fixed_Asm_32,
VST4LNqWB_register_Asm_16,
VST4LNqWB_register_Asm_32,
VST4dAsm_16,
VST4dAsm_32,
VST4dAsm_8,
VST4dWB_fixed_Asm_16,
VST4dWB_fixed_Asm_32,
VST4dWB_fixed_Asm_8,
VST4dWB_register_Asm_16,
VST4dWB_register_Asm_32,
VST4dWB_register_Asm_8,
VST4qAsm_16,
VST4qAsm_32,
VST4qAsm_8,
VST4qWB_fixed_Asm_16,
VST4qWB_fixed_Asm_32,
VST4qWB_fixed_Asm_8,
VST4qWB_register_Asm_16,
VST4qWB_register_Asm_32,
VST4qWB_register_Asm_8,
WIN__CHKSTK,
WIN__DBZCHK,
t2ADDSri,
t2ADDSrr,
t2ADDSrs,
t2BF_LabelPseudo,
t2BR_JT,
t2CALL_BTI,
t2DoLoopStart,
t2DoLoopStartTP,
t2LDMIA_RET,
t2LDRB_OFFSET_imm,
t2LDRB_POST_imm,
t2LDRB_PRE_imm,
t2LDRBpcrel,
t2LDRConstPool,
t2LDRH_OFFSET_imm,
t2LDRH_POST_imm,
t2LDRH_PRE_imm,
t2LDRHpcrel,
t2LDRLIT_ga_pcrel,
t2LDRSB_OFFSET_imm,
t2LDRSB_POST_imm,
t2LDRSB_PRE_imm,
t2LDRSBpcrel,
t2LDRSH_OFFSET_imm,
t2LDRSH_POST_imm,
t2LDRSH_PRE_imm,
t2LDRSHpcrel,
t2LDR_POST_imm,
t2LDR_PRE_imm,
t2LDRpci_pic,
t2LDRpcrel,
t2LEApcrel,
t2LEApcrelJT,
t2LoopDec,
t2LoopEnd,
t2LoopEndDec,
t2MOVCCasr,
t2MOVCCi,
t2MOVCCi16,
t2MOVCCi32imm,
t2MOVCClsl,
t2MOVCClsr,
t2MOVCCr,
t2MOVCCror,
t2MOVSsi,
t2MOVSsr,
t2MOVTi16_ga_pcrel,
t2MOV_ga_pcrel,
t2MOVi16_ga_pcrel,
t2MOVi32imm,
t2MOVsi,
t2MOVsr,
t2MVNCCi,
t2RSBSri,
t2RSBSrs,
t2STRB_OFFSET_imm,
t2STRB_POST_imm,
t2STRB_PRE_imm,
t2STRB_preidx,
t2STRH_OFFSET_imm,
t2STRH_POST_imm,
t2STRH_PRE_imm,
t2STRH_preidx,
t2STR_POST_imm,
t2STR_PRE_imm,
t2STR_preidx,
t2SUBSri,
t2SUBSrr,
t2SUBSrs,
t2SpeculationBarrierISBDSBEndBB,
t2SpeculationBarrierSBEndBB,
t2TBB_JT,
t2TBH_JT,
t2WhileLoopSetup,
t2WhileLoopStart,
t2WhileLoopStartLR,
t2WhileLoopStartTP,
tADCS,
tADDSi3,
tADDSi8,
tADDSrr,
tADDframe,
tADJCALLSTACKDOWN,
tADJCALLSTACKUP,
tBLXNS_CALL,
tBLXr_noip,
tBL_PUSHLR,
tBRIND,
tBR_JTr,
tBXNS_RET,
tBX_CALL,
tBX_RET,
tBX_RET_vararg,
tBfar,
tCMP_SWAP_16,
tCMP_SWAP_32,
tCMP_SWAP_8,
tLDMIA_UPD,
tLDRConstPool,
tLDRLIT_ga_abs,
tLDRLIT_ga_pcrel,
tLDR_postidx,
tLDRpci_pic,
tLEApcrel,
tLEApcrelJT,
tLSLSri,
tMOVCCr_pseudo,
tMOVi32imm,
tPOP_RET,
tRSBS,
tSBCS,
tSUBSi3,
tSUBSi8,
tSUBSrr,
tTAILJMPd,
tTAILJMPdND,
tTAILJMPr,
tTBB_JT,
tTBH_JT,
tTPsoft,
ADCri,
ADCrr,
ADCrsi,
ADCrsr,
ADDri,
ADDrr,
ADDrsi,
ADDrsr,
ADR,
AESD,
AESE,
AESIMC,
AESMC,
ANDri,
ANDrr,
ANDrsi,
ANDrsr,
BF16VDOTI_VDOTD,
BF16VDOTI_VDOTQ,
BF16VDOTS_VDOTD,
BF16VDOTS_VDOTQ,
BF16_VCVT,
BF16_VCVTB,
BF16_VCVTT,
BFC,
BFI,
BICri,
BICrr,
BICrsi,
BICrsr,
BKPT,
BL,
BLX,
BLX_pred,
BLXi,
BL_pred,
BX,
BXJ,
BX_RET,
BX_pred,
Bcc,
CDE_CX1,
CDE_CX1A,
CDE_CX1D,
CDE_CX1DA,
CDE_CX2,
CDE_CX2A,
CDE_CX2D,
CDE_CX2DA,
CDE_CX3,
CDE_CX3A,
CDE_CX3D,
CDE_CX3DA,
CDE_VCX1A_fpdp,
CDE_VCX1A_fpsp,
CDE_VCX1A_vec,
CDE_VCX1_fpdp,
CDE_VCX1_fpsp,
CDE_VCX1_vec,
CDE_VCX2A_fpdp,
CDE_VCX2A_fpsp,
CDE_VCX2A_vec,
CDE_VCX2_fpdp,
CDE_VCX2_fpsp,
CDE_VCX2_vec,
CDE_VCX3A_fpdp,
CDE_VCX3A_fpsp,
CDE_VCX3A_vec,
CDE_VCX3_fpdp,
CDE_VCX3_fpsp,
CDE_VCX3_vec,
CDP,
CDP2,
CLREX,
CLZ,
CMNri,
CMNzrr,
CMNzrsi,
CMNzrsr,
CMPri,
CMPrr,
CMPrsi,
CMPrsr,
CPS1p,
CPS2p,
CPS3p,
CRC32B,
CRC32CB,
CRC32CH,
CRC32CW,
CRC32H,
CRC32W,
DBG,
DMB,
DSB,
EORri,
EORrr,
EORrsi,
EORrsr,
ERET,
FCONSTD,
FCONSTH,
FCONSTS,
FLDMXDB_UPD,
FLDMXIA,
FLDMXIA_UPD,
FMSTAT,
FSTMXDB_UPD,
FSTMXIA,
FSTMXIA_UPD,
HINT,
HLT,
HVC,
ISB,
LDA,
LDAB,
LDAEX,
LDAEXB,
LDAEXD,
LDAEXH,
LDAH,
LDC2L_OFFSET,
LDC2L_OPTION,
LDC2L_POST,
LDC2L_PRE,
LDC2_OFFSET,
LDC2_OPTION,
LDC2_POST,
LDC2_PRE,
LDCL_OFFSET,
LDCL_OPTION,
LDCL_POST,
LDCL_PRE,
LDC_OFFSET,
LDC_OPTION,
LDC_POST,
LDC_PRE,
LDMDA,
LDMDA_UPD,
LDMDB,
LDMDB_UPD,
LDMIA,
LDMIA_UPD,
LDMIB,
LDMIB_UPD,
LDRBT_POST_IMM,
LDRBT_POST_REG,
LDRB_POST_IMM,
LDRB_POST_REG,
LDRB_PRE_IMM,
LDRB_PRE_REG,
LDRBi12,
LDRBrs,
LDRD,
LDRD_POST,
LDRD_PRE,
LDREX,
LDREXB,
LDREXD,
LDREXH,
LDRH,
LDRHTi,
LDRHTr,
LDRH_POST,
LDRH_PRE,
LDRSB,
LDRSBTi,
LDRSBTr,
LDRSB_POST,
LDRSB_PRE,
LDRSH,
LDRSHTi,
LDRSHTr,
LDRSH_POST,
LDRSH_PRE,
LDRT_POST_IMM,
LDRT_POST_REG,
LDR_POST_IMM,
LDR_POST_REG,
LDR_PRE_IMM,
LDR_PRE_REG,
LDRcp,
LDRi12,
LDRrs,
MCR,
MCR2,
MCRR,
MCRR2,
MLA,
MLS,
MOVPCLR,
MOVTi16,
MOVi,
MOVi16,
MOVr,
MOVr_TC,
MOVsi,
MOVsr,
MRC,
MRC2,
MRRC,
MRRC2,
MRS,
MRSbanked,
MRSsys,
MSR,
MSRbanked,
MSRi,
MUL,
MVE_ASRLi,
MVE_ASRLr,
MVE_DLSTP_16,
MVE_DLSTP_32,
MVE_DLSTP_64,
MVE_DLSTP_8,
MVE_LCTP,
MVE_LETP,
MVE_LSLLi,
MVE_LSLLr,
MVE_LSRL,
MVE_SQRSHR,
MVE_SQRSHRL,
MVE_SQSHL,
MVE_SQSHLL,
MVE_SRSHR,
MVE_SRSHRL,
MVE_UQRSHL,
MVE_UQRSHLL,
MVE_UQSHL,
MVE_UQSHLL,
MVE_URSHR,
MVE_URSHRL,
MVE_VABAVs16,
MVE_VABAVs32,
MVE_VABAVs8,
MVE_VABAVu16,
MVE_VABAVu32,
MVE_VABAVu8,
MVE_VABDf16,
MVE_VABDf32,
MVE_VABDs16,
MVE_VABDs32,
MVE_VABDs8,
MVE_VABDu16,
MVE_VABDu32,
MVE_VABDu8,
MVE_VABSf16,
MVE_VABSf32,
MVE_VABSs16,
MVE_VABSs32,
MVE_VABSs8,
MVE_VADC,
MVE_VADCI,
MVE_VADDLVs32acc,
MVE_VADDLVs32no_acc,
MVE_VADDLVu32acc,
MVE_VADDLVu32no_acc,
MVE_VADDVs16acc,
MVE_VADDVs16no_acc,
MVE_VADDVs32acc,
MVE_VADDVs32no_acc,
MVE_VADDVs8acc,
MVE_VADDVs8no_acc,
MVE_VADDVu16acc,
MVE_VADDVu16no_acc,
MVE_VADDVu32acc,
MVE_VADDVu32no_acc,
MVE_VADDVu8acc,
MVE_VADDVu8no_acc,
MVE_VADD_qr_f16,
MVE_VADD_qr_f32,
MVE_VADD_qr_i16,
MVE_VADD_qr_i32,
MVE_VADD_qr_i8,
MVE_VADDf16,
MVE_VADDf32,
MVE_VADDi16,
MVE_VADDi32,
MVE_VADDi8,
MVE_VAND,
MVE_VBIC,
MVE_VBICimmi16,
MVE_VBICimmi32,
MVE_VBRSR16,
MVE_VBRSR32,
MVE_VBRSR8,
MVE_VCADDf16,
MVE_VCADDf32,
MVE_VCADDi16,
MVE_VCADDi32,
MVE_VCADDi8,
MVE_VCLSs16,
MVE_VCLSs32,
MVE_VCLSs8,
MVE_VCLZs16,
MVE_VCLZs32,
MVE_VCLZs8,
MVE_VCMLAf16,
MVE_VCMLAf32,
MVE_VCMPf16,
MVE_VCMPf16r,
MVE_VCMPf32,
MVE_VCMPf32r,
MVE_VCMPi16,
MVE_VCMPi16r,
MVE_VCMPi32,
MVE_VCMPi32r,
MVE_VCMPi8,
MVE_VCMPi8r,
MVE_VCMPs16,
MVE_VCMPs16r,
MVE_VCMPs32,
MVE_VCMPs32r,
MVE_VCMPs8,
MVE_VCMPs8r,
MVE_VCMPu16,
MVE_VCMPu16r,
MVE_VCMPu32,
MVE_VCMPu32r,
MVE_VCMPu8,
MVE_VCMPu8r,
MVE_VCMULf16,
MVE_VCMULf32,
MVE_VCTP16,
MVE_VCTP32,
MVE_VCTP64,
MVE_VCTP8,
MVE_VCVTf16f32bh,
MVE_VCVTf16f32th,
MVE_VCVTf16s16_fix,
MVE_VCVTf16s16n,
MVE_VCVTf16u16_fix,
MVE_VCVTf16u16n,
MVE_VCVTf32f16bh,
MVE_VCVTf32f16th,
MVE_VCVTf32s32_fix,
MVE_VCVTf32s32n,
MVE_VCVTf32u32_fix,
MVE_VCVTf32u32n,
MVE_VCVTs16f16_fix,
MVE_VCVTs16f16a,
MVE_VCVTs16f16m,
MVE_VCVTs16f16n,
MVE_VCVTs16f16p,
MVE_VCVTs16f16z,
MVE_VCVTs32f32_fix,
MVE_VCVTs32f32a,
MVE_VCVTs32f32m,
MVE_VCVTs32f32n,
MVE_VCVTs32f32p,
MVE_VCVTs32f32z,
MVE_VCVTu16f16_fix,
MVE_VCVTu16f16a,
MVE_VCVTu16f16m,
MVE_VCVTu16f16n,
MVE_VCVTu16f16p,
MVE_VCVTu16f16z,
MVE_VCVTu32f32_fix,
MVE_VCVTu32f32a,
MVE_VCVTu32f32m,
MVE_VCVTu32f32n,
MVE_VCVTu32f32p,
MVE_VCVTu32f32z,
MVE_VDDUPu16,
MVE_VDDUPu32,
MVE_VDDUPu8,
MVE_VDUP16,
MVE_VDUP32,
MVE_VDUP8,
MVE_VDWDUPu16,
MVE_VDWDUPu32,
MVE_VDWDUPu8,
MVE_VEOR,
MVE_VFMA_qr_Sf16,
MVE_VFMA_qr_Sf32,
MVE_VFMA_qr_f16,
MVE_VFMA_qr_f32,
MVE_VFMAf16,
MVE_VFMAf32,
MVE_VFMSf16,
MVE_VFMSf32,
MVE_VHADD_qr_s16,
MVE_VHADD_qr_s32,
MVE_VHADD_qr_s8,
MVE_VHADD_qr_u16,
MVE_VHADD_qr_u32,
MVE_VHADD_qr_u8,
MVE_VHADDs16,
MVE_VHADDs32,
MVE_VHADDs8,
MVE_VHADDu16,
MVE_VHADDu32,
MVE_VHADDu8,
MVE_VHCADDs16,
MVE_VHCADDs32,
MVE_VHCADDs8,
MVE_VHSUB_qr_s16,
MVE_VHSUB_qr_s32,
MVE_VHSUB_qr_s8,
MVE_VHSUB_qr_u16,
MVE_VHSUB_qr_u32,
MVE_VHSUB_qr_u8,
MVE_VHSUBs16,
MVE_VHSUBs32,
MVE_VHSUBs8,
MVE_VHSUBu16,
MVE_VHSUBu32,
MVE_VHSUBu8,
MVE_VIDUPu16,
MVE_VIDUPu32,
MVE_VIDUPu8,
MVE_VIWDUPu16,
MVE_VIWDUPu32,
MVE_VIWDUPu8,
MVE_VLD20_16,
MVE_VLD20_16_wb,
MVE_VLD20_32,
MVE_VLD20_32_wb,
MVE_VLD20_8,
MVE_VLD20_8_wb,
MVE_VLD21_16,
MVE_VLD21_16_wb,
MVE_VLD21_32,
MVE_VLD21_32_wb,
MVE_VLD21_8,
MVE_VLD21_8_wb,
MVE_VLD40_16,
MVE_VLD40_16_wb,
MVE_VLD40_32,
MVE_VLD40_32_wb,
MVE_VLD40_8,
MVE_VLD40_8_wb,
MVE_VLD41_16,
MVE_VLD41_16_wb,
MVE_VLD41_32,
MVE_VLD41_32_wb,
MVE_VLD41_8,
MVE_VLD41_8_wb,
MVE_VLD42_16,
MVE_VLD42_16_wb,
MVE_VLD42_32,
MVE_VLD42_32_wb,
MVE_VLD42_8,
MVE_VLD42_8_wb,
MVE_VLD43_16,
MVE_VLD43_16_wb,
MVE_VLD43_32,
MVE_VLD43_32_wb,
MVE_VLD43_8,
MVE_VLD43_8_wb,
MVE_VLDRBS16,
MVE_VLDRBS16_post,
MVE_VLDRBS16_pre,
MVE_VLDRBS16_rq,
MVE_VLDRBS32,
MVE_VLDRBS32_post,
MVE_VLDRBS32_pre,
MVE_VLDRBS32_rq,
MVE_VLDRBU16,
MVE_VLDRBU16_post,
MVE_VLDRBU16_pre,
MVE_VLDRBU16_rq,
MVE_VLDRBU32,
MVE_VLDRBU32_post,
MVE_VLDRBU32_pre,
MVE_VLDRBU32_rq,
MVE_VLDRBU8,
MVE_VLDRBU8_post,
MVE_VLDRBU8_pre,
MVE_VLDRBU8_rq,
MVE_VLDRDU64_qi,
MVE_VLDRDU64_qi_pre,
MVE_VLDRDU64_rq,
MVE_VLDRDU64_rq_u,
MVE_VLDRHS32,
MVE_VLDRHS32_post,
MVE_VLDRHS32_pre,
MVE_VLDRHS32_rq,
MVE_VLDRHS32_rq_u,
MVE_VLDRHU16,
MVE_VLDRHU16_post,
MVE_VLDRHU16_pre,
MVE_VLDRHU16_rq,
MVE_VLDRHU16_rq_u,
MVE_VLDRHU32,
MVE_VLDRHU32_post,
MVE_VLDRHU32_pre,
MVE_VLDRHU32_rq,
MVE_VLDRHU32_rq_u,
MVE_VLDRWU32,
MVE_VLDRWU32_post,
MVE_VLDRWU32_pre,
MVE_VLDRWU32_qi,
MVE_VLDRWU32_qi_pre,
MVE_VLDRWU32_rq,
MVE_VLDRWU32_rq_u,
MVE_VMAXAVs16,
MVE_VMAXAVs32,
MVE_VMAXAVs8,
MVE_VMAXAs16,
MVE_VMAXAs32,
MVE_VMAXAs8,
MVE_VMAXNMAVf16,
MVE_VMAXNMAVf32,
MVE_VMAXNMAf16,
MVE_VMAXNMAf32,
MVE_VMAXNMVf16,
MVE_VMAXNMVf32,
MVE_VMAXNMf16,
MVE_VMAXNMf32,
MVE_VMAXVs16,
MVE_VMAXVs32,
MVE_VMAXVs8,
MVE_VMAXVu16,
MVE_VMAXVu32,
MVE_VMAXVu8,
MVE_VMAXs16,
MVE_VMAXs32,
MVE_VMAXs8,
MVE_VMAXu16,
MVE_VMAXu32,
MVE_VMAXu8,
MVE_VMINAVs16,
MVE_VMINAVs32,
MVE_VMINAVs8,
MVE_VMINAs16,
MVE_VMINAs32,
MVE_VMINAs8,
MVE_VMINNMAVf16,
MVE_VMINNMAVf32,
MVE_VMINNMAf16,
MVE_VMINNMAf32,
MVE_VMINNMVf16,
MVE_VMINNMVf32,
MVE_VMINNMf16,
MVE_VMINNMf32,
MVE_VMINVs16,
MVE_VMINVs32,
MVE_VMINVs8,
MVE_VMINVu16,
MVE_VMINVu32,
MVE_VMINVu8,
MVE_VMINs16,
MVE_VMINs32,
MVE_VMINs8,
MVE_VMINu16,
MVE_VMINu32,
MVE_VMINu8,
MVE_VMLADAVas16,
MVE_VMLADAVas32,
MVE_VMLADAVas8,
MVE_VMLADAVau16,
MVE_VMLADAVau32,
MVE_VMLADAVau8,
MVE_VMLADAVaxs16,
MVE_VMLADAVaxs32,
MVE_VMLADAVaxs8,
MVE_VMLADAVs16,
MVE_VMLADAVs32,
MVE_VMLADAVs8,
MVE_VMLADAVu16,
MVE_VMLADAVu32,
MVE_VMLADAVu8,
MVE_VMLADAVxs16,
MVE_VMLADAVxs32,
MVE_VMLADAVxs8,
MVE_VMLALDAVas16,
MVE_VMLALDAVas32,
MVE_VMLALDAVau16,
MVE_VMLALDAVau32,
MVE_VMLALDAVaxs16,
MVE_VMLALDAVaxs32,
MVE_VMLALDAVs16,
MVE_VMLALDAVs32,
MVE_VMLALDAVu16,
MVE_VMLALDAVu32,
MVE_VMLALDAVxs16,
MVE_VMLALDAVxs32,
MVE_VMLAS_qr_i16,
MVE_VMLAS_qr_i32,
MVE_VMLAS_qr_i8,
MVE_VMLA_qr_i16,
MVE_VMLA_qr_i32,
MVE_VMLA_qr_i8,
MVE_VMLSDAVas16,
MVE_VMLSDAVas32,
MVE_VMLSDAVas8,
MVE_VMLSDAVaxs16,
MVE_VMLSDAVaxs32,
MVE_VMLSDAVaxs8,
MVE_VMLSDAVs16,
MVE_VMLSDAVs32,
MVE_VMLSDAVs8,
MVE_VMLSDAVxs16,
MVE_VMLSDAVxs32,
MVE_VMLSDAVxs8,
MVE_VMLSLDAVas16,
MVE_VMLSLDAVas32,
MVE_VMLSLDAVaxs16,
MVE_VMLSLDAVaxs32,
MVE_VMLSLDAVs16,
MVE_VMLSLDAVs32,
MVE_VMLSLDAVxs16,
MVE_VMLSLDAVxs32,
MVE_VMOVLs16bh,
MVE_VMOVLs16th,
MVE_VMOVLs8bh,
MVE_VMOVLs8th,
MVE_VMOVLu16bh,
MVE_VMOVLu16th,
MVE_VMOVLu8bh,
MVE_VMOVLu8th,
MVE_VMOVNi16bh,
MVE_VMOVNi16th,
MVE_VMOVNi32bh,
MVE_VMOVNi32th,
MVE_VMOV_from_lane_32,
MVE_VMOV_from_lane_s16,
MVE_VMOV_from_lane_s8,
MVE_VMOV_from_lane_u16,
MVE_VMOV_from_lane_u8,
MVE_VMOV_q_rr,
MVE_VMOV_rr_q,
MVE_VMOV_to_lane_16,
MVE_VMOV_to_lane_32,
MVE_VMOV_to_lane_8,
MVE_VMOVimmf32,
MVE_VMOVimmi16,
MVE_VMOVimmi32,
MVE_VMOVimmi64,
MVE_VMOVimmi8,
MVE_VMULHs16,
MVE_VMULHs32,
MVE_VMULHs8,
MVE_VMULHu16,
MVE_VMULHu32,
MVE_VMULHu8,
MVE_VMULLBp16,
MVE_VMULLBp8,
MVE_VMULLBs16,
MVE_VMULLBs32,
MVE_VMULLBs8,
MVE_VMULLBu16,
MVE_VMULLBu32,
MVE_VMULLBu8,
MVE_VMULLTp16,
MVE_VMULLTp8,
MVE_VMULLTs16,
MVE_VMULLTs32,
MVE_VMULLTs8,
MVE_VMULLTu16,
MVE_VMULLTu32,
MVE_VMULLTu8,
MVE_VMUL_qr_f16,
MVE_VMUL_qr_f32,
MVE_VMUL_qr_i16,
MVE_VMUL_qr_i32,
MVE_VMUL_qr_i8,
MVE_VMULf16,
MVE_VMULf32,
MVE_VMULi16,
MVE_VMULi32,
MVE_VMULi8,
MVE_VMVN,
MVE_VMVNimmi16,
MVE_VMVNimmi32,
MVE_VNEGf16,
MVE_VNEGf32,
MVE_VNEGs16,
MVE_VNEGs32,
MVE_VNEGs8,
MVE_VORN,
MVE_VORR,
MVE_VORRimmi16,
MVE_VORRimmi32,
MVE_VPNOT,
MVE_VPSEL,
MVE_VPST,
MVE_VPTv16i8,
MVE_VPTv16i8r,
MVE_VPTv16s8,
MVE_VPTv16s8r,
MVE_VPTv16u8,
MVE_VPTv16u8r,
MVE_VPTv4f32,
MVE_VPTv4f32r,
MVE_VPTv4i32,
MVE_VPTv4i32r,
MVE_VPTv4s32,
MVE_VPTv4s32r,
MVE_VPTv4u32,
MVE_VPTv4u32r,
MVE_VPTv8f16,
MVE_VPTv8f16r,
MVE_VPTv8i16,
MVE_VPTv8i16r,
MVE_VPTv8s16,
MVE_VPTv8s16r,
MVE_VPTv8u16,
MVE_VPTv8u16r,
MVE_VQABSs16,
MVE_VQABSs32,
MVE_VQABSs8,
MVE_VQADD_qr_s16,
MVE_VQADD_qr_s32,
MVE_VQADD_qr_s8,
MVE_VQADD_qr_u16,
MVE_VQADD_qr_u32,
MVE_VQADD_qr_u8,
MVE_VQADDs16,
MVE_VQADDs32,
MVE_VQADDs8,
MVE_VQADDu16,
MVE_VQADDu32,
MVE_VQADDu8,
MVE_VQDMLADHXs16,
MVE_VQDMLADHXs32,
MVE_VQDMLADHXs8,
MVE_VQDMLADHs16,
MVE_VQDMLADHs32,
MVE_VQDMLADHs8,
MVE_VQDMLAH_qrs16,
MVE_VQDMLAH_qrs32,
MVE_VQDMLAH_qrs8,
MVE_VQDMLASH_qrs16,
MVE_VQDMLASH_qrs32,
MVE_VQDMLASH_qrs8,
MVE_VQDMLSDHXs16,
MVE_VQDMLSDHXs32,
MVE_VQDMLSDHXs8,
MVE_VQDMLSDHs16,
MVE_VQDMLSDHs32,
MVE_VQDMLSDHs8,
MVE_VQDMULH_qr_s16,
MVE_VQDMULH_qr_s32,
MVE_VQDMULH_qr_s8,
MVE_VQDMULHi16,
MVE_VQDMULHi32,
MVE_VQDMULHi8,
MVE_VQDMULL_qr_s16bh,
MVE_VQDMULL_qr_s16th,
MVE_VQDMULL_qr_s32bh,
MVE_VQDMULL_qr_s32th,
MVE_VQDMULLs16bh,
MVE_VQDMULLs16th,
MVE_VQDMULLs32bh,
MVE_VQDMULLs32th,
MVE_VQMOVNs16bh,
MVE_VQMOVNs16th,
MVE_VQMOVNs32bh,
MVE_VQMOVNs32th,
MVE_VQMOVNu16bh,
MVE_VQMOVNu16th,
MVE_VQMOVNu32bh,
MVE_VQMOVNu32th,
MVE_VQMOVUNs16bh,
MVE_VQMOVUNs16th,
MVE_VQMOVUNs32bh,
MVE_VQMOVUNs32th,
MVE_VQNEGs16,
MVE_VQNEGs32,
MVE_VQNEGs8,
MVE_VQRDMLADHXs16,
MVE_VQRDMLADHXs32,
MVE_VQRDMLADHXs8,
MVE_VQRDMLADHs16,
MVE_VQRDMLADHs32,
MVE_VQRDMLADHs8,
MVE_VQRDMLAH_qrs16,
MVE_VQRDMLAH_qrs32,
MVE_VQRDMLAH_qrs8,
MVE_VQRDMLASH_qrs16,
MVE_VQRDMLASH_qrs32,
MVE_VQRDMLASH_qrs8,
MVE_VQRDMLSDHXs16,
MVE_VQRDMLSDHXs32,
MVE_VQRDMLSDHXs8,
MVE_VQRDMLSDHs16,
MVE_VQRDMLSDHs32,
MVE_VQRDMLSDHs8,
MVE_VQRDMULH_qr_s16,
MVE_VQRDMULH_qr_s32,
MVE_VQRDMULH_qr_s8,
MVE_VQRDMULHi16,
MVE_VQRDMULHi32,
MVE_VQRDMULHi8,
MVE_VQRSHL_by_vecs16,
MVE_VQRSHL_by_vecs32,
MVE_VQRSHL_by_vecs8,
MVE_VQRSHL_by_vecu16,
MVE_VQRSHL_by_vecu32,
MVE_VQRSHL_by_vecu8,
MVE_VQRSHL_qrs16,
MVE_VQRSHL_qrs32,
MVE_VQRSHL_qrs8,
MVE_VQRSHL_qru16,
MVE_VQRSHL_qru32,
MVE_VQRSHL_qru8,
MVE_VQRSHRNbhs16,
MVE_VQRSHRNbhs32,
MVE_VQRSHRNbhu16,
MVE_VQRSHRNbhu32,
MVE_VQRSHRNths16,
MVE_VQRSHRNths32,
MVE_VQRSHRNthu16,
MVE_VQRSHRNthu32,
MVE_VQRSHRUNs16bh,
MVE_VQRSHRUNs16th,
MVE_VQRSHRUNs32bh,
MVE_VQRSHRUNs32th,
MVE_VQSHLU_imms16,
MVE_VQSHLU_imms32,
MVE_VQSHLU_imms8,
MVE_VQSHL_by_vecs16,
MVE_VQSHL_by_vecs32,
MVE_VQSHL_by_vecs8,
MVE_VQSHL_by_vecu16,
MVE_VQSHL_by_vecu32,
MVE_VQSHL_by_vecu8,
MVE_VQSHL_qrs16,
MVE_VQSHL_qrs32,
MVE_VQSHL_qrs8,
MVE_VQSHL_qru16,
MVE_VQSHL_qru32,
MVE_VQSHL_qru8,
MVE_VQSHLimms16,
MVE_VQSHLimms32,
MVE_VQSHLimms8,
MVE_VQSHLimmu16,
MVE_VQSHLimmu32,
MVE_VQSHLimmu8,
MVE_VQSHRNbhs16,
MVE_VQSHRNbhs32,
MVE_VQSHRNbhu16,
MVE_VQSHRNbhu32,
MVE_VQSHRNths16,
MVE_VQSHRNths32,
MVE_VQSHRNthu16,
MVE_VQSHRNthu32,
MVE_VQSHRUNs16bh,
MVE_VQSHRUNs16th,
MVE_VQSHRUNs32bh,
MVE_VQSHRUNs32th,
MVE_VQSUB_qr_s16,
MVE_VQSUB_qr_s32,
MVE_VQSUB_qr_s8,
MVE_VQSUB_qr_u16,
MVE_VQSUB_qr_u32,
MVE_VQSUB_qr_u8,
MVE_VQSUBs16,
MVE_VQSUBs32,
MVE_VQSUBs8,
MVE_VQSUBu16,
MVE_VQSUBu32,
MVE_VQSUBu8,
MVE_VREV16_8,
MVE_VREV32_16,
MVE_VREV32_8,
MVE_VREV64_16,
MVE_VREV64_32,
MVE_VREV64_8,
MVE_VRHADDs16,
MVE_VRHADDs32,
MVE_VRHADDs8,
MVE_VRHADDu16,
MVE_VRHADDu32,
MVE_VRHADDu8,
MVE_VRINTf16A,
MVE_VRINTf16M,
MVE_VRINTf16N,
MVE_VRINTf16P,
MVE_VRINTf16X,
MVE_VRINTf16Z,
MVE_VRINTf32A,
MVE_VRINTf32M,
MVE_VRINTf32N,
MVE_VRINTf32P,
MVE_VRINTf32X,
MVE_VRINTf32Z,
MVE_VRMLALDAVHas32,
MVE_VRMLALDAVHau32,
MVE_VRMLALDAVHaxs32,
MVE_VRMLALDAVHs32,
MVE_VRMLALDAVHu32,
MVE_VRMLALDAVHxs32,
MVE_VRMLSLDAVHas32,
MVE_VRMLSLDAVHaxs32,
MVE_VRMLSLDAVHs32,
MVE_VRMLSLDAVHxs32,
MVE_VRMULHs16,
MVE_VRMULHs32,
MVE_VRMULHs8,
MVE_VRMULHu16,
MVE_VRMULHu32,
MVE_VRMULHu8,
MVE_VRSHL_by_vecs16,
MVE_VRSHL_by_vecs32,
MVE_VRSHL_by_vecs8,
MVE_VRSHL_by_vecu16,
MVE_VRSHL_by_vecu32,
MVE_VRSHL_by_vecu8,
MVE_VRSHL_qrs16,
MVE_VRSHL_qrs32,
MVE_VRSHL_qrs8,
MVE_VRSHL_qru16,
MVE_VRSHL_qru32,
MVE_VRSHL_qru8,
MVE_VRSHRNi16bh,
MVE_VRSHRNi16th,
MVE_VRSHRNi32bh,
MVE_VRSHRNi32th,
MVE_VRSHR_imms16,
MVE_VRSHR_imms32,
MVE_VRSHR_imms8,
MVE_VRSHR_immu16,
MVE_VRSHR_immu32,
MVE_VRSHR_immu8,
MVE_VSBC,
MVE_VSBCI,
MVE_VSHLC,
MVE_VSHLL_imms16bh,
MVE_VSHLL_imms16th,
MVE_VSHLL_imms8bh,
MVE_VSHLL_imms8th,
MVE_VSHLL_immu16bh,
MVE_VSHLL_immu16th,
MVE_VSHLL_immu8bh,
MVE_VSHLL_immu8th,
MVE_VSHLL_lws16bh,
MVE_VSHLL_lws16th,
MVE_VSHLL_lws8bh,
MVE_VSHLL_lws8th,
MVE_VSHLL_lwu16bh,
MVE_VSHLL_lwu16th,
MVE_VSHLL_lwu8bh,
MVE_VSHLL_lwu8th,
MVE_VSHL_by_vecs16,
MVE_VSHL_by_vecs32,
MVE_VSHL_by_vecs8,
MVE_VSHL_by_vecu16,
MVE_VSHL_by_vecu32,
MVE_VSHL_by_vecu8,
MVE_VSHL_immi16,
MVE_VSHL_immi32,
MVE_VSHL_immi8,
MVE_VSHL_qrs16,
MVE_VSHL_qrs32,
MVE_VSHL_qrs8,
MVE_VSHL_qru16,
MVE_VSHL_qru32,
MVE_VSHL_qru8,
MVE_VSHRNi16bh,
MVE_VSHRNi16th,
MVE_VSHRNi32bh,
MVE_VSHRNi32th,
MVE_VSHR_imms16,
MVE_VSHR_imms32,
MVE_VSHR_imms8,
MVE_VSHR_immu16,
MVE_VSHR_immu32,
MVE_VSHR_immu8,
MVE_VSLIimm16,
MVE_VSLIimm32,
MVE_VSLIimm8,
MVE_VSRIimm16,
MVE_VSRIimm32,
MVE_VSRIimm8,
MVE_VST20_16,
MVE_VST20_16_wb,
MVE_VST20_32,
MVE_VST20_32_wb,
MVE_VST20_8,
MVE_VST20_8_wb,
MVE_VST21_16,
MVE_VST21_16_wb,
MVE_VST21_32,
MVE_VST21_32_wb,
MVE_VST21_8,
MVE_VST21_8_wb,
MVE_VST40_16,
MVE_VST40_16_wb,
MVE_VST40_32,
MVE_VST40_32_wb,
MVE_VST40_8,
MVE_VST40_8_wb,
MVE_VST41_16,
MVE_VST41_16_wb,
MVE_VST41_32,
MVE_VST41_32_wb,
MVE_VST41_8,
MVE_VST41_8_wb,
MVE_VST42_16,
MVE_VST42_16_wb,
MVE_VST42_32,
MVE_VST42_32_wb,
MVE_VST42_8,
MVE_VST42_8_wb,
MVE_VST43_16,
MVE_VST43_16_wb,
MVE_VST43_32,
MVE_VST43_32_wb,
MVE_VST43_8,
MVE_VST43_8_wb,
MVE_VSTRB16,
MVE_VSTRB16_post,
MVE_VSTRB16_pre,
MVE_VSTRB16_rq,
MVE_VSTRB32,
MVE_VSTRB32_post,
MVE_VSTRB32_pre,
MVE_VSTRB32_rq,
MVE_VSTRB8_rq,
MVE_VSTRBU8,
MVE_VSTRBU8_post,
MVE_VSTRBU8_pre,
MVE_VSTRD64_qi,
MVE_VSTRD64_qi_pre,
MVE_VSTRD64_rq,
MVE_VSTRD64_rq_u,
MVE_VSTRH16_rq,
MVE_VSTRH16_rq_u,
MVE_VSTRH32,
MVE_VSTRH32_post,
MVE_VSTRH32_pre,
MVE_VSTRH32_rq,
MVE_VSTRH32_rq_u,
MVE_VSTRHU16,
MVE_VSTRHU16_post,
MVE_VSTRHU16_pre,
MVE_VSTRW32_qi,
MVE_VSTRW32_qi_pre,
MVE_VSTRW32_rq,
MVE_VSTRW32_rq_u,
MVE_VSTRWU32,
MVE_VSTRWU32_post,
MVE_VSTRWU32_pre,
MVE_VSUB_qr_f16,
MVE_VSUB_qr_f32,
MVE_VSUB_qr_i16,
MVE_VSUB_qr_i32,
MVE_VSUB_qr_i8,
MVE_VSUBf16,
MVE_VSUBf32,
MVE_VSUBi16,
MVE_VSUBi32,
MVE_VSUBi8,
MVE_WLSTP_16,
MVE_WLSTP_32,
MVE_WLSTP_64,
MVE_WLSTP_8,
MVNi,
MVNr,
MVNsi,
MVNsr,
NEON_VMAXNMNDf,
NEON_VMAXNMNDh,
NEON_VMAXNMNQf,
NEON_VMAXNMNQh,
NEON_VMINNMNDf,
NEON_VMINNMNDh,
NEON_VMINNMNQf,
NEON_VMINNMNQh,
ORRri,
ORRrr,
ORRrsi,
ORRrsr,
PKHBT,
PKHTB,
PLDWi12,
PLDWrs,
PLDi12,
PLDrs,
PLIi12,
PLIrs,
QADD,
QADD16,
QADD8,
QASX,
QDADD,
QDSUB,
QSAX,
QSUB,
QSUB16,
QSUB8,
RBIT,
REV,
REV16,
REVSH,
RFEDA,
RFEDA_UPD,
RFEDB,
RFEDB_UPD,
RFEIA,
RFEIA_UPD,
RFEIB,
RFEIB_UPD,
RSBri,
RSBrr,
RSBrsi,
RSBrsr,
RSCri,
RSCrr,
RSCrsi,
RSCrsr,
SADD16,
SADD8,
SASX,
SB,
SBCri,
SBCrr,
SBCrsi,
SBCrsr,
SBFX,
SDIV,
SEL,
SETEND,
SETPAN,
SHA1C,
SHA1H,
SHA1M,
SHA1P,
SHA1SU0,
SHA1SU1,
SHA256H,
SHA256H2,
SHA256SU0,
SHA256SU1,
SHADD16,
SHADD8,
SHASX,
SHSAX,
SHSUB16,
SHSUB8,
SMC,
SMLABB,
SMLABT,
SMLAD,
SMLADX,
SMLAL,
SMLALBB,
SMLALBT,
SMLALD,
SMLALDX,
SMLALTB,
SMLALTT,
SMLATB,
SMLATT,
SMLAWB,
SMLAWT,
SMLSD,
SMLSDX,
SMLSLD,
SMLSLDX,
SMMLA,
SMMLAR,
SMMLS,
SMMLSR,
SMMUL,
SMMULR,
SMUAD,
SMUADX,
SMULBB,
SMULBT,
SMULL,
SMULTB,
SMULTT,
SMULWB,
SMULWT,
SMUSD,
SMUSDX,
SRSDA,
SRSDA_UPD,
SRSDB,
SRSDB_UPD,
SRSIA,
SRSIA_UPD,
SRSIB,
SRSIB_UPD,
SSAT,
SSAT16,
SSAX,
SSUB16,
SSUB8,
STC2L_OFFSET,
STC2L_OPTION,
STC2L_POST,
STC2L_PRE,
STC2_OFFSET,
STC2_OPTION,
STC2_POST,
STC2_PRE,
STCL_OFFSET,
STCL_OPTION,
STCL_POST,
STCL_PRE,
STC_OFFSET,
STC_OPTION,
STC_POST,
STC_PRE,
STL,
STLB,
STLEX,
STLEXB,
STLEXD,
STLEXH,
STLH,
STMDA,
STMDA_UPD,
STMDB,
STMDB_UPD,
STMIA,
STMIA_UPD,
STMIB,
STMIB_UPD,
STRBT_POST_IMM,
STRBT_POST_REG,
STRB_POST_IMM,
STRB_POST_REG,
STRB_PRE_IMM,
STRB_PRE_REG,
STRBi12,
STRBrs,
STRD,
STRD_POST,
STRD_PRE,
STREX,
STREXB,
STREXD,
STREXH,
STRH,
STRHTi,
STRHTr,
STRH_POST,
STRH_PRE,
STRT_POST_IMM,
STRT_POST_REG,
STR_POST_IMM,
STR_POST_REG,
STR_PRE_IMM,
STR_PRE_REG,
STRi12,
STRrs,
SUBri,
SUBrr,
SUBrsi,
SUBrsr,
SVC,
SWP,
SWPB,
SXTAB,
SXTAB16,
SXTAH,
SXTB,
SXTB16,
SXTH,
TEQri,
TEQrr,
TEQrsi,
TEQrsr,
TRAP,
TSB,
TSTri,
TSTrr,
TSTrsi,
TSTrsr,
UADD16,
UADD8,
UASX,
UBFX,
UDF,
UDIV,
UHADD16,
UHADD8,
UHASX,
UHSAX,
UHSUB16,
UHSUB8,
UMAAL,
UMLAL,
UMULL,
UQADD16,
UQADD8,
UQASX,
UQSAX,
UQSUB16,
UQSUB8,
USAD8,
USADA8,
USAT,
USAT16,
USAX,
USUB16,
USUB8,
UXTAB,
UXTAB16,
UXTAH,
UXTB,
UXTB16,
UXTH,
VABALsv2i64,
VABALsv4i32,
VABALsv8i16,
VABALuv2i64,
VABALuv4i32,
VABALuv8i16,
VABAsv16i8,
VABAsv2i32,
VABAsv4i16,
VABAsv4i32,
VABAsv8i16,
VABAsv8i8,
VABAuv16i8,
VABAuv2i32,
VABAuv4i16,
VABAuv4i32,
VABAuv8i16,
VABAuv8i8,
VABDLsv2i64,
VABDLsv4i32,
VABDLsv8i16,
VABDLuv2i64,
VABDLuv4i32,
VABDLuv8i16,
VABDfd,
VABDfq,
VABDhd,
VABDhq,
VABDsv16i8,
VABDsv2i32,
VABDsv4i16,
VABDsv4i32,
VABDsv8i16,
VABDsv8i8,
VABDuv16i8,
VABDuv2i32,
VABDuv4i16,
VABDuv4i32,
VABDuv8i16,
VABDuv8i8,
VABSD,
VABSH,
VABSS,
VABSfd,
VABSfq,
VABShd,
VABShq,
VABSv16i8,
VABSv2i32,
VABSv4i16,
VABSv4i32,
VABSv8i16,
VABSv8i8,
VACGEfd,
VACGEfq,
VACGEhd,
VACGEhq,
VACGTfd,
VACGTfq,
VACGThd,
VACGThq,
VADDD,
VADDH,
VADDHNv2i32,
VADDHNv4i16,
VADDHNv8i8,
VADDLsv2i64,
VADDLsv4i32,
VADDLsv8i16,
VADDLuv2i64,
VADDLuv4i32,
VADDLuv8i16,
VADDS,
VADDWsv2i64,
VADDWsv4i32,
VADDWsv8i16,
VADDWuv2i64,
VADDWuv4i32,
VADDWuv8i16,
VADDfd,
VADDfq,
VADDhd,
VADDhq,
VADDv16i8,
VADDv1i64,
VADDv2i32,
VADDv2i64,
VADDv4i16,
VADDv4i32,
VADDv8i16,
VADDv8i8,
VANDd,
VANDq,
VBF16MALBQ,
VBF16MALBQI,
VBF16MALTQ,
VBF16MALTQI,
VBICd,
VBICiv2i32,
VBICiv4i16,
VBICiv4i32,
VBICiv8i16,
VBICq,
VBIFd,
VBIFq,
VBITd,
VBITq,
VBSLd,
VBSLq,
VBSPd,
VBSPq,
VCADDv2f32,
VCADDv4f16,
VCADDv4f32,
VCADDv8f16,
VCEQfd,
VCEQfq,
VCEQhd,
VCEQhq,
VCEQv16i8,
VCEQv2i32,
VCEQv4i16,
VCEQv4i32,
VCEQv8i16,
VCEQv8i8,
VCEQzv16i8,
VCEQzv2f32,
VCEQzv2i32,
VCEQzv4f16,
VCEQzv4f32,
VCEQzv4i16,
VCEQzv4i32,
VCEQzv8f16,
VCEQzv8i16,
VCEQzv8i8,
VCGEfd,
VCGEfq,
VCGEhd,
VCGEhq,
VCGEsv16i8,
VCGEsv2i32,
VCGEsv4i16,
VCGEsv4i32,
VCGEsv8i16,
VCGEsv8i8,
VCGEuv16i8,
VCGEuv2i32,
VCGEuv4i16,
VCGEuv4i32,
VCGEuv8i16,
VCGEuv8i8,
VCGEzv16i8,
VCGEzv2f32,
VCGEzv2i32,
VCGEzv4f16,
VCGEzv4f32,
VCGEzv4i16,
VCGEzv4i32,
VCGEzv8f16,
VCGEzv8i16,
VCGEzv8i8,
VCGTfd,
VCGTfq,
VCGThd,
VCGThq,
VCGTsv16i8,
VCGTsv2i32,
VCGTsv4i16,
VCGTsv4i32,
VCGTsv8i16,
VCGTsv8i8,
VCGTuv16i8,
VCGTuv2i32,
VCGTuv4i16,
VCGTuv4i32,
VCGTuv8i16,
VCGTuv8i8,
VCGTzv16i8,
VCGTzv2f32,
VCGTzv2i32,
VCGTzv4f16,
VCGTzv4f32,
VCGTzv4i16,
VCGTzv4i32,
VCGTzv8f16,
VCGTzv8i16,
VCGTzv8i8,
VCLEzv16i8,
VCLEzv2f32,
VCLEzv2i32,
VCLEzv4f16,
VCLEzv4f32,
VCLEzv4i16,
VCLEzv4i32,
VCLEzv8f16,
VCLEzv8i16,
VCLEzv8i8,
VCLSv16i8,
VCLSv2i32,
VCLSv4i16,
VCLSv4i32,
VCLSv8i16,
VCLSv8i8,
VCLTzv16i8,
VCLTzv2f32,
VCLTzv2i32,
VCLTzv4f16,
VCLTzv4f32,
VCLTzv4i16,
VCLTzv4i32,
VCLTzv8f16,
VCLTzv8i16,
VCLTzv8i8,
VCLZv16i8,
VCLZv2i32,
VCLZv4i16,
VCLZv4i32,
VCLZv8i16,
VCLZv8i8,
VCMLAv2f32,
VCMLAv2f32_indexed,
VCMLAv4f16,
VCMLAv4f16_indexed,
VCMLAv4f32,
VCMLAv4f32_indexed,
VCMLAv8f16,
VCMLAv8f16_indexed,
VCMPD,
VCMPED,
VCMPEH,
VCMPES,
VCMPEZD,
VCMPEZH,
VCMPEZS,
VCMPH,
VCMPS,
VCMPZD,
VCMPZH,
VCMPZS,
VCNTd,
VCNTq,
VCVTANSDf,
VCVTANSDh,
VCVTANSQf,
VCVTANSQh,
VCVTANUDf,
VCVTANUDh,
VCVTANUQf,
VCVTANUQh,
VCVTASD,
VCVTASH,
VCVTASS,
VCVTAUD,
VCVTAUH,
VCVTAUS,
VCVTBDH,
VCVTBHD,
VCVTBHS,
VCVTBSH,
VCVTDS,
VCVTMNSDf,
VCVTMNSDh,
VCVTMNSQf,
VCVTMNSQh,
VCVTMNUDf,
VCVTMNUDh,
VCVTMNUQf,
VCVTMNUQh,
VCVTMSD,
VCVTMSH,
VCVTMSS,
VCVTMUD,
VCVTMUH,
VCVTMUS,
VCVTNNSDf,
VCVTNNSDh,
VCVTNNSQf,
VCVTNNSQh,
VCVTNNUDf,
VCVTNNUDh,
VCVTNNUQf,
VCVTNNUQh,
VCVTNSD,
VCVTNSH,
VCVTNSS,
VCVTNUD,
VCVTNUH,
VCVTNUS,
VCVTPNSDf,
VCVTPNSDh,
VCVTPNSQf,
VCVTPNSQh,
VCVTPNUDf,
VCVTPNUDh,
VCVTPNUQf,
VCVTPNUQh,
VCVTPSD,
VCVTPSH,
VCVTPSS,
VCVTPUD,
VCVTPUH,
VCVTPUS,
VCVTSD,
VCVTTDH,
VCVTTHD,
VCVTTHS,
VCVTTSH,
VCVTf2h,
VCVTf2sd,
VCVTf2sq,
VCVTf2ud,
VCVTf2uq,
VCVTf2xsd,
VCVTf2xsq,
VCVTf2xud,
VCVTf2xuq,
VCVTh2f,
VCVTh2sd,
VCVTh2sq,
VCVTh2ud,
VCVTh2uq,
VCVTh2xsd,
VCVTh2xsq,
VCVTh2xud,
VCVTh2xuq,
VCVTs2fd,
VCVTs2fq,
VCVTs2hd,
VCVTs2hq,
VCVTu2fd,
VCVTu2fq,
VCVTu2hd,
VCVTu2hq,
VCVTxs2fd,
VCVTxs2fq,
VCVTxs2hd,
VCVTxs2hq,
VCVTxu2fd,
VCVTxu2fq,
VCVTxu2hd,
VCVTxu2hq,
VDIVD,
VDIVH,
VDIVS,
VDUP16d,
VDUP16q,
VDUP32d,
VDUP32q,
VDUP8d,
VDUP8q,
VDUPLN16d,
VDUPLN16q,
VDUPLN32d,
VDUPLN32q,
VDUPLN8d,
VDUPLN8q,
VEORd,
VEORq,
VEXTd16,
VEXTd32,
VEXTd8,
VEXTq16,
VEXTq32,
VEXTq64,
VEXTq8,
VFMAD,
VFMAH,
VFMALD,
VFMALDI,
VFMALQ,
VFMALQI,
VFMAS,
VFMAfd,
VFMAfq,
VFMAhd,
VFMAhq,
VFMSD,
VFMSH,
VFMSLD,
VFMSLDI,
VFMSLQ,
VFMSLQI,
VFMSS,
VFMSfd,
VFMSfq,
VFMShd,
VFMShq,
VFNMAD,
VFNMAH,
VFNMAS,
VFNMSD,
VFNMSH,
VFNMSS,
VFP_VMAXNMD,
VFP_VMAXNMH,
VFP_VMAXNMS,
VFP_VMINNMD,
VFP_VMINNMH,
VFP_VMINNMS,
VGETLNi32,
VGETLNs16,
VGETLNs8,
VGETLNu16,
VGETLNu8,
VHADDsv16i8,
VHADDsv2i32,
VHADDsv4i16,
VHADDsv4i32,
VHADDsv8i16,
VHADDsv8i8,
VHADDuv16i8,
VHADDuv2i32,
VHADDuv4i16,
VHADDuv4i32,
VHADDuv8i16,
VHADDuv8i8,
VHSUBsv16i8,
VHSUBsv2i32,
VHSUBsv4i16,
VHSUBsv4i32,
VHSUBsv8i16,
VHSUBsv8i8,
VHSUBuv16i8,
VHSUBuv2i32,
VHSUBuv4i16,
VHSUBuv4i32,
VHSUBuv8i16,
VHSUBuv8i8,
VINSH,
VJCVT,
VLD1DUPd16,
VLD1DUPd16wb_fixed,
VLD1DUPd16wb_register,
VLD1DUPd32,
VLD1DUPd32wb_fixed,
VLD1DUPd32wb_register,
VLD1DUPd8,
VLD1DUPd8wb_fixed,
VLD1DUPd8wb_register,
VLD1DUPq16,
VLD1DUPq16wb_fixed,
VLD1DUPq16wb_register,
VLD1DUPq32,
VLD1DUPq32wb_fixed,
VLD1DUPq32wb_register,
VLD1DUPq8,
VLD1DUPq8wb_fixed,
VLD1DUPq8wb_register,
VLD1LNd16,
VLD1LNd16_UPD,
VLD1LNd32,
VLD1LNd32_UPD,
VLD1LNd8,
VLD1LNd8_UPD,
VLD1LNq16Pseudo,
VLD1LNq16Pseudo_UPD,
VLD1LNq32Pseudo,
VLD1LNq32Pseudo_UPD,
VLD1LNq8Pseudo,
VLD1LNq8Pseudo_UPD,
VLD1d16,
VLD1d16Q,
VLD1d16QPseudo,
VLD1d16QPseudoWB_fixed,
VLD1d16QPseudoWB_register,
VLD1d16Qwb_fixed,
VLD1d16Qwb_register,
VLD1d16T,
VLD1d16TPseudo,
VLD1d16TPseudoWB_fixed,
VLD1d16TPseudoWB_register,
VLD1d16Twb_fixed,
VLD1d16Twb_register,
VLD1d16wb_fixed,
VLD1d16wb_register,
VLD1d32,
VLD1d32Q,
VLD1d32QPseudo,
VLD1d32QPseudoWB_fixed,
VLD1d32QPseudoWB_register,
VLD1d32Qwb_fixed,
VLD1d32Qwb_register,
VLD1d32T,
VLD1d32TPseudo,
VLD1d32TPseudoWB_fixed,
VLD1d32TPseudoWB_register,
VLD1d32Twb_fixed,
VLD1d32Twb_register,
VLD1d32wb_fixed,
VLD1d32wb_register,
VLD1d64,
VLD1d64Q,
VLD1d64QPseudo,
VLD1d64QPseudoWB_fixed,
VLD1d64QPseudoWB_register,
VLD1d64Qwb_fixed,
VLD1d64Qwb_register,
VLD1d64T,
VLD1d64TPseudo,
VLD1d64TPseudoWB_fixed,
VLD1d64TPseudoWB_register,
VLD1d64Twb_fixed,
VLD1d64Twb_register,
VLD1d64wb_fixed,
VLD1d64wb_register,
VLD1d8,
VLD1d8Q,
VLD1d8QPseudo,
VLD1d8QPseudoWB_fixed,
VLD1d8QPseudoWB_register,
VLD1d8Qwb_fixed,
VLD1d8Qwb_register,
VLD1d8T,
VLD1d8TPseudo,
VLD1d8TPseudoWB_fixed,
VLD1d8TPseudoWB_register,
VLD1d8Twb_fixed,
VLD1d8Twb_register,
VLD1d8wb_fixed,
VLD1d8wb_register,
VLD1q16,
VLD1q16HighQPseudo,
VLD1q16HighQPseudo_UPD,
VLD1q16HighTPseudo,
VLD1q16HighTPseudo_UPD,
VLD1q16LowQPseudo_UPD,
VLD1q16LowTPseudo_UPD,
VLD1q16wb_fixed,
VLD1q16wb_register,
VLD1q32,
VLD1q32HighQPseudo,
VLD1q32HighQPseudo_UPD,
VLD1q32HighTPseudo,
VLD1q32HighTPseudo_UPD,
VLD1q32LowQPseudo_UPD,
VLD1q32LowTPseudo_UPD,
VLD1q32wb_fixed,
VLD1q32wb_register,
VLD1q64,
VLD1q64HighQPseudo,
VLD1q64HighQPseudo_UPD,
VLD1q64HighTPseudo,
VLD1q64HighTPseudo_UPD,
VLD1q64LowQPseudo_UPD,
VLD1q64LowTPseudo_UPD,
VLD1q64wb_fixed,
VLD1q64wb_register,
VLD1q8,
VLD1q8HighQPseudo,
VLD1q8HighQPseudo_UPD,
VLD1q8HighTPseudo,
VLD1q8HighTPseudo_UPD,
VLD1q8LowQPseudo_UPD,
VLD1q8LowTPseudo_UPD,
VLD1q8wb_fixed,
VLD1q8wb_register,
VLD2DUPd16,
VLD2DUPd16wb_fixed,
VLD2DUPd16wb_register,
VLD2DUPd16x2,
VLD2DUPd16x2wb_fixed,
VLD2DUPd16x2wb_register,
VLD2DUPd32,
VLD2DUPd32wb_fixed,
VLD2DUPd32wb_register,
VLD2DUPd32x2,
VLD2DUPd32x2wb_fixed,
VLD2DUPd32x2wb_register,
VLD2DUPd8,
VLD2DUPd8wb_fixed,
VLD2DUPd8wb_register,
VLD2DUPd8x2,
VLD2DUPd8x2wb_fixed,
VLD2DUPd8x2wb_register,
VLD2DUPq16EvenPseudo,
VLD2DUPq16OddPseudo,
VLD2DUPq16OddPseudoWB_fixed,
VLD2DUPq16OddPseudoWB_register,
VLD2DUPq32EvenPseudo,
VLD2DUPq32OddPseudo,
VLD2DUPq32OddPseudoWB_fixed,
VLD2DUPq32OddPseudoWB_register,
VLD2DUPq8EvenPseudo,
VLD2DUPq8OddPseudo,
VLD2DUPq8OddPseudoWB_fixed,
VLD2DUPq8OddPseudoWB_register,
VLD2LNd16,
VLD2LNd16Pseudo,
VLD2LNd16Pseudo_UPD,
VLD2LNd16_UPD,
VLD2LNd32,
VLD2LNd32Pseudo,
VLD2LNd32Pseudo_UPD,
VLD2LNd32_UPD,
VLD2LNd8,
VLD2LNd8Pseudo,
VLD2LNd8Pseudo_UPD,
VLD2LNd8_UPD,
VLD2LNq16,
VLD2LNq16Pseudo,
VLD2LNq16Pseudo_UPD,
VLD2LNq16_UPD,
VLD2LNq32,
VLD2LNq32Pseudo,
VLD2LNq32Pseudo_UPD,
VLD2LNq32_UPD,
VLD2b16,
VLD2b16wb_fixed,
VLD2b16wb_register,
VLD2b32,
VLD2b32wb_fixed,
VLD2b32wb_register,
VLD2b8,
VLD2b8wb_fixed,
VLD2b8wb_register,
VLD2d16,
VLD2d16wb_fixed,
VLD2d16wb_register,
VLD2d32,
VLD2d32wb_fixed,
VLD2d32wb_register,
VLD2d8,
VLD2d8wb_fixed,
VLD2d8wb_register,
VLD2q16,
VLD2q16Pseudo,
VLD2q16PseudoWB_fixed,
VLD2q16PseudoWB_register,
VLD2q16wb_fixed,
VLD2q16wb_register,
VLD2q32,
VLD2q32Pseudo,
VLD2q32PseudoWB_fixed,
VLD2q32PseudoWB_register,
VLD2q32wb_fixed,
VLD2q32wb_register,
VLD2q8,
VLD2q8Pseudo,
VLD2q8PseudoWB_fixed,
VLD2q8PseudoWB_register,
VLD2q8wb_fixed,
VLD2q8wb_register,
VLD3DUPd16,
VLD3DUPd16Pseudo,
VLD3DUPd16Pseudo_UPD,
VLD3DUPd16_UPD,
VLD3DUPd32,
VLD3DUPd32Pseudo,
VLD3DUPd32Pseudo_UPD,
VLD3DUPd32_UPD,
VLD3DUPd8,
VLD3DUPd8Pseudo,
VLD3DUPd8Pseudo_UPD,
VLD3DUPd8_UPD,
VLD3DUPq16,
VLD3DUPq16EvenPseudo,
VLD3DUPq16OddPseudo,
VLD3DUPq16OddPseudo_UPD,
VLD3DUPq16_UPD,
VLD3DUPq32,
VLD3DUPq32EvenPseudo,
VLD3DUPq32OddPseudo,
VLD3DUPq32OddPseudo_UPD,
VLD3DUPq32_UPD,
VLD3DUPq8,
VLD3DUPq8EvenPseudo,
VLD3DUPq8OddPseudo,
VLD3DUPq8OddPseudo_UPD,
VLD3DUPq8_UPD,
VLD3LNd16,
VLD3LNd16Pseudo,
VLD3LNd16Pseudo_UPD,
VLD3LNd16_UPD,
VLD3LNd32,
VLD3LNd32Pseudo,
VLD3LNd32Pseudo_UPD,
VLD3LNd32_UPD,
VLD3LNd8,
VLD3LNd8Pseudo,
VLD3LNd8Pseudo_UPD,
VLD3LNd8_UPD,
VLD3LNq16,
VLD3LNq16Pseudo,
VLD3LNq16Pseudo_UPD,
VLD3LNq16_UPD,
VLD3LNq32,
VLD3LNq32Pseudo,
VLD3LNq32Pseudo_UPD,
VLD3LNq32_UPD,
VLD3d16,
VLD3d16Pseudo,
VLD3d16Pseudo_UPD,
VLD3d16_UPD,
VLD3d32,
VLD3d32Pseudo,
VLD3d32Pseudo_UPD,
VLD3d32_UPD,
VLD3d8,
VLD3d8Pseudo,
VLD3d8Pseudo_UPD,
VLD3d8_UPD,
VLD3q16,
VLD3q16Pseudo_UPD,
VLD3q16_UPD,
VLD3q16oddPseudo,
VLD3q16oddPseudo_UPD,
VLD3q32,
VLD3q32Pseudo_UPD,
VLD3q32_UPD,
VLD3q32oddPseudo,
VLD3q32oddPseudo_UPD,
VLD3q8,
VLD3q8Pseudo_UPD,
VLD3q8_UPD,
VLD3q8oddPseudo,
VLD3q8oddPseudo_UPD,
VLD4DUPd16,
VLD4DUPd16Pseudo,
VLD4DUPd16Pseudo_UPD,
VLD4DUPd16_UPD,
VLD4DUPd32,
VLD4DUPd32Pseudo,
VLD4DUPd32Pseudo_UPD,
VLD4DUPd32_UPD,
VLD4DUPd8,
VLD4DUPd8Pseudo,
VLD4DUPd8Pseudo_UPD,
VLD4DUPd8_UPD,
VLD4DUPq16,
VLD4DUPq16EvenPseudo,
VLD4DUPq16OddPseudo,
VLD4DUPq16OddPseudo_UPD,
VLD4DUPq16_UPD,
VLD4DUPq32,
VLD4DUPq32EvenPseudo,
VLD4DUPq32OddPseudo,
VLD4DUPq32OddPseudo_UPD,
VLD4DUPq32_UPD,
VLD4DUPq8,
VLD4DUPq8EvenPseudo,
VLD4DUPq8OddPseudo,
VLD4DUPq8OddPseudo_UPD,
VLD4DUPq8_UPD,
VLD4LNd16,
VLD4LNd16Pseudo,
VLD4LNd16Pseudo_UPD,
VLD4LNd16_UPD,
VLD4LNd32,
VLD4LNd32Pseudo,
VLD4LNd32Pseudo_UPD,
VLD4LNd32_UPD,
VLD4LNd8,
VLD4LNd8Pseudo,
VLD4LNd8Pseudo_UPD,
VLD4LNd8_UPD,
VLD4LNq16,
VLD4LNq16Pseudo,
VLD4LNq16Pseudo_UPD,
VLD4LNq16_UPD,
VLD4LNq32,
VLD4LNq32Pseudo,
VLD4LNq32Pseudo_UPD,
VLD4LNq32_UPD,
VLD4d16,
VLD4d16Pseudo,
VLD4d16Pseudo_UPD,
VLD4d16_UPD,
VLD4d32,
VLD4d32Pseudo,
VLD4d32Pseudo_UPD,
VLD4d32_UPD,
VLD4d8,
VLD4d8Pseudo,
VLD4d8Pseudo_UPD,
VLD4d8_UPD,
VLD4q16,
VLD4q16Pseudo_UPD,
VLD4q16_UPD,
VLD4q16oddPseudo,
VLD4q16oddPseudo_UPD,
VLD4q32,
VLD4q32Pseudo_UPD,
VLD4q32_UPD,
VLD4q32oddPseudo,
VLD4q32oddPseudo_UPD,
VLD4q8,
VLD4q8Pseudo_UPD,
VLD4q8_UPD,
VLD4q8oddPseudo,
VLD4q8oddPseudo_UPD,
VLDMDDB_UPD,
VLDMDIA,
VLDMDIA_UPD,
VLDMQIA,
VLDMSDB_UPD,
VLDMSIA,
VLDMSIA_UPD,
VLDRD,
VLDRH,
VLDRS,
VLDR_FPCXTNS_off,
VLDR_FPCXTNS_post,
VLDR_FPCXTNS_pre,
VLDR_FPCXTS_off,
VLDR_FPCXTS_post,
VLDR_FPCXTS_pre,
VLDR_FPSCR_NZCVQC_off,
VLDR_FPSCR_NZCVQC_post,
VLDR_FPSCR_NZCVQC_pre,
VLDR_FPSCR_off,
VLDR_FPSCR_post,
VLDR_FPSCR_pre,
VLDR_P0_off,
VLDR_P0_post,
VLDR_P0_pre,
VLDR_VPR_off,
VLDR_VPR_post,
VLDR_VPR_pre,
VLLDM,
VLLDM_T2,
VLSTM,
VLSTM_T2,
VMAXfd,
VMAXfq,
VMAXhd,
VMAXhq,
VMAXsv16i8,
VMAXsv2i32,
VMAXsv4i16,
VMAXsv4i32,
VMAXsv8i16,
VMAXsv8i8,
VMAXuv16i8,
VMAXuv2i32,
VMAXuv4i16,
VMAXuv4i32,
VMAXuv8i16,
VMAXuv8i8,
VMINfd,
VMINfq,
VMINhd,
VMINhq,
VMINsv16i8,
VMINsv2i32,
VMINsv4i16,
VMINsv4i32,
VMINsv8i16,
VMINsv8i8,
VMINuv16i8,
VMINuv2i32,
VMINuv4i16,
VMINuv4i32,
VMINuv8i16,
VMINuv8i8,
VMLAD,
VMLAH,
VMLALslsv2i32,
VMLALslsv4i16,
VMLALsluv2i32,
VMLALsluv4i16,
VMLALsv2i64,
VMLALsv4i32,
VMLALsv8i16,
VMLALuv2i64,
VMLALuv4i32,
VMLALuv8i16,
VMLAS,
VMLAfd,
VMLAfq,
VMLAhd,
VMLAhq,
VMLAslfd,
VMLAslfq,
VMLAslhd,
VMLAslhq,
VMLAslv2i32,
VMLAslv4i16,
VMLAslv4i32,
VMLAslv8i16,
VMLAv16i8,
VMLAv2i32,
VMLAv4i16,
VMLAv4i32,
VMLAv8i16,
VMLAv8i8,
VMLSD,
VMLSH,
VMLSLslsv2i32,
VMLSLslsv4i16,
VMLSLsluv2i32,
VMLSLsluv4i16,
VMLSLsv2i64,
VMLSLsv4i32,
VMLSLsv8i16,
VMLSLuv2i64,
VMLSLuv4i32,
VMLSLuv8i16,
VMLSS,
VMLSfd,
VMLSfq,
VMLShd,
VMLShq,
VMLSslfd,
VMLSslfq,
VMLSslhd,
VMLSslhq,
VMLSslv2i32,
VMLSslv4i16,
VMLSslv4i32,
VMLSslv8i16,
VMLSv16i8,
VMLSv2i32,
VMLSv4i16,
VMLSv4i32,
VMLSv8i16,
VMLSv8i8,
VMMLA,
VMOVD,
VMOVDRR,
VMOVH,
VMOVHR,
VMOVLsv2i64,
VMOVLsv4i32,
VMOVLsv8i16,
VMOVLuv2i64,
VMOVLuv4i32,
VMOVLuv8i16,
VMOVNv2i32,
VMOVNv4i16,
VMOVNv8i8,
VMOVRH,
VMOVRRD,
VMOVRRS,
VMOVRS,
VMOVS,
VMOVSR,
VMOVSRR,
VMOVv16i8,
VMOVv1i64,
VMOVv2f32,
VMOVv2i32,
VMOVv2i64,
VMOVv4f32,
VMOVv4i16,
VMOVv4i32,
VMOVv8i16,
VMOVv8i8,
VMRS,
VMRS_FPCXTNS,
VMRS_FPCXTS,
VMRS_FPEXC,
VMRS_FPINST,
VMRS_FPINST2,
VMRS_FPSCR_NZCVQC,
VMRS_FPSID,
VMRS_MVFR0,
VMRS_MVFR1,
VMRS_MVFR2,
VMRS_P0,
VMRS_VPR,
VMSR,
VMSR_FPCXTNS,
VMSR_FPCXTS,
VMSR_FPEXC,
VMSR_FPINST,
VMSR_FPINST2,
VMSR_FPSCR_NZCVQC,
VMSR_FPSID,
VMSR_P0,
VMSR_VPR,
VMULD,
VMULH,
VMULLp64,
VMULLp8,
VMULLslsv2i32,
VMULLslsv4i16,
VMULLsluv2i32,
VMULLsluv4i16,
VMULLsv2i64,
VMULLsv4i32,
VMULLsv8i16,
VMULLuv2i64,
VMULLuv4i32,
VMULLuv8i16,
VMULS,
VMULfd,
VMULfq,
VMULhd,
VMULhq,
VMULpd,
VMULpq,
VMULslfd,
VMULslfq,
VMULslhd,
VMULslhq,
VMULslv2i32,
VMULslv4i16,
VMULslv4i32,
VMULslv8i16,
VMULv16i8,
VMULv2i32,
VMULv4i16,
VMULv4i32,
VMULv8i16,
VMULv8i8,
VMVNd,
VMVNq,
VMVNv2i32,
VMVNv4i16,
VMVNv4i32,
VMVNv8i16,
VNEGD,
VNEGH,
VNEGS,
VNEGf32q,
VNEGfd,
VNEGhd,
VNEGhq,
VNEGs16d,
VNEGs16q,
VNEGs32d,
VNEGs32q,
VNEGs8d,
VNEGs8q,
VNMLAD,
VNMLAH,
VNMLAS,
VNMLSD,
VNMLSH,
VNMLSS,
VNMULD,
VNMULH,
VNMULS,
VORNd,
VORNq,
VORRd,
VORRiv2i32,
VORRiv4i16,
VORRiv4i32,
VORRiv8i16,
VORRq,
VPADALsv16i8,
VPADALsv2i32,
VPADALsv4i16,
VPADALsv4i32,
VPADALsv8i16,
VPADALsv8i8,
VPADALuv16i8,
VPADALuv2i32,
VPADALuv4i16,
VPADALuv4i32,
VPADALuv8i16,
VPADALuv8i8,
VPADDLsv16i8,
VPADDLsv2i32,
VPADDLsv4i16,
VPADDLsv4i32,
VPADDLsv8i16,
VPADDLsv8i8,
VPADDLuv16i8,
VPADDLuv2i32,
VPADDLuv4i16,
VPADDLuv4i32,
VPADDLuv8i16,
VPADDLuv8i8,
VPADDf,
VPADDh,
VPADDi16,
VPADDi32,
VPADDi8,
VPMAXf,
VPMAXh,
VPMAXs16,
VPMAXs32,
VPMAXs8,
VPMAXu16,
VPMAXu32,
VPMAXu8,
VPMINf,
VPMINh,
VPMINs16,
VPMINs32,
VPMINs8,
VPMINu16,
VPMINu32,
VPMINu8,
VQABSv16i8,
VQABSv2i32,
VQABSv4i16,
VQABSv4i32,
VQABSv8i16,
VQABSv8i8,
VQADDsv16i8,
VQADDsv1i64,
VQADDsv2i32,
VQADDsv2i64,
VQADDsv4i16,
VQADDsv4i32,
VQADDsv8i16,
VQADDsv8i8,
VQADDuv16i8,
VQADDuv1i64,
VQADDuv2i32,
VQADDuv2i64,
VQADDuv4i16,
VQADDuv4i32,
VQADDuv8i16,
VQADDuv8i8,
VQDMLALslv2i32,
VQDMLALslv4i16,
VQDMLALv2i64,
VQDMLALv4i32,
VQDMLSLslv2i32,
VQDMLSLslv4i16,
VQDMLSLv2i64,
VQDMLSLv4i32,
VQDMULHslv2i32,
VQDMULHslv4i16,
VQDMULHslv4i32,
VQDMULHslv8i16,
VQDMULHv2i32,
VQDMULHv4i16,
VQDMULHv4i32,
VQDMULHv8i16,
VQDMULLslv2i32,
VQDMULLslv4i16,
VQDMULLv2i64,
VQDMULLv4i32,
VQMOVNsuv2i32,
VQMOVNsuv4i16,
VQMOVNsuv8i8,
VQMOVNsv2i32,
VQMOVNsv4i16,
VQMOVNsv8i8,
VQMOVNuv2i32,
VQMOVNuv4i16,
VQMOVNuv8i8,
VQNEGv16i8,
VQNEGv2i32,
VQNEGv4i16,
VQNEGv4i32,
VQNEGv8i16,
VQNEGv8i8,
VQRDMLAHslv2i32,
VQRDMLAHslv4i16,
VQRDMLAHslv4i32,
VQRDMLAHslv8i16,
VQRDMLAHv2i32,
VQRDMLAHv4i16,
VQRDMLAHv4i32,
VQRDMLAHv8i16,
VQRDMLSHslv2i32,
VQRDMLSHslv4i16,
VQRDMLSHslv4i32,
VQRDMLSHslv8i16,
VQRDMLSHv2i32,
VQRDMLSHv4i16,
VQRDMLSHv4i32,
VQRDMLSHv8i16,
VQRDMULHslv2i32,
VQRDMULHslv4i16,
VQRDMULHslv4i32,
VQRDMULHslv8i16,
VQRDMULHv2i32,
VQRDMULHv4i16,
VQRDMULHv4i32,
VQRDMULHv8i16,
VQRSHLsv16i8,
VQRSHLsv1i64,
VQRSHLsv2i32,
VQRSHLsv2i64,
VQRSHLsv4i16,
VQRSHLsv4i32,
VQRSHLsv8i16,
VQRSHLsv8i8,
VQRSHLuv16i8,
VQRSHLuv1i64,
VQRSHLuv2i32,
VQRSHLuv2i64,
VQRSHLuv4i16,
VQRSHLuv4i32,
VQRSHLuv8i16,
VQRSHLuv8i8,
VQRSHRNsv2i32,
VQRSHRNsv4i16,
VQRSHRNsv8i8,
VQRSHRNuv2i32,
VQRSHRNuv4i16,
VQRSHRNuv8i8,
VQRSHRUNv2i32,
VQRSHRUNv4i16,
VQRSHRUNv8i8,
VQSHLsiv16i8,
VQSHLsiv1i64,
VQSHLsiv2i32,
VQSHLsiv2i64,
VQSHLsiv4i16,
VQSHLsiv4i32,
VQSHLsiv8i16,
VQSHLsiv8i8,
VQSHLsuv16i8,
VQSHLsuv1i64,
VQSHLsuv2i32,
VQSHLsuv2i64,
VQSHLsuv4i16,
VQSHLsuv4i32,
VQSHLsuv8i16,
VQSHLsuv8i8,
VQSHLsv16i8,
VQSHLsv1i64,
VQSHLsv2i32,
VQSHLsv2i64,
VQSHLsv4i16,
VQSHLsv4i32,
VQSHLsv8i16,
VQSHLsv8i8,
VQSHLuiv16i8,
VQSHLuiv1i64,
VQSHLuiv2i32,
VQSHLuiv2i64,
VQSHLuiv4i16,
VQSHLuiv4i32,
VQSHLuiv8i16,
VQSHLuiv8i8,
VQSHLuv16i8,
VQSHLuv1i64,
VQSHLuv2i32,
VQSHLuv2i64,
VQSHLuv4i16,
VQSHLuv4i32,
VQSHLuv8i16,
VQSHLuv8i8,
VQSHRNsv2i32,
VQSHRNsv4i16,
VQSHRNsv8i8,
VQSHRNuv2i32,
VQSHRNuv4i16,
VQSHRNuv8i8,
VQSHRUNv2i32,
VQSHRUNv4i16,
VQSHRUNv8i8,
VQSUBsv16i8,
VQSUBsv1i64,
VQSUBsv2i32,
VQSUBsv2i64,
VQSUBsv4i16,
VQSUBsv4i32,
VQSUBsv8i16,
VQSUBsv8i8,
VQSUBuv16i8,
VQSUBuv1i64,
VQSUBuv2i32,
VQSUBuv2i64,
VQSUBuv4i16,
VQSUBuv4i32,
VQSUBuv8i16,
VQSUBuv8i8,
VRADDHNv2i32,
VRADDHNv4i16,
VRADDHNv8i8,
VRECPEd,
VRECPEfd,
VRECPEfq,
VRECPEhd,
VRECPEhq,
VRECPEq,
VRECPSfd,
VRECPSfq,
VRECPShd,
VRECPShq,
VREV16d8,
VREV16q8,
VREV32d16,
VREV32d8,
VREV32q16,
VREV32q8,
VREV64d16,
VREV64d32,
VREV64d8,
VREV64q16,
VREV64q32,
VREV64q8,
VRHADDsv16i8,
VRHADDsv2i32,
VRHADDsv4i16,
VRHADDsv4i32,
VRHADDsv8i16,
VRHADDsv8i8,
VRHADDuv16i8,
VRHADDuv2i32,
VRHADDuv4i16,
VRHADDuv4i32,
VRHADDuv8i16,
VRHADDuv8i8,
VRINTAD,
VRINTAH,
VRINTANDf,
VRINTANDh,
VRINTANQf,
VRINTANQh,
VRINTAS,
VRINTMD,
VRINTMH,
VRINTMNDf,
VRINTMNDh,
VRINTMNQf,
VRINTMNQh,
VRINTMS,
VRINTND,
VRINTNH,
VRINTNNDf,
VRINTNNDh,
VRINTNNQf,
VRINTNNQh,
VRINTNS,
VRINTPD,
VRINTPH,
VRINTPNDf,
VRINTPNDh,
VRINTPNQf,
VRINTPNQh,
VRINTPS,
VRINTRD,
VRINTRH,
VRINTRS,
VRINTXD,
VRINTXH,
VRINTXNDf,
VRINTXNDh,
VRINTXNQf,
VRINTXNQh,
VRINTXS,
VRINTZD,
VRINTZH,
VRINTZNDf,
VRINTZNDh,
VRINTZNQf,
VRINTZNQh,
VRINTZS,
VRSHLsv16i8,
VRSHLsv1i64,
VRSHLsv2i32,
VRSHLsv2i64,
VRSHLsv4i16,
VRSHLsv4i32,
VRSHLsv8i16,
VRSHLsv8i8,
VRSHLuv16i8,
VRSHLuv1i64,
VRSHLuv2i32,
VRSHLuv2i64,
VRSHLuv4i16,
VRSHLuv4i32,
VRSHLuv8i16,
VRSHLuv8i8,
VRSHRNv2i32,
VRSHRNv4i16,
VRSHRNv8i8,
VRSHRsv16i8,
VRSHRsv1i64,
VRSHRsv2i32,
VRSHRsv2i64,
VRSHRsv4i16,
VRSHRsv4i32,
VRSHRsv8i16,
VRSHRsv8i8,
VRSHRuv16i8,
VRSHRuv1i64,
VRSHRuv2i32,
VRSHRuv2i64,
VRSHRuv4i16,
VRSHRuv4i32,
VRSHRuv8i16,
VRSHRuv8i8,
VRSQRTEd,
VRSQRTEfd,
VRSQRTEfq,
VRSQRTEhd,
VRSQRTEhq,
VRSQRTEq,
VRSQRTSfd,
VRSQRTSfq,
VRSQRTShd,
VRSQRTShq,
VRSRAsv16i8,
VRSRAsv1i64,
VRSRAsv2i32,
VRSRAsv2i64,
VRSRAsv4i16,
VRSRAsv4i32,
VRSRAsv8i16,
VRSRAsv8i8,
VRSRAuv16i8,
VRSRAuv1i64,
VRSRAuv2i32,
VRSRAuv2i64,
VRSRAuv4i16,
VRSRAuv4i32,
VRSRAuv8i16,
VRSRAuv8i8,
VRSUBHNv2i32,
VRSUBHNv4i16,
VRSUBHNv8i8,
VSCCLRMD,
VSCCLRMS,
VSDOTD,
VSDOTDI,
VSDOTQ,
VSDOTQI,
VSELEQD,
VSELEQH,
VSELEQS,
VSELGED,
VSELGEH,
VSELGES,
VSELGTD,
VSELGTH,
VSELGTS,
VSELVSD,
VSELVSH,
VSELVSS,
VSETLNi16,
VSETLNi32,
VSETLNi8,
VSHLLi16,
VSHLLi32,
VSHLLi8,
VSHLLsv2i64,
VSHLLsv4i32,
VSHLLsv8i16,
VSHLLuv2i64,
VSHLLuv4i32,
VSHLLuv8i16,
VSHLiv16i8,
VSHLiv1i64,
VSHLiv2i32,
VSHLiv2i64,
VSHLiv4i16,
VSHLiv4i32,
VSHLiv8i16,
VSHLiv8i8,
VSHLsv16i8,
VSHLsv1i64,
VSHLsv2i32,
VSHLsv2i64,
VSHLsv4i16,
VSHLsv4i32,
VSHLsv8i16,
VSHLsv8i8,
VSHLuv16i8,
VSHLuv1i64,
VSHLuv2i32,
VSHLuv2i64,
VSHLuv4i16,
VSHLuv4i32,
VSHLuv8i16,
VSHLuv8i8,
VSHRNv2i32,
VSHRNv4i16,
VSHRNv8i8,
VSHRsv16i8,
VSHRsv1i64,
VSHRsv2i32,
VSHRsv2i64,
VSHRsv4i16,
VSHRsv4i32,
VSHRsv8i16,
VSHRsv8i8,
VSHRuv16i8,
VSHRuv1i64,
VSHRuv2i32,
VSHRuv2i64,
VSHRuv4i16,
VSHRuv4i32,
VSHRuv8i16,
VSHRuv8i8,
VSHTOD,
VSHTOH,
VSHTOS,
VSITOD,
VSITOH,
VSITOS,
VSLIv16i8,
VSLIv1i64,
VSLIv2i32,
VSLIv2i64,
VSLIv4i16,
VSLIv4i32,
VSLIv8i16,
VSLIv8i8,
VSLTOD,
VSLTOH,
VSLTOS,
VSMMLA,
VSQRTD,
VSQRTH,
VSQRTS,
VSRAsv16i8,
VSRAsv1i64,
VSRAsv2i32,
VSRAsv2i64,
VSRAsv4i16,
VSRAsv4i32,
VSRAsv8i16,
VSRAsv8i8,
VSRAuv16i8,
VSRAuv1i64,
VSRAuv2i32,
VSRAuv2i64,
VSRAuv4i16,
VSRAuv4i32,
VSRAuv8i16,
VSRAuv8i8,
VSRIv16i8,
VSRIv1i64,
VSRIv2i32,
VSRIv2i64,
VSRIv4i16,
VSRIv4i32,
VSRIv8i16,
VSRIv8i8,
VST1LNd16,
VST1LNd16_UPD,
VST1LNd32,
VST1LNd32_UPD,
VST1LNd8,
VST1LNd8_UPD,
VST1LNq16Pseudo,
VST1LNq16Pseudo_UPD,
VST1LNq32Pseudo,
VST1LNq32Pseudo_UPD,
VST1LNq8Pseudo,
VST1LNq8Pseudo_UPD,
VST1d16,
VST1d16Q,
VST1d16QPseudo,
VST1d16QPseudoWB_fixed,
VST1d16QPseudoWB_register,
VST1d16Qwb_fixed,
VST1d16Qwb_register,
VST1d16T,
VST1d16TPseudo,
VST1d16TPseudoWB_fixed,
VST1d16TPseudoWB_register,
VST1d16Twb_fixed,
VST1d16Twb_register,
VST1d16wb_fixed,
VST1d16wb_register,
VST1d32,
VST1d32Q,
VST1d32QPseudo,
VST1d32QPseudoWB_fixed,
VST1d32QPseudoWB_register,
VST1d32Qwb_fixed,
VST1d32Qwb_register,
VST1d32T,
VST1d32TPseudo,
VST1d32TPseudoWB_fixed,
VST1d32TPseudoWB_register,
VST1d32Twb_fixed,
VST1d32Twb_register,
VST1d32wb_fixed,
VST1d32wb_register,
VST1d64,
VST1d64Q,
VST1d64QPseudo,
VST1d64QPseudoWB_fixed,
VST1d64QPseudoWB_register,
VST1d64Qwb_fixed,
VST1d64Qwb_register,
VST1d64T,
VST1d64TPseudo,
VST1d64TPseudoWB_fixed,
VST1d64TPseudoWB_register,
VST1d64Twb_fixed,
VST1d64Twb_register,
VST1d64wb_fixed,
VST1d64wb_register,
VST1d8,
VST1d8Q,
VST1d8QPseudo,
VST1d8QPseudoWB_fixed,
VST1d8QPseudoWB_register,
VST1d8Qwb_fixed,
VST1d8Qwb_register,
VST1d8T,
VST1d8TPseudo,
VST1d8TPseudoWB_fixed,
VST1d8TPseudoWB_register,
VST1d8Twb_fixed,
VST1d8Twb_register,
VST1d8wb_fixed,
VST1d8wb_register,
VST1q16,
VST1q16HighQPseudo,
VST1q16HighQPseudo_UPD,
VST1q16HighTPseudo,
VST1q16HighTPseudo_UPD,
VST1q16LowQPseudo_UPD,
VST1q16LowTPseudo_UPD,
VST1q16wb_fixed,
VST1q16wb_register,
VST1q32,
VST1q32HighQPseudo,
VST1q32HighQPseudo_UPD,
VST1q32HighTPseudo,
VST1q32HighTPseudo_UPD,
VST1q32LowQPseudo_UPD,
VST1q32LowTPseudo_UPD,
VST1q32wb_fixed,
VST1q32wb_register,
VST1q64,
VST1q64HighQPseudo,
VST1q64HighQPseudo_UPD,
VST1q64HighTPseudo,
VST1q64HighTPseudo_UPD,
VST1q64LowQPseudo_UPD,
VST1q64LowTPseudo_UPD,
VST1q64wb_fixed,
VST1q64wb_register,
VST1q8,
VST1q8HighQPseudo,
VST1q8HighQPseudo_UPD,
VST1q8HighTPseudo,
VST1q8HighTPseudo_UPD,
VST1q8LowQPseudo_UPD,
VST1q8LowTPseudo_UPD,
VST1q8wb_fixed,
VST1q8wb_register,
VST2LNd16,
VST2LNd16Pseudo,
VST2LNd16Pseudo_UPD,
VST2LNd16_UPD,
VST2LNd32,
VST2LNd32Pseudo,
VST2LNd32Pseudo_UPD,
VST2LNd32_UPD,
VST2LNd8,
VST2LNd8Pseudo,
VST2LNd8Pseudo_UPD,
VST2LNd8_UPD,
VST2LNq16,
VST2LNq16Pseudo,
VST2LNq16Pseudo_UPD,
VST2LNq16_UPD,
VST2LNq32,
VST2LNq32Pseudo,
VST2LNq32Pseudo_UPD,
VST2LNq32_UPD,
VST2b16,
VST2b16wb_fixed,
VST2b16wb_register,
VST2b32,
VST2b32wb_fixed,
VST2b32wb_register,
VST2b8,
VST2b8wb_fixed,
VST2b8wb_register,
VST2d16,
VST2d16wb_fixed,
VST2d16wb_register,
VST2d32,
VST2d32wb_fixed,
VST2d32wb_register,
VST2d8,
VST2d8wb_fixed,
VST2d8wb_register,
VST2q16,
VST2q16Pseudo,
VST2q16PseudoWB_fixed,
VST2q16PseudoWB_register,
VST2q16wb_fixed,
VST2q16wb_register,
VST2q32,
VST2q32Pseudo,
VST2q32PseudoWB_fixed,
VST2q32PseudoWB_register,
VST2q32wb_fixed,
VST2q32wb_register,
VST2q8,
VST2q8Pseudo,
VST2q8PseudoWB_fixed,
VST2q8PseudoWB_register,
VST2q8wb_fixed,
VST2q8wb_register,
VST3LNd16,
VST3LNd16Pseudo,
VST3LNd16Pseudo_UPD,
VST3LNd16_UPD,
VST3LNd32,
VST3LNd32Pseudo,
VST3LNd32Pseudo_UPD,
VST3LNd32_UPD,
VST3LNd8,
VST3LNd8Pseudo,
VST3LNd8Pseudo_UPD,
VST3LNd8_UPD,
VST3LNq16,
VST3LNq16Pseudo,
VST3LNq16Pseudo_UPD,
VST3LNq16_UPD,
VST3LNq32,
VST3LNq32Pseudo,
VST3LNq32Pseudo_UPD,
VST3LNq32_UPD,
VST3d16,
VST3d16Pseudo,
VST3d16Pseudo_UPD,
VST3d16_UPD,
VST3d32,
VST3d32Pseudo,
VST3d32Pseudo_UPD,
VST3d32_UPD,
VST3d8,
VST3d8Pseudo,
VST3d8Pseudo_UPD,
VST3d8_UPD,
VST3q16,
VST3q16Pseudo_UPD,
VST3q16_UPD,
VST3q16oddPseudo,
VST3q16oddPseudo_UPD,
VST3q32,
VST3q32Pseudo_UPD,
VST3q32_UPD,
VST3q32oddPseudo,
VST3q32oddPseudo_UPD,
VST3q8,
VST3q8Pseudo_UPD,
VST3q8_UPD,
VST3q8oddPseudo,
VST3q8oddPseudo_UPD,
VST4LNd16,
VST4LNd16Pseudo,
VST4LNd16Pseudo_UPD,
VST4LNd16_UPD,
VST4LNd32,
VST4LNd32Pseudo,
VST4LNd32Pseudo_UPD,
VST4LNd32_UPD,
VST4LNd8,
VST4LNd8Pseudo,
VST4LNd8Pseudo_UPD,
VST4LNd8_UPD,
VST4LNq16,
VST4LNq16Pseudo,
VST4LNq16Pseudo_UPD,
VST4LNq16_UPD,
VST4LNq32,
VST4LNq32Pseudo,
VST4LNq32Pseudo_UPD,
VST4LNq32_UPD,
VST4d16,
VST4d16Pseudo,
VST4d16Pseudo_UPD,
VST4d16_UPD,
VST4d32,
VST4d32Pseudo,
VST4d32Pseudo_UPD,
VST4d32_UPD,
VST4d8,
VST4d8Pseudo,
VST4d8Pseudo_UPD,
VST4d8_UPD,
VST4q16,
VST4q16Pseudo_UPD,
VST4q16_UPD,
VST4q16oddPseudo,
VST4q16oddPseudo_UPD,
VST4q32,
VST4q32Pseudo_UPD,
VST4q32_UPD,
VST4q32oddPseudo,
VST4q32oddPseudo_UPD,
VST4q8,
VST4q8Pseudo_UPD,
VST4q8_UPD,
VST4q8oddPseudo,
VST4q8oddPseudo_UPD,
VSTMDDB_UPD,
VSTMDIA,
VSTMDIA_UPD,
VSTMQIA,
VSTMSDB_UPD,
VSTMSIA,
VSTMSIA_UPD,
VSTRD,
VSTRH,
VSTRS,
VSTR_FPCXTNS_off,
VSTR_FPCXTNS_post,
VSTR_FPCXTNS_pre,
VSTR_FPCXTS_off,
VSTR_FPCXTS_post,
VSTR_FPCXTS_pre,
VSTR_FPSCR_NZCVQC_off,
VSTR_FPSCR_NZCVQC_post,
VSTR_FPSCR_NZCVQC_pre,
VSTR_FPSCR_off,
VSTR_FPSCR_post,
VSTR_FPSCR_pre,
VSTR_P0_off,
VSTR_P0_post,
VSTR_P0_pre,
VSTR_VPR_off,
VSTR_VPR_post,
VSTR_VPR_pre,
VSUBD,
VSUBH,
VSUBHNv2i32,
VSUBHNv4i16,
VSUBHNv8i8,
VSUBLsv2i64,
VSUBLsv4i32,
VSUBLsv8i16,
VSUBLuv2i64,
VSUBLuv4i32,
VSUBLuv8i16,
VSUBS,
VSUBWsv2i64,
VSUBWsv4i32,
VSUBWsv8i16,
VSUBWuv2i64,
VSUBWuv4i32,
VSUBWuv8i16,
VSUBfd,
VSUBfq,
VSUBhd,
VSUBhq,
VSUBv16i8,
VSUBv1i64,
VSUBv2i32,
VSUBv2i64,
VSUBv4i16,
VSUBv4i32,
VSUBv8i16,
VSUBv8i8,
VSUDOTDI,
VSUDOTQI,
VSWPd,
VSWPq,
VTBL1,
VTBL2,
VTBL3,
VTBL3Pseudo,
VTBL4,
VTBL4Pseudo,
VTBX1,
VTBX2,
VTBX3,
VTBX3Pseudo,
VTBX4,
VTBX4Pseudo,
VTOSHD,
VTOSHH,
VTOSHS,
VTOSIRD,
VTOSIRH,
VTOSIRS,
VTOSIZD,
VTOSIZH,
VTOSIZS,
VTOSLD,
VTOSLH,
VTOSLS,
VTOUHD,
VTOUHH,
VTOUHS,
VTOUIRD,
VTOUIRH,
VTOUIRS,
VTOUIZD,
VTOUIZH,
VTOUIZS,
VTOULD,
VTOULH,
VTOULS,
VTRNd16,
VTRNd32,
VTRNd8,
VTRNq16,
VTRNq32,
VTRNq8,
VTSTv16i8,
VTSTv2i32,
VTSTv4i16,
VTSTv4i32,
VTSTv8i16,
VTSTv8i8,
VUDOTD,
VUDOTDI,
VUDOTQ,
VUDOTQI,
VUHTOD,
VUHTOH,
VUHTOS,
VUITOD,
VUITOH,
VUITOS,
VULTOD,
VULTOH,
VULTOS,
VUMMLA,
VUSDOTD,
VUSDOTDI,
VUSDOTQ,
VUSDOTQI,
VUSMMLA,
VUZPd16,
VUZPd8,
VUZPq16,
VUZPq32,
VUZPq8,
VZIPd16,
VZIPd8,
VZIPq16,
VZIPq32,
VZIPq8,
sysLDMDA,
sysLDMDA_UPD,
sysLDMDB,
sysLDMDB_UPD,
sysLDMIA,
sysLDMIA_UPD,
sysLDMIB,
sysLDMIB_UPD,
sysSTMDA,
sysSTMDA_UPD,
sysSTMDB,
sysSTMDB_UPD,
sysSTMIA,
sysSTMIA_UPD,
sysSTMIB,
sysSTMIB_UPD,
t2ADCri,
t2ADCrr,
t2ADCrs,
t2ADDri,
t2ADDri12,
t2ADDrr,
t2ADDrs,
t2ADDspImm,
t2ADDspImm12,
t2ADR,
t2ANDri,
t2ANDrr,
t2ANDrs,
t2ASRri,
t2ASRrr,
t2ASRs1,
t2AUT,
t2AUTG,
t2B,
t2BFC,
t2BFI,
t2BFLi,
t2BFLr,
t2BFi,
t2BFic,
t2BFr,
t2BICri,
t2BICrr,
t2BICrs,
t2BTI,
t2BXAUT,
t2BXJ,
t2Bcc,
t2CDP,
t2CDP2,
t2CLREX,
t2CLRM,
t2CLZ,
t2CMNri,
t2CMNzrr,
t2CMNzrs,
t2CMPri,
t2CMPrr,
t2CMPrs,
t2CPS1p,
t2CPS2p,
t2CPS3p,
t2CRC32B,
t2CRC32CB,
t2CRC32CH,
t2CRC32CW,
t2CRC32H,
t2CRC32W,
t2CSEL,
t2CSINC,
t2CSINV,
t2CSNEG,
t2DBG,
t2DCPS1,
t2DCPS2,
t2DCPS3,
t2DLS,
t2DMB,
t2DSB,
t2EORri,
t2EORrr,
t2EORrs,
t2HINT,
t2HVC,
t2ISB,
t2IT,
t2Int_eh_sjlj_setjmp,
t2Int_eh_sjlj_setjmp_nofp,
t2LDA,
t2LDAB,
t2LDAEX,
t2LDAEXB,
t2LDAEXD,
t2LDAEXH,
t2LDAH,
t2LDC2L_OFFSET,
t2LDC2L_OPTION,
t2LDC2L_POST,
t2LDC2L_PRE,
t2LDC2_OFFSET,
t2LDC2_OPTION,
t2LDC2_POST,
t2LDC2_PRE,
t2LDCL_OFFSET,
t2LDCL_OPTION,
t2LDCL_POST,
t2LDCL_PRE,
t2LDC_OFFSET,
t2LDC_OPTION,
t2LDC_POST,
t2LDC_PRE,
t2LDMDB,
t2LDMDB_UPD,
t2LDMIA,
t2LDMIA_UPD,
t2LDRBT,
t2LDRB_POST,
t2LDRB_PRE,
t2LDRBi12,
t2LDRBi8,
t2LDRBpci,
t2LDRBs,
t2LDRD_POST,
t2LDRD_PRE,
t2LDRDi8,
t2LDREX,
t2LDREXB,
t2LDREXD,
t2LDREXH,
t2LDRHT,
t2LDRH_POST,
t2LDRH_PRE,
t2LDRHi12,
t2LDRHi8,
t2LDRHpci,
t2LDRHs,
t2LDRSBT,
t2LDRSB_POST,
t2LDRSB_PRE,
t2LDRSBi12,
t2LDRSBi8,
t2LDRSBpci,
t2LDRSBs,
t2LDRSHT,
t2LDRSH_POST,
t2LDRSH_PRE,
t2LDRSHi12,
t2LDRSHi8,
t2LDRSHpci,
t2LDRSHs,
t2LDRT,
t2LDR_POST,
t2LDR_PRE,
t2LDRi12,
t2LDRi8,
t2LDRpci,
t2LDRs,
t2LE,
t2LEUpdate,
t2LSLri,
t2LSLrr,
t2LSRri,
t2LSRrr,
t2LSRs1,
t2MCR,
t2MCR2,
t2MCRR,
t2MCRR2,
t2MLA,
t2MLS,
t2MOVTi16,
t2MOVi,
t2MOVi16,
t2MOVr,
t2MRC,
t2MRC2,
t2MRRC,
t2MRRC2,
t2MRS_AR,
t2MRS_M,
t2MRSbanked,
t2MRSsys_AR,
t2MSR_AR,
t2MSR_M,
t2MSRbanked,
t2MUL,
t2MVNi,
t2MVNr,
t2MVNs,
t2ORNri,
t2ORNrr,
t2ORNrs,
t2ORRri,
t2ORRrr,
t2ORRrs,
t2PAC,
t2PACBTI,
t2PACG,
t2PKHBT,
t2PKHTB,
t2PLDWi12,
t2PLDWi8,
t2PLDWs,
t2PLDi12,
t2PLDi8,
t2PLDpci,
t2PLDs,
t2PLIi12,
t2PLIi8,
t2PLIpci,
t2PLIs,
t2QADD,
t2QADD16,
t2QADD8,
t2QASX,
t2QDADD,
t2QDSUB,
t2QSAX,
t2QSUB,
t2QSUB16,
t2QSUB8,
t2RBIT,
t2REV,
t2REV16,
t2REVSH,
t2RFEDB,
t2RFEDBW,
t2RFEIA,
t2RFEIAW,
t2RORri,
t2RORrr,
t2RRX,
t2RSBri,
t2RSBrr,
t2RSBrs,
t2SADD16,
t2SADD8,
t2SASX,
t2SB,
t2SBCri,
t2SBCrr,
t2SBCrs,
t2SBFX,
t2SDIV,
t2SEL,
t2SETPAN,
t2SG,
t2SHADD16,
t2SHADD8,
t2SHASX,
t2SHSAX,
t2SHSUB16,
t2SHSUB8,
t2SMC,
t2SMLABB,
t2SMLABT,
t2SMLAD,
t2SMLADX,
t2SMLAL,
t2SMLALBB,
t2SMLALBT,
t2SMLALD,
t2SMLALDX,
t2SMLALTB,
t2SMLALTT,
t2SMLATB,
t2SMLATT,
t2SMLAWB,
t2SMLAWT,
t2SMLSD,
t2SMLSDX,
t2SMLSLD,
t2SMLSLDX,
t2SMMLA,
t2SMMLAR,
t2SMMLS,
t2SMMLSR,
t2SMMUL,
t2SMMULR,
t2SMUAD,
t2SMUADX,
t2SMULBB,
t2SMULBT,
t2SMULL,
t2SMULTB,
t2SMULTT,
t2SMULWB,
t2SMULWT,
t2SMUSD,
t2SMUSDX,
t2SRSDB,
t2SRSDB_UPD,
t2SRSIA,
t2SRSIA_UPD,
t2SSAT,
t2SSAT16,
t2SSAX,
t2SSUB16,
t2SSUB8,
t2STC2L_OFFSET,
t2STC2L_OPTION,
t2STC2L_POST,
t2STC2L_PRE,
t2STC2_OFFSET,
t2STC2_OPTION,
t2STC2_POST,
t2STC2_PRE,
t2STCL_OFFSET,
t2STCL_OPTION,
t2STCL_POST,
t2STCL_PRE,
t2STC_OFFSET,
t2STC_OPTION,
t2STC_POST,
t2STC_PRE,
t2STL,
t2STLB,
t2STLEX,
t2STLEXB,
t2STLEXD,
t2STLEXH,
t2STLH,
t2STMDB,
t2STMDB_UPD,
t2STMIA,
t2STMIA_UPD,
t2STRBT,
t2STRB_POST,
t2STRB_PRE,
t2STRBi12,
t2STRBi8,
t2STRBs,
t2STRD_POST,
t2STRD_PRE,
t2STRDi8,
t2STREX,
t2STREXB,
t2STREXD,
t2STREXH,
t2STRHT,
t2STRH_POST,
t2STRH_PRE,
t2STRHi12,
t2STRHi8,
t2STRHs,
t2STRT,
t2STR_POST,
t2STR_PRE,
t2STRi12,
t2STRi8,
t2STRs,
t2SUBS_PC_LR,
t2SUBri,
t2SUBri12,
t2SUBrr,
t2SUBrs,
t2SUBspImm,
t2SUBspImm12,
t2SXTAB,
t2SXTAB16,
t2SXTAH,
t2SXTB,
t2SXTB16,
t2SXTH,
t2TBB,
t2TBH,
t2TEQri,
t2TEQrr,
t2TEQrs,
t2TSB,
t2TSTri,
t2TSTrr,
t2TSTrs,
t2TT,
t2TTA,
t2TTAT,
t2TTT,
t2UADD16,
t2UADD8,
t2UASX,
t2UBFX,
t2UDF,
t2UDIV,
t2UHADD16,
t2UHADD8,
t2UHASX,
t2UHSAX,
t2UHSUB16,
t2UHSUB8,
t2UMAAL,
t2UMLAL,
t2UMULL,
t2UQADD16,
t2UQADD8,
t2UQASX,
t2UQSAX,
t2UQSUB16,
t2UQSUB8,
t2USAD8,
t2USADA8,
t2USAT,
t2USAT16,
t2USAX,
t2USUB16,
t2USUB8,
t2UXTAB,
t2UXTAB16,
t2UXTAH,
t2UXTB,
t2UXTB16,
t2UXTH,
t2WLS,
tADC,
tADDhirr,
tADDi3,
tADDi8,
tADDrSP,
tADDrSPi,
tADDrr,
tADDspi,
tADDspr,
tADR,
tAND,
tASRri,
tASRrr,
tB,
tBIC,
tBKPT,
tBL,
tBLXNSr,
tBLXi,
tBLXr,
tBX,
tBXNS,
tBcc,
tCBNZ,
tCBZ,
tCMNz,
tCMPhir,
tCMPi8,
tCMPr,
tCPS,
tEOR,
tHINT,
tHLT,
tInt_WIN_eh_sjlj_longjmp,
tInt_eh_sjlj_longjmp,
tInt_eh_sjlj_setjmp,
tLDMIA,
tLDRBi,
tLDRBr,
tLDRHi,
tLDRHr,
tLDRSB,
tLDRSH,
tLDRi,
tLDRpci,
tLDRr,
tLDRspi,
tLSLri,
tLSLrr,
tLSRri,
tLSRrr,
tMOVSr,
tMOVi8,
tMOVr,
tMUL,
tMVN,
tORR,
tPICADD,
tPOP,
tPUSH,
tREV,
tREV16,
tREVSH,
tROR,
tRSB,
tSBC,
tSETEND,
tSTMIA_UPD,
tSTRBi,
tSTRBr,
tSTRHi,
tSTRHr,
tSTRi,
tSTRr,
tSTRspi,
tSUBi3,
tSUBi8,
tSUBrr,
tSUBspi,
tSVC,
tSXTB,
tSXTH,
tTRAP,
tTST,
tUDF,
tUXTB,
tUXTH,
t__brkdiv0,
INSTRUCTION_LIST_END,
UNKNOWN(u64),
}
impl From<u64> for Opcode {
fn from(value: u64) -> Self {
match value {
0 => Opcode::PHI,
1 => Opcode::INLINEASM,
2 => Opcode::INLINEASM_BR,
3 => Opcode::CFI_INSTRUCTION,
4 => Opcode::EH_LABEL,
5 => Opcode::GC_LABEL,
6 => Opcode::ANNOTATION_LABEL,
7 => Opcode::KILL,
8 => Opcode::EXTRACT_SUBREG,
9 => Opcode::INSERT_SUBREG,
10 => Opcode::IMPLICIT_DEF,
11 => Opcode::INIT_UNDEF,
12 => Opcode::SUBREG_TO_REG,
13 => Opcode::COPY_TO_REGCLASS,
14 => Opcode::DBG_VALUE,
15 => Opcode::DBG_VALUE_LIST,
16 => Opcode::DBG_INSTR_REF,
17 => Opcode::DBG_PHI,
18 => Opcode::DBG_LABEL,
19 => Opcode::REG_SEQUENCE,
20 => Opcode::COPY,
21 => Opcode::COPY_LANEMASK,
22 => Opcode::BUNDLE,
23 => Opcode::LIFETIME_START,
24 => Opcode::LIFETIME_END,
25 => Opcode::PSEUDO_PROBE,
26 => Opcode::ARITH_FENCE,
27 => Opcode::STACKMAP,
28 => Opcode::FENTRY_CALL,
29 => Opcode::PATCHPOINT,
30 => Opcode::LOAD_STACK_GUARD,
31 => Opcode::PREALLOCATED_SETUP,
32 => Opcode::PREALLOCATED_ARG,
33 => Opcode::STATEPOINT,
34 => Opcode::LOCAL_ESCAPE,
35 => Opcode::FAULTING_OP,
36 => Opcode::PATCHABLE_OP,
37 => Opcode::PATCHABLE_FUNCTION_ENTER,
38 => Opcode::PATCHABLE_RET,
39 => Opcode::PATCHABLE_FUNCTION_EXIT,
40 => Opcode::PATCHABLE_TAIL_CALL,
41 => Opcode::PATCHABLE_EVENT_CALL,
42 => Opcode::PATCHABLE_TYPED_EVENT_CALL,
43 => Opcode::ICALL_BRANCH_FUNNEL,
44 => Opcode::FAKE_USE,
45 => Opcode::MEMBARRIER,
46 => Opcode::JUMP_TABLE_DEBUG_INFO,
47 => Opcode::RELOC_NONE,
48 => Opcode::CONVERGENCECTRL_ENTRY,
49 => Opcode::CONVERGENCECTRL_ANCHOR,
50 => Opcode::CONVERGENCECTRL_LOOP,
51 => Opcode::CONVERGENCECTRL_GLUE,
52 => Opcode::G_ASSERT_SEXT,
53 => Opcode::G_ASSERT_ZEXT,
54 => Opcode::G_ASSERT_ALIGN,
55 => Opcode::G_ADD,
56 => Opcode::G_SUB,
57 => Opcode::G_MUL,
58 => Opcode::G_SDIV,
59 => Opcode::G_UDIV,
60 => Opcode::G_SREM,
61 => Opcode::G_UREM,
62 => Opcode::G_SDIVREM,
63 => Opcode::G_UDIVREM,
64 => Opcode::G_AND,
65 => Opcode::G_OR,
66 => Opcode::G_XOR,
67 => Opcode::G_ABDS,
68 => Opcode::G_ABDU,
69 => Opcode::G_UAVGFLOOR,
70 => Opcode::G_UAVGCEIL,
71 => Opcode::G_SAVGFLOOR,
72 => Opcode::G_SAVGCEIL,
73 => Opcode::G_IMPLICIT_DEF,
74 => Opcode::G_PHI,
75 => Opcode::G_FRAME_INDEX,
76 => Opcode::G_GLOBAL_VALUE,
77 => Opcode::G_PTRAUTH_GLOBAL_VALUE,
78 => Opcode::G_CONSTANT_POOL,
79 => Opcode::G_EXTRACT,
80 => Opcode::G_UNMERGE_VALUES,
81 => Opcode::G_INSERT,
82 => Opcode::G_MERGE_VALUES,
83 => Opcode::G_BUILD_VECTOR,
84 => Opcode::G_BUILD_VECTOR_TRUNC,
85 => Opcode::G_CONCAT_VECTORS,
86 => Opcode::G_PTRTOINT,
87 => Opcode::G_INTTOPTR,
88 => Opcode::G_BITCAST,
89 => Opcode::G_FREEZE,
90 => Opcode::G_CONSTANT_FOLD_BARRIER,
91 => Opcode::G_INTRINSIC_FPTRUNC_ROUND,
92 => Opcode::G_INTRINSIC_TRUNC,
93 => Opcode::G_INTRINSIC_ROUND,
94 => Opcode::G_INTRINSIC_LRINT,
95 => Opcode::G_INTRINSIC_LLRINT,
96 => Opcode::G_INTRINSIC_ROUNDEVEN,
97 => Opcode::G_READCYCLECOUNTER,
98 => Opcode::G_READSTEADYCOUNTER,
99 => Opcode::G_LOAD,
100 => Opcode::G_SEXTLOAD,
101 => Opcode::G_ZEXTLOAD,
102 => Opcode::G_INDEXED_LOAD,
103 => Opcode::G_INDEXED_SEXTLOAD,
104 => Opcode::G_INDEXED_ZEXTLOAD,
105 => Opcode::G_STORE,
106 => Opcode::G_INDEXED_STORE,
107 => Opcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS,
108 => Opcode::G_ATOMIC_CMPXCHG,
109 => Opcode::G_ATOMICRMW_XCHG,
110 => Opcode::G_ATOMICRMW_ADD,
111 => Opcode::G_ATOMICRMW_SUB,
112 => Opcode::G_ATOMICRMW_AND,
113 => Opcode::G_ATOMICRMW_NAND,
114 => Opcode::G_ATOMICRMW_OR,
115 => Opcode::G_ATOMICRMW_XOR,
116 => Opcode::G_ATOMICRMW_MAX,
117 => Opcode::G_ATOMICRMW_MIN,
118 => Opcode::G_ATOMICRMW_UMAX,
119 => Opcode::G_ATOMICRMW_UMIN,
120 => Opcode::G_ATOMICRMW_FADD,
121 => Opcode::G_ATOMICRMW_FSUB,
122 => Opcode::G_ATOMICRMW_FMAX,
123 => Opcode::G_ATOMICRMW_FMIN,
124 => Opcode::G_ATOMICRMW_FMAXIMUM,
125 => Opcode::G_ATOMICRMW_FMINIMUM,
126 => Opcode::G_ATOMICRMW_UINC_WRAP,
127 => Opcode::G_ATOMICRMW_UDEC_WRAP,
128 => Opcode::G_ATOMICRMW_USUB_COND,
129 => Opcode::G_ATOMICRMW_USUB_SAT,
130 => Opcode::G_FENCE,
131 => Opcode::G_PREFETCH,
132 => Opcode::G_BRCOND,
133 => Opcode::G_BRINDIRECT,
134 => Opcode::G_INVOKE_REGION_START,
135 => Opcode::G_INTRINSIC,
136 => Opcode::G_INTRINSIC_W_SIDE_EFFECTS,
137 => Opcode::G_INTRINSIC_CONVERGENT,
138 => Opcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS,
139 => Opcode::G_ANYEXT,
140 => Opcode::G_TRUNC,
141 => Opcode::G_TRUNC_SSAT_S,
142 => Opcode::G_TRUNC_SSAT_U,
143 => Opcode::G_TRUNC_USAT_U,
144 => Opcode::G_CONSTANT,
145 => Opcode::G_FCONSTANT,
146 => Opcode::G_VASTART,
147 => Opcode::G_VAARG,
148 => Opcode::G_SEXT,
149 => Opcode::G_SEXT_INREG,
150 => Opcode::G_ZEXT,
151 => Opcode::G_SHL,
152 => Opcode::G_LSHR,
153 => Opcode::G_ASHR,
154 => Opcode::G_FSHL,
155 => Opcode::G_FSHR,
156 => Opcode::G_ROTR,
157 => Opcode::G_ROTL,
158 => Opcode::G_ICMP,
159 => Opcode::G_FCMP,
160 => Opcode::G_SCMP,
161 => Opcode::G_UCMP,
162 => Opcode::G_SELECT,
163 => Opcode::G_UADDO,
164 => Opcode::G_UADDE,
165 => Opcode::G_USUBO,
166 => Opcode::G_USUBE,
167 => Opcode::G_SADDO,
168 => Opcode::G_SADDE,
169 => Opcode::G_SSUBO,
170 => Opcode::G_SSUBE,
171 => Opcode::G_UMULO,
172 => Opcode::G_SMULO,
173 => Opcode::G_UMULH,
174 => Opcode::G_SMULH,
175 => Opcode::G_UADDSAT,
176 => Opcode::G_SADDSAT,
177 => Opcode::G_USUBSAT,
178 => Opcode::G_SSUBSAT,
179 => Opcode::G_USHLSAT,
180 => Opcode::G_SSHLSAT,
181 => Opcode::G_SMULFIX,
182 => Opcode::G_UMULFIX,
183 => Opcode::G_SMULFIXSAT,
184 => Opcode::G_UMULFIXSAT,
185 => Opcode::G_SDIVFIX,
186 => Opcode::G_UDIVFIX,
187 => Opcode::G_SDIVFIXSAT,
188 => Opcode::G_UDIVFIXSAT,
189 => Opcode::G_FADD,
190 => Opcode::G_FSUB,
191 => Opcode::G_FMUL,
192 => Opcode::G_FMA,
193 => Opcode::G_FMAD,
194 => Opcode::G_FDIV,
195 => Opcode::G_FREM,
196 => Opcode::G_FMODF,
197 => Opcode::G_FPOW,
198 => Opcode::G_FPOWI,
199 => Opcode::G_FEXP,
200 => Opcode::G_FEXP2,
201 => Opcode::G_FEXP10,
202 => Opcode::G_FLOG,
203 => Opcode::G_FLOG2,
204 => Opcode::G_FLOG10,
205 => Opcode::G_FLDEXP,
206 => Opcode::G_FFREXP,
207 => Opcode::G_FNEG,
208 => Opcode::G_FPEXT,
209 => Opcode::G_FPTRUNC,
210 => Opcode::G_FPTOSI,
211 => Opcode::G_FPTOUI,
212 => Opcode::G_SITOFP,
213 => Opcode::G_UITOFP,
214 => Opcode::G_FPTOSI_SAT,
215 => Opcode::G_FPTOUI_SAT,
216 => Opcode::G_FABS,
217 => Opcode::G_FCOPYSIGN,
218 => Opcode::G_IS_FPCLASS,
219 => Opcode::G_FCANONICALIZE,
220 => Opcode::G_FMINNUM,
221 => Opcode::G_FMAXNUM,
222 => Opcode::G_FMINNUM_IEEE,
223 => Opcode::G_FMAXNUM_IEEE,
224 => Opcode::G_FMINIMUM,
225 => Opcode::G_FMAXIMUM,
226 => Opcode::G_FMINIMUMNUM,
227 => Opcode::G_FMAXIMUMNUM,
228 => Opcode::G_GET_FPENV,
229 => Opcode::G_SET_FPENV,
230 => Opcode::G_RESET_FPENV,
231 => Opcode::G_GET_FPMODE,
232 => Opcode::G_SET_FPMODE,
233 => Opcode::G_RESET_FPMODE,
234 => Opcode::G_GET_ROUNDING,
235 => Opcode::G_SET_ROUNDING,
236 => Opcode::G_PTR_ADD,
237 => Opcode::G_PTRMASK,
238 => Opcode::G_SMIN,
239 => Opcode::G_SMAX,
240 => Opcode::G_UMIN,
241 => Opcode::G_UMAX,
242 => Opcode::G_ABS,
243 => Opcode::G_LROUND,
244 => Opcode::G_LLROUND,
245 => Opcode::G_BR,
246 => Opcode::G_BRJT,
247 => Opcode::G_VSCALE,
248 => Opcode::G_INSERT_SUBVECTOR,
249 => Opcode::G_EXTRACT_SUBVECTOR,
250 => Opcode::G_INSERT_VECTOR_ELT,
251 => Opcode::G_EXTRACT_VECTOR_ELT,
252 => Opcode::G_SHUFFLE_VECTOR,
253 => Opcode::G_SPLAT_VECTOR,
254 => Opcode::G_STEP_VECTOR,
255 => Opcode::G_VECTOR_COMPRESS,
256 => Opcode::G_CTTZ,
257 => Opcode::G_CTTZ_ZERO_UNDEF,
258 => Opcode::G_CTLZ,
259 => Opcode::G_CTLZ_ZERO_UNDEF,
260 => Opcode::G_CTPOP,
261 => Opcode::G_BSWAP,
262 => Opcode::G_BITREVERSE,
263 => Opcode::G_FCEIL,
264 => Opcode::G_FCOS,
265 => Opcode::G_FSIN,
266 => Opcode::G_FSINCOS,
267 => Opcode::G_FTAN,
268 => Opcode::G_FACOS,
269 => Opcode::G_FASIN,
270 => Opcode::G_FATAN,
271 => Opcode::G_FATAN2,
272 => Opcode::G_FCOSH,
273 => Opcode::G_FSINH,
274 => Opcode::G_FTANH,
275 => Opcode::G_FSQRT,
276 => Opcode::G_FFLOOR,
277 => Opcode::G_FRINT,
278 => Opcode::G_FNEARBYINT,
279 => Opcode::G_ADDRSPACE_CAST,
280 => Opcode::G_BLOCK_ADDR,
281 => Opcode::G_JUMP_TABLE,
282 => Opcode::G_DYN_STACKALLOC,
283 => Opcode::G_STACKSAVE,
284 => Opcode::G_STACKRESTORE,
285 => Opcode::G_STRICT_FADD,
286 => Opcode::G_STRICT_FSUB,
287 => Opcode::G_STRICT_FMUL,
288 => Opcode::G_STRICT_FDIV,
289 => Opcode::G_STRICT_FREM,
290 => Opcode::G_STRICT_FMA,
291 => Opcode::G_STRICT_FSQRT,
292 => Opcode::G_STRICT_FLDEXP,
293 => Opcode::G_READ_REGISTER,
294 => Opcode::G_WRITE_REGISTER,
295 => Opcode::G_MEMCPY,
296 => Opcode::G_MEMCPY_INLINE,
297 => Opcode::G_MEMMOVE,
298 => Opcode::G_MEMSET,
299 => Opcode::G_BZERO,
300 => Opcode::G_TRAP,
301 => Opcode::G_DEBUGTRAP,
302 => Opcode::G_UBSANTRAP,
303 => Opcode::G_VECREDUCE_SEQ_FADD,
304 => Opcode::G_VECREDUCE_SEQ_FMUL,
305 => Opcode::G_VECREDUCE_FADD,
306 => Opcode::G_VECREDUCE_FMUL,
307 => Opcode::G_VECREDUCE_FMAX,
308 => Opcode::G_VECREDUCE_FMIN,
309 => Opcode::G_VECREDUCE_FMAXIMUM,
310 => Opcode::G_VECREDUCE_FMINIMUM,
311 => Opcode::G_VECREDUCE_ADD,
312 => Opcode::G_VECREDUCE_MUL,
313 => Opcode::G_VECREDUCE_AND,
314 => Opcode::G_VECREDUCE_OR,
315 => Opcode::G_VECREDUCE_XOR,
316 => Opcode::G_VECREDUCE_SMAX,
317 => Opcode::G_VECREDUCE_SMIN,
318 => Opcode::G_VECREDUCE_UMAX,
319 => Opcode::G_VECREDUCE_UMIN,
320 => Opcode::G_SBFX,
321 => Opcode::G_UBFX,
322 => Opcode::ADDSri,
323 => Opcode::ADDSrr,
324 => Opcode::ADDSrsi,
325 => Opcode::ADDSrsr,
326 => Opcode::ADJCALLSTACKDOWN,
327 => Opcode::ADJCALLSTACKUP,
328 => Opcode::ASRi,
329 => Opcode::ASRr,
330 => Opcode::ASRs1,
331 => Opcode::B,
332 => Opcode::BCCZi64,
333 => Opcode::BCCi64,
334 => Opcode::BLX_noip,
335 => Opcode::BLX_pred_noip,
336 => Opcode::BL_PUSHLR,
337 => Opcode::BMOVPCB_CALL,
338 => Opcode::BMOVPCRX_CALL,
339 => Opcode::BR_JTadd,
340 => Opcode::BR_JTm_i12,
341 => Opcode::BR_JTm_rs,
342 => Opcode::BR_JTr,
343 => Opcode::BX_CALL,
344 => Opcode::CMP_SWAP_16,
345 => Opcode::CMP_SWAP_32,
346 => Opcode::CMP_SWAP_64,
347 => Opcode::CMP_SWAP_8,
348 => Opcode::CONSTPOOL_ENTRY,
349 => Opcode::COPY_STRUCT_BYVAL_I32,
350 => Opcode::ITasm,
351 => Opcode::Int_eh_sjlj_dispatchsetup,
352 => Opcode::Int_eh_sjlj_longjmp,
353 => Opcode::Int_eh_sjlj_setjmp,
354 => Opcode::Int_eh_sjlj_setjmp_nofp,
355 => Opcode::Int_eh_sjlj_setup_dispatch,
356 => Opcode::JUMPTABLE_ADDRS,
357 => Opcode::JUMPTABLE_INSTS,
358 => Opcode::JUMPTABLE_TBB,
359 => Opcode::JUMPTABLE_TBH,
360 => Opcode::KCFI_CHECK_ARM,
361 => Opcode::KCFI_CHECK_Thumb1,
362 => Opcode::KCFI_CHECK_Thumb2,
363 => Opcode::LDMIA_RET,
364 => Opcode::LDRBT_POST,
365 => Opcode::LDRConstPool,
366 => Opcode::LDRHTii,
367 => Opcode::LDRLIT_ga_abs,
368 => Opcode::LDRLIT_ga_pcrel,
369 => Opcode::LDRLIT_ga_pcrel_ldr,
370 => Opcode::LDRSBTii,
371 => Opcode::LDRSHTii,
372 => Opcode::LDRT_POST,
373 => Opcode::LEApcrel,
374 => Opcode::LEApcrelJT,
375 => Opcode::LOADDUAL,
376 => Opcode::LSLi,
377 => Opcode::LSLr,
378 => Opcode::LSRi,
379 => Opcode::LSRr,
380 => Opcode::LSRs1,
381 => Opcode::MEMCPY,
382 => Opcode::MLAv5,
383 => Opcode::MOVCCi,
384 => Opcode::MOVCCi16,
385 => Opcode::MOVCCi32imm,
386 => Opcode::MOVCCr,
387 => Opcode::MOVCCsi,
388 => Opcode::MOVCCsr,
389 => Opcode::MOVPCRX,
390 => Opcode::MOVTi16_ga_pcrel,
391 => Opcode::MOV_ga_pcrel,
392 => Opcode::MOV_ga_pcrel_ldr,
393 => Opcode::MOVi16_ga_pcrel,
394 => Opcode::MOVi32imm,
395 => Opcode::MQPRCopy,
396 => Opcode::MQQPRLoad,
397 => Opcode::MQQPRStore,
398 => Opcode::MQQQQPRLoad,
399 => Opcode::MQQQQPRStore,
400 => Opcode::MULv5,
401 => Opcode::MVE_MEMCPYLOOPINST,
402 => Opcode::MVE_MEMSETLOOPINST,
403 => Opcode::MVNCCi,
404 => Opcode::PICADD,
405 => Opcode::PICLDR,
406 => Opcode::PICLDRB,
407 => Opcode::PICLDRH,
408 => Opcode::PICLDRSB,
409 => Opcode::PICLDRSH,
410 => Opcode::PICSTR,
411 => Opcode::PICSTRB,
412 => Opcode::PICSTRH,
413 => Opcode::RORi,
414 => Opcode::RORr,
415 => Opcode::RRX,
416 => Opcode::RRXi,
417 => Opcode::RSBSri,
418 => Opcode::RSBSrsi,
419 => Opcode::RSBSrsr,
420 => Opcode::SEH_EpilogEnd,
421 => Opcode::SEH_EpilogStart,
422 => Opcode::SEH_Nop,
423 => Opcode::SEH_Nop_Ret,
424 => Opcode::SEH_PrologEnd,
425 => Opcode::SEH_SaveFRegs,
426 => Opcode::SEH_SaveLR,
427 => Opcode::SEH_SaveRegs,
428 => Opcode::SEH_SaveRegs_Ret,
429 => Opcode::SEH_SaveSP,
430 => Opcode::SEH_StackAlloc,
431 => Opcode::SMLALv5,
432 => Opcode::SMULLv5,
433 => Opcode::SPACE,
434 => Opcode::STOREDUAL,
435 => Opcode::STRBT_POST,
436 => Opcode::STRBi_preidx,
437 => Opcode::STRBr_preidx,
438 => Opcode::STRH_preidx,
439 => Opcode::STRT_POST,
440 => Opcode::STRi_preidx,
441 => Opcode::STRr_preidx,
442 => Opcode::SUBS_PC_LR,
443 => Opcode::SUBSri,
444 => Opcode::SUBSrr,
445 => Opcode::SUBSrsi,
446 => Opcode::SUBSrsr,
447 => Opcode::SpeculationBarrierISBDSBEndBB,
448 => Opcode::SpeculationBarrierSBEndBB,
449 => Opcode::TAILJMPd,
450 => Opcode::TAILJMPr,
451 => Opcode::TAILJMPr4,
452 => Opcode::TCRETURNdi,
453 => Opcode::TCRETURNri,
454 => Opcode::TCRETURNrinotr12,
455 => Opcode::TPsoft,
456 => Opcode::UMLALv5,
457 => Opcode::UMULLv5,
458 => Opcode::VLD1LNdAsm_16,
459 => Opcode::VLD1LNdAsm_32,
460 => Opcode::VLD1LNdAsm_8,
461 => Opcode::VLD1LNdWB_fixed_Asm_16,
462 => Opcode::VLD1LNdWB_fixed_Asm_32,
463 => Opcode::VLD1LNdWB_fixed_Asm_8,
464 => Opcode::VLD1LNdWB_register_Asm_16,
465 => Opcode::VLD1LNdWB_register_Asm_32,
466 => Opcode::VLD1LNdWB_register_Asm_8,
467 => Opcode::VLD2LNdAsm_16,
468 => Opcode::VLD2LNdAsm_32,
469 => Opcode::VLD2LNdAsm_8,
470 => Opcode::VLD2LNdWB_fixed_Asm_16,
471 => Opcode::VLD2LNdWB_fixed_Asm_32,
472 => Opcode::VLD2LNdWB_fixed_Asm_8,
473 => Opcode::VLD2LNdWB_register_Asm_16,
474 => Opcode::VLD2LNdWB_register_Asm_32,
475 => Opcode::VLD2LNdWB_register_Asm_8,
476 => Opcode::VLD2LNqAsm_16,
477 => Opcode::VLD2LNqAsm_32,
478 => Opcode::VLD2LNqWB_fixed_Asm_16,
479 => Opcode::VLD2LNqWB_fixed_Asm_32,
480 => Opcode::VLD2LNqWB_register_Asm_16,
481 => Opcode::VLD2LNqWB_register_Asm_32,
482 => Opcode::VLD3DUPdAsm_16,
483 => Opcode::VLD3DUPdAsm_32,
484 => Opcode::VLD3DUPdAsm_8,
485 => Opcode::VLD3DUPdWB_fixed_Asm_16,
486 => Opcode::VLD3DUPdWB_fixed_Asm_32,
487 => Opcode::VLD3DUPdWB_fixed_Asm_8,
488 => Opcode::VLD3DUPdWB_register_Asm_16,
489 => Opcode::VLD3DUPdWB_register_Asm_32,
490 => Opcode::VLD3DUPdWB_register_Asm_8,
491 => Opcode::VLD3DUPqAsm_16,
492 => Opcode::VLD3DUPqAsm_32,
493 => Opcode::VLD3DUPqAsm_8,
494 => Opcode::VLD3DUPqWB_fixed_Asm_16,
495 => Opcode::VLD3DUPqWB_fixed_Asm_32,
496 => Opcode::VLD3DUPqWB_fixed_Asm_8,
497 => Opcode::VLD3DUPqWB_register_Asm_16,
498 => Opcode::VLD3DUPqWB_register_Asm_32,
499 => Opcode::VLD3DUPqWB_register_Asm_8,
500 => Opcode::VLD3LNdAsm_16,
501 => Opcode::VLD3LNdAsm_32,
502 => Opcode::VLD3LNdAsm_8,
503 => Opcode::VLD3LNdWB_fixed_Asm_16,
504 => Opcode::VLD3LNdWB_fixed_Asm_32,
505 => Opcode::VLD3LNdWB_fixed_Asm_8,
506 => Opcode::VLD3LNdWB_register_Asm_16,
507 => Opcode::VLD3LNdWB_register_Asm_32,
508 => Opcode::VLD3LNdWB_register_Asm_8,
509 => Opcode::VLD3LNqAsm_16,
510 => Opcode::VLD3LNqAsm_32,
511 => Opcode::VLD3LNqWB_fixed_Asm_16,
512 => Opcode::VLD3LNqWB_fixed_Asm_32,
513 => Opcode::VLD3LNqWB_register_Asm_16,
514 => Opcode::VLD3LNqWB_register_Asm_32,
515 => Opcode::VLD3dAsm_16,
516 => Opcode::VLD3dAsm_32,
517 => Opcode::VLD3dAsm_8,
518 => Opcode::VLD3dWB_fixed_Asm_16,
519 => Opcode::VLD3dWB_fixed_Asm_32,
520 => Opcode::VLD3dWB_fixed_Asm_8,
521 => Opcode::VLD3dWB_register_Asm_16,
522 => Opcode::VLD3dWB_register_Asm_32,
523 => Opcode::VLD3dWB_register_Asm_8,
524 => Opcode::VLD3qAsm_16,
525 => Opcode::VLD3qAsm_32,
526 => Opcode::VLD3qAsm_8,
527 => Opcode::VLD3qWB_fixed_Asm_16,
528 => Opcode::VLD3qWB_fixed_Asm_32,
529 => Opcode::VLD3qWB_fixed_Asm_8,
530 => Opcode::VLD3qWB_register_Asm_16,
531 => Opcode::VLD3qWB_register_Asm_32,
532 => Opcode::VLD3qWB_register_Asm_8,
533 => Opcode::VLD4DUPdAsm_16,
534 => Opcode::VLD4DUPdAsm_32,
535 => Opcode::VLD4DUPdAsm_8,
536 => Opcode::VLD4DUPdWB_fixed_Asm_16,
537 => Opcode::VLD4DUPdWB_fixed_Asm_32,
538 => Opcode::VLD4DUPdWB_fixed_Asm_8,
539 => Opcode::VLD4DUPdWB_register_Asm_16,
540 => Opcode::VLD4DUPdWB_register_Asm_32,
541 => Opcode::VLD4DUPdWB_register_Asm_8,
542 => Opcode::VLD4DUPqAsm_16,
543 => Opcode::VLD4DUPqAsm_32,
544 => Opcode::VLD4DUPqAsm_8,
545 => Opcode::VLD4DUPqWB_fixed_Asm_16,
546 => Opcode::VLD4DUPqWB_fixed_Asm_32,
547 => Opcode::VLD4DUPqWB_fixed_Asm_8,
548 => Opcode::VLD4DUPqWB_register_Asm_16,
549 => Opcode::VLD4DUPqWB_register_Asm_32,
550 => Opcode::VLD4DUPqWB_register_Asm_8,
551 => Opcode::VLD4LNdAsm_16,
552 => Opcode::VLD4LNdAsm_32,
553 => Opcode::VLD4LNdAsm_8,
554 => Opcode::VLD4LNdWB_fixed_Asm_16,
555 => Opcode::VLD4LNdWB_fixed_Asm_32,
556 => Opcode::VLD4LNdWB_fixed_Asm_8,
557 => Opcode::VLD4LNdWB_register_Asm_16,
558 => Opcode::VLD4LNdWB_register_Asm_32,
559 => Opcode::VLD4LNdWB_register_Asm_8,
560 => Opcode::VLD4LNqAsm_16,
561 => Opcode::VLD4LNqAsm_32,
562 => Opcode::VLD4LNqWB_fixed_Asm_16,
563 => Opcode::VLD4LNqWB_fixed_Asm_32,
564 => Opcode::VLD4LNqWB_register_Asm_16,
565 => Opcode::VLD4LNqWB_register_Asm_32,
566 => Opcode::VLD4dAsm_16,
567 => Opcode::VLD4dAsm_32,
568 => Opcode::VLD4dAsm_8,
569 => Opcode::VLD4dWB_fixed_Asm_16,
570 => Opcode::VLD4dWB_fixed_Asm_32,
571 => Opcode::VLD4dWB_fixed_Asm_8,
572 => Opcode::VLD4dWB_register_Asm_16,
573 => Opcode::VLD4dWB_register_Asm_32,
574 => Opcode::VLD4dWB_register_Asm_8,
575 => Opcode::VLD4qAsm_16,
576 => Opcode::VLD4qAsm_32,
577 => Opcode::VLD4qAsm_8,
578 => Opcode::VLD4qWB_fixed_Asm_16,
579 => Opcode::VLD4qWB_fixed_Asm_32,
580 => Opcode::VLD4qWB_fixed_Asm_8,
581 => Opcode::VLD4qWB_register_Asm_16,
582 => Opcode::VLD4qWB_register_Asm_32,
583 => Opcode::VLD4qWB_register_Asm_8,
584 => Opcode::VMOVD0,
585 => Opcode::VMOVDcc,
586 => Opcode::VMOVHcc,
587 => Opcode::VMOVQ0,
588 => Opcode::VMOVScc,
589 => Opcode::VST1LNdAsm_16,
590 => Opcode::VST1LNdAsm_32,
591 => Opcode::VST1LNdAsm_8,
592 => Opcode::VST1LNdWB_fixed_Asm_16,
593 => Opcode::VST1LNdWB_fixed_Asm_32,
594 => Opcode::VST1LNdWB_fixed_Asm_8,
595 => Opcode::VST1LNdWB_register_Asm_16,
596 => Opcode::VST1LNdWB_register_Asm_32,
597 => Opcode::VST1LNdWB_register_Asm_8,
598 => Opcode::VST2LNdAsm_16,
599 => Opcode::VST2LNdAsm_32,
600 => Opcode::VST2LNdAsm_8,
601 => Opcode::VST2LNdWB_fixed_Asm_16,
602 => Opcode::VST2LNdWB_fixed_Asm_32,
603 => Opcode::VST2LNdWB_fixed_Asm_8,
604 => Opcode::VST2LNdWB_register_Asm_16,
605 => Opcode::VST2LNdWB_register_Asm_32,
606 => Opcode::VST2LNdWB_register_Asm_8,
607 => Opcode::VST2LNqAsm_16,
608 => Opcode::VST2LNqAsm_32,
609 => Opcode::VST2LNqWB_fixed_Asm_16,
610 => Opcode::VST2LNqWB_fixed_Asm_32,
611 => Opcode::VST2LNqWB_register_Asm_16,
612 => Opcode::VST2LNqWB_register_Asm_32,
613 => Opcode::VST3LNdAsm_16,
614 => Opcode::VST3LNdAsm_32,
615 => Opcode::VST3LNdAsm_8,
616 => Opcode::VST3LNdWB_fixed_Asm_16,
617 => Opcode::VST3LNdWB_fixed_Asm_32,
618 => Opcode::VST3LNdWB_fixed_Asm_8,
619 => Opcode::VST3LNdWB_register_Asm_16,
620 => Opcode::VST3LNdWB_register_Asm_32,
621 => Opcode::VST3LNdWB_register_Asm_8,
622 => Opcode::VST3LNqAsm_16,
623 => Opcode::VST3LNqAsm_32,
624 => Opcode::VST3LNqWB_fixed_Asm_16,
625 => Opcode::VST3LNqWB_fixed_Asm_32,
626 => Opcode::VST3LNqWB_register_Asm_16,
627 => Opcode::VST3LNqWB_register_Asm_32,
628 => Opcode::VST3dAsm_16,
629 => Opcode::VST3dAsm_32,
630 => Opcode::VST3dAsm_8,
631 => Opcode::VST3dWB_fixed_Asm_16,
632 => Opcode::VST3dWB_fixed_Asm_32,
633 => Opcode::VST3dWB_fixed_Asm_8,
634 => Opcode::VST3dWB_register_Asm_16,
635 => Opcode::VST3dWB_register_Asm_32,
636 => Opcode::VST3dWB_register_Asm_8,
637 => Opcode::VST3qAsm_16,
638 => Opcode::VST3qAsm_32,
639 => Opcode::VST3qAsm_8,
640 => Opcode::VST3qWB_fixed_Asm_16,
641 => Opcode::VST3qWB_fixed_Asm_32,
642 => Opcode::VST3qWB_fixed_Asm_8,
643 => Opcode::VST3qWB_register_Asm_16,
644 => Opcode::VST3qWB_register_Asm_32,
645 => Opcode::VST3qWB_register_Asm_8,
646 => Opcode::VST4LNdAsm_16,
647 => Opcode::VST4LNdAsm_32,
648 => Opcode::VST4LNdAsm_8,
649 => Opcode::VST4LNdWB_fixed_Asm_16,
650 => Opcode::VST4LNdWB_fixed_Asm_32,
651 => Opcode::VST4LNdWB_fixed_Asm_8,
652 => Opcode::VST4LNdWB_register_Asm_16,
653 => Opcode::VST4LNdWB_register_Asm_32,
654 => Opcode::VST4LNdWB_register_Asm_8,
655 => Opcode::VST4LNqAsm_16,
656 => Opcode::VST4LNqAsm_32,
657 => Opcode::VST4LNqWB_fixed_Asm_16,
658 => Opcode::VST4LNqWB_fixed_Asm_32,
659 => Opcode::VST4LNqWB_register_Asm_16,
660 => Opcode::VST4LNqWB_register_Asm_32,
661 => Opcode::VST4dAsm_16,
662 => Opcode::VST4dAsm_32,
663 => Opcode::VST4dAsm_8,
664 => Opcode::VST4dWB_fixed_Asm_16,
665 => Opcode::VST4dWB_fixed_Asm_32,
666 => Opcode::VST4dWB_fixed_Asm_8,
667 => Opcode::VST4dWB_register_Asm_16,
668 => Opcode::VST4dWB_register_Asm_32,
669 => Opcode::VST4dWB_register_Asm_8,
670 => Opcode::VST4qAsm_16,
671 => Opcode::VST4qAsm_32,
672 => Opcode::VST4qAsm_8,
673 => Opcode::VST4qWB_fixed_Asm_16,
674 => Opcode::VST4qWB_fixed_Asm_32,
675 => Opcode::VST4qWB_fixed_Asm_8,
676 => Opcode::VST4qWB_register_Asm_16,
677 => Opcode::VST4qWB_register_Asm_32,
678 => Opcode::VST4qWB_register_Asm_8,
679 => Opcode::WIN__CHKSTK,
680 => Opcode::WIN__DBZCHK,
681 => Opcode::t2ADDSri,
682 => Opcode::t2ADDSrr,
683 => Opcode::t2ADDSrs,
684 => Opcode::t2BF_LabelPseudo,
685 => Opcode::t2BR_JT,
686 => Opcode::t2CALL_BTI,
687 => Opcode::t2DoLoopStart,
688 => Opcode::t2DoLoopStartTP,
689 => Opcode::t2LDMIA_RET,
690 => Opcode::t2LDRB_OFFSET_imm,
691 => Opcode::t2LDRB_POST_imm,
692 => Opcode::t2LDRB_PRE_imm,
693 => Opcode::t2LDRBpcrel,
694 => Opcode::t2LDRConstPool,
695 => Opcode::t2LDRH_OFFSET_imm,
696 => Opcode::t2LDRH_POST_imm,
697 => Opcode::t2LDRH_PRE_imm,
698 => Opcode::t2LDRHpcrel,
699 => Opcode::t2LDRLIT_ga_pcrel,
700 => Opcode::t2LDRSB_OFFSET_imm,
701 => Opcode::t2LDRSB_POST_imm,
702 => Opcode::t2LDRSB_PRE_imm,
703 => Opcode::t2LDRSBpcrel,
704 => Opcode::t2LDRSH_OFFSET_imm,
705 => Opcode::t2LDRSH_POST_imm,
706 => Opcode::t2LDRSH_PRE_imm,
707 => Opcode::t2LDRSHpcrel,
708 => Opcode::t2LDR_POST_imm,
709 => Opcode::t2LDR_PRE_imm,
710 => Opcode::t2LDRpci_pic,
711 => Opcode::t2LDRpcrel,
712 => Opcode::t2LEApcrel,
713 => Opcode::t2LEApcrelJT,
714 => Opcode::t2LoopDec,
715 => Opcode::t2LoopEnd,
716 => Opcode::t2LoopEndDec,
717 => Opcode::t2MOVCCasr,
718 => Opcode::t2MOVCCi,
719 => Opcode::t2MOVCCi16,
720 => Opcode::t2MOVCCi32imm,
721 => Opcode::t2MOVCClsl,
722 => Opcode::t2MOVCClsr,
723 => Opcode::t2MOVCCr,
724 => Opcode::t2MOVCCror,
725 => Opcode::t2MOVSsi,
726 => Opcode::t2MOVSsr,
727 => Opcode::t2MOVTi16_ga_pcrel,
728 => Opcode::t2MOV_ga_pcrel,
729 => Opcode::t2MOVi16_ga_pcrel,
730 => Opcode::t2MOVi32imm,
731 => Opcode::t2MOVsi,
732 => Opcode::t2MOVsr,
733 => Opcode::t2MVNCCi,
734 => Opcode::t2RSBSri,
735 => Opcode::t2RSBSrs,
736 => Opcode::t2STRB_OFFSET_imm,
737 => Opcode::t2STRB_POST_imm,
738 => Opcode::t2STRB_PRE_imm,
739 => Opcode::t2STRB_preidx,
740 => Opcode::t2STRH_OFFSET_imm,
741 => Opcode::t2STRH_POST_imm,
742 => Opcode::t2STRH_PRE_imm,
743 => Opcode::t2STRH_preidx,
744 => Opcode::t2STR_POST_imm,
745 => Opcode::t2STR_PRE_imm,
746 => Opcode::t2STR_preidx,
747 => Opcode::t2SUBSri,
748 => Opcode::t2SUBSrr,
749 => Opcode::t2SUBSrs,
750 => Opcode::t2SpeculationBarrierISBDSBEndBB,
751 => Opcode::t2SpeculationBarrierSBEndBB,
752 => Opcode::t2TBB_JT,
753 => Opcode::t2TBH_JT,
754 => Opcode::t2WhileLoopSetup,
755 => Opcode::t2WhileLoopStart,
756 => Opcode::t2WhileLoopStartLR,
757 => Opcode::t2WhileLoopStartTP,
758 => Opcode::tADCS,
759 => Opcode::tADDSi3,
760 => Opcode::tADDSi8,
761 => Opcode::tADDSrr,
762 => Opcode::tADDframe,
763 => Opcode::tADJCALLSTACKDOWN,
764 => Opcode::tADJCALLSTACKUP,
765 => Opcode::tBLXNS_CALL,
766 => Opcode::tBLXr_noip,
767 => Opcode::tBL_PUSHLR,
768 => Opcode::tBRIND,
769 => Opcode::tBR_JTr,
770 => Opcode::tBXNS_RET,
771 => Opcode::tBX_CALL,
772 => Opcode::tBX_RET,
773 => Opcode::tBX_RET_vararg,
774 => Opcode::tBfar,
775 => Opcode::tCMP_SWAP_16,
776 => Opcode::tCMP_SWAP_32,
777 => Opcode::tCMP_SWAP_8,
778 => Opcode::tLDMIA_UPD,
779 => Opcode::tLDRConstPool,
780 => Opcode::tLDRLIT_ga_abs,
781 => Opcode::tLDRLIT_ga_pcrel,
782 => Opcode::tLDR_postidx,
783 => Opcode::tLDRpci_pic,
784 => Opcode::tLEApcrel,
785 => Opcode::tLEApcrelJT,
786 => Opcode::tLSLSri,
787 => Opcode::tMOVCCr_pseudo,
788 => Opcode::tMOVi32imm,
789 => Opcode::tPOP_RET,
790 => Opcode::tRSBS,
791 => Opcode::tSBCS,
792 => Opcode::tSUBSi3,
793 => Opcode::tSUBSi8,
794 => Opcode::tSUBSrr,
795 => Opcode::tTAILJMPd,
796 => Opcode::tTAILJMPdND,
797 => Opcode::tTAILJMPr,
798 => Opcode::tTBB_JT,
799 => Opcode::tTBH_JT,
800 => Opcode::tTPsoft,
801 => Opcode::ADCri,
802 => Opcode::ADCrr,
803 => Opcode::ADCrsi,
804 => Opcode::ADCrsr,
805 => Opcode::ADDri,
806 => Opcode::ADDrr,
807 => Opcode::ADDrsi,
808 => Opcode::ADDrsr,
809 => Opcode::ADR,
810 => Opcode::AESD,
811 => Opcode::AESE,
812 => Opcode::AESIMC,
813 => Opcode::AESMC,
814 => Opcode::ANDri,
815 => Opcode::ANDrr,
816 => Opcode::ANDrsi,
817 => Opcode::ANDrsr,
818 => Opcode::BF16VDOTI_VDOTD,
819 => Opcode::BF16VDOTI_VDOTQ,
820 => Opcode::BF16VDOTS_VDOTD,
821 => Opcode::BF16VDOTS_VDOTQ,
822 => Opcode::BF16_VCVT,
823 => Opcode::BF16_VCVTB,
824 => Opcode::BF16_VCVTT,
825 => Opcode::BFC,
826 => Opcode::BFI,
827 => Opcode::BICri,
828 => Opcode::BICrr,
829 => Opcode::BICrsi,
830 => Opcode::BICrsr,
831 => Opcode::BKPT,
832 => Opcode::BL,
833 => Opcode::BLX,
834 => Opcode::BLX_pred,
835 => Opcode::BLXi,
836 => Opcode::BL_pred,
837 => Opcode::BX,
838 => Opcode::BXJ,
839 => Opcode::BX_RET,
840 => Opcode::BX_pred,
841 => Opcode::Bcc,
842 => Opcode::CDE_CX1,
843 => Opcode::CDE_CX1A,
844 => Opcode::CDE_CX1D,
845 => Opcode::CDE_CX1DA,
846 => Opcode::CDE_CX2,
847 => Opcode::CDE_CX2A,
848 => Opcode::CDE_CX2D,
849 => Opcode::CDE_CX2DA,
850 => Opcode::CDE_CX3,
851 => Opcode::CDE_CX3A,
852 => Opcode::CDE_CX3D,
853 => Opcode::CDE_CX3DA,
854 => Opcode::CDE_VCX1A_fpdp,
855 => Opcode::CDE_VCX1A_fpsp,
856 => Opcode::CDE_VCX1A_vec,
857 => Opcode::CDE_VCX1_fpdp,
858 => Opcode::CDE_VCX1_fpsp,
859 => Opcode::CDE_VCX1_vec,
860 => Opcode::CDE_VCX2A_fpdp,
861 => Opcode::CDE_VCX2A_fpsp,
862 => Opcode::CDE_VCX2A_vec,
863 => Opcode::CDE_VCX2_fpdp,
864 => Opcode::CDE_VCX2_fpsp,
865 => Opcode::CDE_VCX2_vec,
866 => Opcode::CDE_VCX3A_fpdp,
867 => Opcode::CDE_VCX3A_fpsp,
868 => Opcode::CDE_VCX3A_vec,
869 => Opcode::CDE_VCX3_fpdp,
870 => Opcode::CDE_VCX3_fpsp,
871 => Opcode::CDE_VCX3_vec,
872 => Opcode::CDP,
873 => Opcode::CDP2,
874 => Opcode::CLREX,
875 => Opcode::CLZ,
876 => Opcode::CMNri,
877 => Opcode::CMNzrr,
878 => Opcode::CMNzrsi,
879 => Opcode::CMNzrsr,
880 => Opcode::CMPri,
881 => Opcode::CMPrr,
882 => Opcode::CMPrsi,
883 => Opcode::CMPrsr,
884 => Opcode::CPS1p,
885 => Opcode::CPS2p,
886 => Opcode::CPS3p,
887 => Opcode::CRC32B,
888 => Opcode::CRC32CB,
889 => Opcode::CRC32CH,
890 => Opcode::CRC32CW,
891 => Opcode::CRC32H,
892 => Opcode::CRC32W,
893 => Opcode::DBG,
894 => Opcode::DMB,
895 => Opcode::DSB,
896 => Opcode::EORri,
897 => Opcode::EORrr,
898 => Opcode::EORrsi,
899 => Opcode::EORrsr,
900 => Opcode::ERET,
901 => Opcode::FCONSTD,
902 => Opcode::FCONSTH,
903 => Opcode::FCONSTS,
904 => Opcode::FLDMXDB_UPD,
905 => Opcode::FLDMXIA,
906 => Opcode::FLDMXIA_UPD,
907 => Opcode::FMSTAT,
908 => Opcode::FSTMXDB_UPD,
909 => Opcode::FSTMXIA,
910 => Opcode::FSTMXIA_UPD,
911 => Opcode::HINT,
912 => Opcode::HLT,
913 => Opcode::HVC,
914 => Opcode::ISB,
915 => Opcode::LDA,
916 => Opcode::LDAB,
917 => Opcode::LDAEX,
918 => Opcode::LDAEXB,
919 => Opcode::LDAEXD,
920 => Opcode::LDAEXH,
921 => Opcode::LDAH,
922 => Opcode::LDC2L_OFFSET,
923 => Opcode::LDC2L_OPTION,
924 => Opcode::LDC2L_POST,
925 => Opcode::LDC2L_PRE,
926 => Opcode::LDC2_OFFSET,
927 => Opcode::LDC2_OPTION,
928 => Opcode::LDC2_POST,
929 => Opcode::LDC2_PRE,
930 => Opcode::LDCL_OFFSET,
931 => Opcode::LDCL_OPTION,
932 => Opcode::LDCL_POST,
933 => Opcode::LDCL_PRE,
934 => Opcode::LDC_OFFSET,
935 => Opcode::LDC_OPTION,
936 => Opcode::LDC_POST,
937 => Opcode::LDC_PRE,
938 => Opcode::LDMDA,
939 => Opcode::LDMDA_UPD,
940 => Opcode::LDMDB,
941 => Opcode::LDMDB_UPD,
942 => Opcode::LDMIA,
943 => Opcode::LDMIA_UPD,
944 => Opcode::LDMIB,
945 => Opcode::LDMIB_UPD,
946 => Opcode::LDRBT_POST_IMM,
947 => Opcode::LDRBT_POST_REG,
948 => Opcode::LDRB_POST_IMM,
949 => Opcode::LDRB_POST_REG,
950 => Opcode::LDRB_PRE_IMM,
951 => Opcode::LDRB_PRE_REG,
952 => Opcode::LDRBi12,
953 => Opcode::LDRBrs,
954 => Opcode::LDRD,
955 => Opcode::LDRD_POST,
956 => Opcode::LDRD_PRE,
957 => Opcode::LDREX,
958 => Opcode::LDREXB,
959 => Opcode::LDREXD,
960 => Opcode::LDREXH,
961 => Opcode::LDRH,
962 => Opcode::LDRHTi,
963 => Opcode::LDRHTr,
964 => Opcode::LDRH_POST,
965 => Opcode::LDRH_PRE,
966 => Opcode::LDRSB,
967 => Opcode::LDRSBTi,
968 => Opcode::LDRSBTr,
969 => Opcode::LDRSB_POST,
970 => Opcode::LDRSB_PRE,
971 => Opcode::LDRSH,
972 => Opcode::LDRSHTi,
973 => Opcode::LDRSHTr,
974 => Opcode::LDRSH_POST,
975 => Opcode::LDRSH_PRE,
976 => Opcode::LDRT_POST_IMM,
977 => Opcode::LDRT_POST_REG,
978 => Opcode::LDR_POST_IMM,
979 => Opcode::LDR_POST_REG,
980 => Opcode::LDR_PRE_IMM,
981 => Opcode::LDR_PRE_REG,
982 => Opcode::LDRcp,
983 => Opcode::LDRi12,
984 => Opcode::LDRrs,
985 => Opcode::MCR,
986 => Opcode::MCR2,
987 => Opcode::MCRR,
988 => Opcode::MCRR2,
989 => Opcode::MLA,
990 => Opcode::MLS,
991 => Opcode::MOVPCLR,
992 => Opcode::MOVTi16,
993 => Opcode::MOVi,
994 => Opcode::MOVi16,
995 => Opcode::MOVr,
996 => Opcode::MOVr_TC,
997 => Opcode::MOVsi,
998 => Opcode::MOVsr,
999 => Opcode::MRC,
1000 => Opcode::MRC2,
1001 => Opcode::MRRC,
1002 => Opcode::MRRC2,
1003 => Opcode::MRS,
1004 => Opcode::MRSbanked,
1005 => Opcode::MRSsys,
1006 => Opcode::MSR,
1007 => Opcode::MSRbanked,
1008 => Opcode::MSRi,
1009 => Opcode::MUL,
1010 => Opcode::MVE_ASRLi,
1011 => Opcode::MVE_ASRLr,
1012 => Opcode::MVE_DLSTP_16,
1013 => Opcode::MVE_DLSTP_32,
1014 => Opcode::MVE_DLSTP_64,
1015 => Opcode::MVE_DLSTP_8,
1016 => Opcode::MVE_LCTP,
1017 => Opcode::MVE_LETP,
1018 => Opcode::MVE_LSLLi,
1019 => Opcode::MVE_LSLLr,
1020 => Opcode::MVE_LSRL,
1021 => Opcode::MVE_SQRSHR,
1022 => Opcode::MVE_SQRSHRL,
1023 => Opcode::MVE_SQSHL,
1024 => Opcode::MVE_SQSHLL,
1025 => Opcode::MVE_SRSHR,
1026 => Opcode::MVE_SRSHRL,
1027 => Opcode::MVE_UQRSHL,
1028 => Opcode::MVE_UQRSHLL,
1029 => Opcode::MVE_UQSHL,
1030 => Opcode::MVE_UQSHLL,
1031 => Opcode::MVE_URSHR,
1032 => Opcode::MVE_URSHRL,
1033 => Opcode::MVE_VABAVs16,
1034 => Opcode::MVE_VABAVs32,
1035 => Opcode::MVE_VABAVs8,
1036 => Opcode::MVE_VABAVu16,
1037 => Opcode::MVE_VABAVu32,
1038 => Opcode::MVE_VABAVu8,
1039 => Opcode::MVE_VABDf16,
1040 => Opcode::MVE_VABDf32,
1041 => Opcode::MVE_VABDs16,
1042 => Opcode::MVE_VABDs32,
1043 => Opcode::MVE_VABDs8,
1044 => Opcode::MVE_VABDu16,
1045 => Opcode::MVE_VABDu32,
1046 => Opcode::MVE_VABDu8,
1047 => Opcode::MVE_VABSf16,
1048 => Opcode::MVE_VABSf32,
1049 => Opcode::MVE_VABSs16,
1050 => Opcode::MVE_VABSs32,
1051 => Opcode::MVE_VABSs8,
1052 => Opcode::MVE_VADC,
1053 => Opcode::MVE_VADCI,
1054 => Opcode::MVE_VADDLVs32acc,
1055 => Opcode::MVE_VADDLVs32no_acc,
1056 => Opcode::MVE_VADDLVu32acc,
1057 => Opcode::MVE_VADDLVu32no_acc,
1058 => Opcode::MVE_VADDVs16acc,
1059 => Opcode::MVE_VADDVs16no_acc,
1060 => Opcode::MVE_VADDVs32acc,
1061 => Opcode::MVE_VADDVs32no_acc,
1062 => Opcode::MVE_VADDVs8acc,
1063 => Opcode::MVE_VADDVs8no_acc,
1064 => Opcode::MVE_VADDVu16acc,
1065 => Opcode::MVE_VADDVu16no_acc,
1066 => Opcode::MVE_VADDVu32acc,
1067 => Opcode::MVE_VADDVu32no_acc,
1068 => Opcode::MVE_VADDVu8acc,
1069 => Opcode::MVE_VADDVu8no_acc,
1070 => Opcode::MVE_VADD_qr_f16,
1071 => Opcode::MVE_VADD_qr_f32,
1072 => Opcode::MVE_VADD_qr_i16,
1073 => Opcode::MVE_VADD_qr_i32,
1074 => Opcode::MVE_VADD_qr_i8,
1075 => Opcode::MVE_VADDf16,
1076 => Opcode::MVE_VADDf32,
1077 => Opcode::MVE_VADDi16,
1078 => Opcode::MVE_VADDi32,
1079 => Opcode::MVE_VADDi8,
1080 => Opcode::MVE_VAND,
1081 => Opcode::MVE_VBIC,
1082 => Opcode::MVE_VBICimmi16,
1083 => Opcode::MVE_VBICimmi32,
1084 => Opcode::MVE_VBRSR16,
1085 => Opcode::MVE_VBRSR32,
1086 => Opcode::MVE_VBRSR8,
1087 => Opcode::MVE_VCADDf16,
1088 => Opcode::MVE_VCADDf32,
1089 => Opcode::MVE_VCADDi16,
1090 => Opcode::MVE_VCADDi32,
1091 => Opcode::MVE_VCADDi8,
1092 => Opcode::MVE_VCLSs16,
1093 => Opcode::MVE_VCLSs32,
1094 => Opcode::MVE_VCLSs8,
1095 => Opcode::MVE_VCLZs16,
1096 => Opcode::MVE_VCLZs32,
1097 => Opcode::MVE_VCLZs8,
1098 => Opcode::MVE_VCMLAf16,
1099 => Opcode::MVE_VCMLAf32,
1100 => Opcode::MVE_VCMPf16,
1101 => Opcode::MVE_VCMPf16r,
1102 => Opcode::MVE_VCMPf32,
1103 => Opcode::MVE_VCMPf32r,
1104 => Opcode::MVE_VCMPi16,
1105 => Opcode::MVE_VCMPi16r,
1106 => Opcode::MVE_VCMPi32,
1107 => Opcode::MVE_VCMPi32r,
1108 => Opcode::MVE_VCMPi8,
1109 => Opcode::MVE_VCMPi8r,
1110 => Opcode::MVE_VCMPs16,
1111 => Opcode::MVE_VCMPs16r,
1112 => Opcode::MVE_VCMPs32,
1113 => Opcode::MVE_VCMPs32r,
1114 => Opcode::MVE_VCMPs8,
1115 => Opcode::MVE_VCMPs8r,
1116 => Opcode::MVE_VCMPu16,
1117 => Opcode::MVE_VCMPu16r,
1118 => Opcode::MVE_VCMPu32,
1119 => Opcode::MVE_VCMPu32r,
1120 => Opcode::MVE_VCMPu8,
1121 => Opcode::MVE_VCMPu8r,
1122 => Opcode::MVE_VCMULf16,
1123 => Opcode::MVE_VCMULf32,
1124 => Opcode::MVE_VCTP16,
1125 => Opcode::MVE_VCTP32,
1126 => Opcode::MVE_VCTP64,
1127 => Opcode::MVE_VCTP8,
1128 => Opcode::MVE_VCVTf16f32bh,
1129 => Opcode::MVE_VCVTf16f32th,
1130 => Opcode::MVE_VCVTf16s16_fix,
1131 => Opcode::MVE_VCVTf16s16n,
1132 => Opcode::MVE_VCVTf16u16_fix,
1133 => Opcode::MVE_VCVTf16u16n,
1134 => Opcode::MVE_VCVTf32f16bh,
1135 => Opcode::MVE_VCVTf32f16th,
1136 => Opcode::MVE_VCVTf32s32_fix,
1137 => Opcode::MVE_VCVTf32s32n,
1138 => Opcode::MVE_VCVTf32u32_fix,
1139 => Opcode::MVE_VCVTf32u32n,
1140 => Opcode::MVE_VCVTs16f16_fix,
1141 => Opcode::MVE_VCVTs16f16a,
1142 => Opcode::MVE_VCVTs16f16m,
1143 => Opcode::MVE_VCVTs16f16n,
1144 => Opcode::MVE_VCVTs16f16p,
1145 => Opcode::MVE_VCVTs16f16z,
1146 => Opcode::MVE_VCVTs32f32_fix,
1147 => Opcode::MVE_VCVTs32f32a,
1148 => Opcode::MVE_VCVTs32f32m,
1149 => Opcode::MVE_VCVTs32f32n,
1150 => Opcode::MVE_VCVTs32f32p,
1151 => Opcode::MVE_VCVTs32f32z,
1152 => Opcode::MVE_VCVTu16f16_fix,
1153 => Opcode::MVE_VCVTu16f16a,
1154 => Opcode::MVE_VCVTu16f16m,
1155 => Opcode::MVE_VCVTu16f16n,
1156 => Opcode::MVE_VCVTu16f16p,
1157 => Opcode::MVE_VCVTu16f16z,
1158 => Opcode::MVE_VCVTu32f32_fix,
1159 => Opcode::MVE_VCVTu32f32a,
1160 => Opcode::MVE_VCVTu32f32m,
1161 => Opcode::MVE_VCVTu32f32n,
1162 => Opcode::MVE_VCVTu32f32p,
1163 => Opcode::MVE_VCVTu32f32z,
1164 => Opcode::MVE_VDDUPu16,
1165 => Opcode::MVE_VDDUPu32,
1166 => Opcode::MVE_VDDUPu8,
1167 => Opcode::MVE_VDUP16,
1168 => Opcode::MVE_VDUP32,
1169 => Opcode::MVE_VDUP8,
1170 => Opcode::MVE_VDWDUPu16,
1171 => Opcode::MVE_VDWDUPu32,
1172 => Opcode::MVE_VDWDUPu8,
1173 => Opcode::MVE_VEOR,
1174 => Opcode::MVE_VFMA_qr_Sf16,
1175 => Opcode::MVE_VFMA_qr_Sf32,
1176 => Opcode::MVE_VFMA_qr_f16,
1177 => Opcode::MVE_VFMA_qr_f32,
1178 => Opcode::MVE_VFMAf16,
1179 => Opcode::MVE_VFMAf32,
1180 => Opcode::MVE_VFMSf16,
1181 => Opcode::MVE_VFMSf32,
1182 => Opcode::MVE_VHADD_qr_s16,
1183 => Opcode::MVE_VHADD_qr_s32,
1184 => Opcode::MVE_VHADD_qr_s8,
1185 => Opcode::MVE_VHADD_qr_u16,
1186 => Opcode::MVE_VHADD_qr_u32,
1187 => Opcode::MVE_VHADD_qr_u8,
1188 => Opcode::MVE_VHADDs16,
1189 => Opcode::MVE_VHADDs32,
1190 => Opcode::MVE_VHADDs8,
1191 => Opcode::MVE_VHADDu16,
1192 => Opcode::MVE_VHADDu32,
1193 => Opcode::MVE_VHADDu8,
1194 => Opcode::MVE_VHCADDs16,
1195 => Opcode::MVE_VHCADDs32,
1196 => Opcode::MVE_VHCADDs8,
1197 => Opcode::MVE_VHSUB_qr_s16,
1198 => Opcode::MVE_VHSUB_qr_s32,
1199 => Opcode::MVE_VHSUB_qr_s8,
1200 => Opcode::MVE_VHSUB_qr_u16,
1201 => Opcode::MVE_VHSUB_qr_u32,
1202 => Opcode::MVE_VHSUB_qr_u8,
1203 => Opcode::MVE_VHSUBs16,
1204 => Opcode::MVE_VHSUBs32,
1205 => Opcode::MVE_VHSUBs8,
1206 => Opcode::MVE_VHSUBu16,
1207 => Opcode::MVE_VHSUBu32,
1208 => Opcode::MVE_VHSUBu8,
1209 => Opcode::MVE_VIDUPu16,
1210 => Opcode::MVE_VIDUPu32,
1211 => Opcode::MVE_VIDUPu8,
1212 => Opcode::MVE_VIWDUPu16,
1213 => Opcode::MVE_VIWDUPu32,
1214 => Opcode::MVE_VIWDUPu8,
1215 => Opcode::MVE_VLD20_16,
1216 => Opcode::MVE_VLD20_16_wb,
1217 => Opcode::MVE_VLD20_32,
1218 => Opcode::MVE_VLD20_32_wb,
1219 => Opcode::MVE_VLD20_8,
1220 => Opcode::MVE_VLD20_8_wb,
1221 => Opcode::MVE_VLD21_16,
1222 => Opcode::MVE_VLD21_16_wb,
1223 => Opcode::MVE_VLD21_32,
1224 => Opcode::MVE_VLD21_32_wb,
1225 => Opcode::MVE_VLD21_8,
1226 => Opcode::MVE_VLD21_8_wb,
1227 => Opcode::MVE_VLD40_16,
1228 => Opcode::MVE_VLD40_16_wb,
1229 => Opcode::MVE_VLD40_32,
1230 => Opcode::MVE_VLD40_32_wb,
1231 => Opcode::MVE_VLD40_8,
1232 => Opcode::MVE_VLD40_8_wb,
1233 => Opcode::MVE_VLD41_16,
1234 => Opcode::MVE_VLD41_16_wb,
1235 => Opcode::MVE_VLD41_32,
1236 => Opcode::MVE_VLD41_32_wb,
1237 => Opcode::MVE_VLD41_8,
1238 => Opcode::MVE_VLD41_8_wb,
1239 => Opcode::MVE_VLD42_16,
1240 => Opcode::MVE_VLD42_16_wb,
1241 => Opcode::MVE_VLD42_32,
1242 => Opcode::MVE_VLD42_32_wb,
1243 => Opcode::MVE_VLD42_8,
1244 => Opcode::MVE_VLD42_8_wb,
1245 => Opcode::MVE_VLD43_16,
1246 => Opcode::MVE_VLD43_16_wb,
1247 => Opcode::MVE_VLD43_32,
1248 => Opcode::MVE_VLD43_32_wb,
1249 => Opcode::MVE_VLD43_8,
1250 => Opcode::MVE_VLD43_8_wb,
1251 => Opcode::MVE_VLDRBS16,
1252 => Opcode::MVE_VLDRBS16_post,
1253 => Opcode::MVE_VLDRBS16_pre,
1254 => Opcode::MVE_VLDRBS16_rq,
1255 => Opcode::MVE_VLDRBS32,
1256 => Opcode::MVE_VLDRBS32_post,
1257 => Opcode::MVE_VLDRBS32_pre,
1258 => Opcode::MVE_VLDRBS32_rq,
1259 => Opcode::MVE_VLDRBU16,
1260 => Opcode::MVE_VLDRBU16_post,
1261 => Opcode::MVE_VLDRBU16_pre,
1262 => Opcode::MVE_VLDRBU16_rq,
1263 => Opcode::MVE_VLDRBU32,
1264 => Opcode::MVE_VLDRBU32_post,
1265 => Opcode::MVE_VLDRBU32_pre,
1266 => Opcode::MVE_VLDRBU32_rq,
1267 => Opcode::MVE_VLDRBU8,
1268 => Opcode::MVE_VLDRBU8_post,
1269 => Opcode::MVE_VLDRBU8_pre,
1270 => Opcode::MVE_VLDRBU8_rq,
1271 => Opcode::MVE_VLDRDU64_qi,
1272 => Opcode::MVE_VLDRDU64_qi_pre,
1273 => Opcode::MVE_VLDRDU64_rq,
1274 => Opcode::MVE_VLDRDU64_rq_u,
1275 => Opcode::MVE_VLDRHS32,
1276 => Opcode::MVE_VLDRHS32_post,
1277 => Opcode::MVE_VLDRHS32_pre,
1278 => Opcode::MVE_VLDRHS32_rq,
1279 => Opcode::MVE_VLDRHS32_rq_u,
1280 => Opcode::MVE_VLDRHU16,
1281 => Opcode::MVE_VLDRHU16_post,
1282 => Opcode::MVE_VLDRHU16_pre,
1283 => Opcode::MVE_VLDRHU16_rq,
1284 => Opcode::MVE_VLDRHU16_rq_u,
1285 => Opcode::MVE_VLDRHU32,
1286 => Opcode::MVE_VLDRHU32_post,
1287 => Opcode::MVE_VLDRHU32_pre,
1288 => Opcode::MVE_VLDRHU32_rq,
1289 => Opcode::MVE_VLDRHU32_rq_u,
1290 => Opcode::MVE_VLDRWU32,
1291 => Opcode::MVE_VLDRWU32_post,
1292 => Opcode::MVE_VLDRWU32_pre,
1293 => Opcode::MVE_VLDRWU32_qi,
1294 => Opcode::MVE_VLDRWU32_qi_pre,
1295 => Opcode::MVE_VLDRWU32_rq,
1296 => Opcode::MVE_VLDRWU32_rq_u,
1297 => Opcode::MVE_VMAXAVs16,
1298 => Opcode::MVE_VMAXAVs32,
1299 => Opcode::MVE_VMAXAVs8,
1300 => Opcode::MVE_VMAXAs16,
1301 => Opcode::MVE_VMAXAs32,
1302 => Opcode::MVE_VMAXAs8,
1303 => Opcode::MVE_VMAXNMAVf16,
1304 => Opcode::MVE_VMAXNMAVf32,
1305 => Opcode::MVE_VMAXNMAf16,
1306 => Opcode::MVE_VMAXNMAf32,
1307 => Opcode::MVE_VMAXNMVf16,
1308 => Opcode::MVE_VMAXNMVf32,
1309 => Opcode::MVE_VMAXNMf16,
1310 => Opcode::MVE_VMAXNMf32,
1311 => Opcode::MVE_VMAXVs16,
1312 => Opcode::MVE_VMAXVs32,
1313 => Opcode::MVE_VMAXVs8,
1314 => Opcode::MVE_VMAXVu16,
1315 => Opcode::MVE_VMAXVu32,
1316 => Opcode::MVE_VMAXVu8,
1317 => Opcode::MVE_VMAXs16,
1318 => Opcode::MVE_VMAXs32,
1319 => Opcode::MVE_VMAXs8,
1320 => Opcode::MVE_VMAXu16,
1321 => Opcode::MVE_VMAXu32,
1322 => Opcode::MVE_VMAXu8,
1323 => Opcode::MVE_VMINAVs16,
1324 => Opcode::MVE_VMINAVs32,
1325 => Opcode::MVE_VMINAVs8,
1326 => Opcode::MVE_VMINAs16,
1327 => Opcode::MVE_VMINAs32,
1328 => Opcode::MVE_VMINAs8,
1329 => Opcode::MVE_VMINNMAVf16,
1330 => Opcode::MVE_VMINNMAVf32,
1331 => Opcode::MVE_VMINNMAf16,
1332 => Opcode::MVE_VMINNMAf32,
1333 => Opcode::MVE_VMINNMVf16,
1334 => Opcode::MVE_VMINNMVf32,
1335 => Opcode::MVE_VMINNMf16,
1336 => Opcode::MVE_VMINNMf32,
1337 => Opcode::MVE_VMINVs16,
1338 => Opcode::MVE_VMINVs32,
1339 => Opcode::MVE_VMINVs8,
1340 => Opcode::MVE_VMINVu16,
1341 => Opcode::MVE_VMINVu32,
1342 => Opcode::MVE_VMINVu8,
1343 => Opcode::MVE_VMINs16,
1344 => Opcode::MVE_VMINs32,
1345 => Opcode::MVE_VMINs8,
1346 => Opcode::MVE_VMINu16,
1347 => Opcode::MVE_VMINu32,
1348 => Opcode::MVE_VMINu8,
1349 => Opcode::MVE_VMLADAVas16,
1350 => Opcode::MVE_VMLADAVas32,
1351 => Opcode::MVE_VMLADAVas8,
1352 => Opcode::MVE_VMLADAVau16,
1353 => Opcode::MVE_VMLADAVau32,
1354 => Opcode::MVE_VMLADAVau8,
1355 => Opcode::MVE_VMLADAVaxs16,
1356 => Opcode::MVE_VMLADAVaxs32,
1357 => Opcode::MVE_VMLADAVaxs8,
1358 => Opcode::MVE_VMLADAVs16,
1359 => Opcode::MVE_VMLADAVs32,
1360 => Opcode::MVE_VMLADAVs8,
1361 => Opcode::MVE_VMLADAVu16,
1362 => Opcode::MVE_VMLADAVu32,
1363 => Opcode::MVE_VMLADAVu8,
1364 => Opcode::MVE_VMLADAVxs16,
1365 => Opcode::MVE_VMLADAVxs32,
1366 => Opcode::MVE_VMLADAVxs8,
1367 => Opcode::MVE_VMLALDAVas16,
1368 => Opcode::MVE_VMLALDAVas32,
1369 => Opcode::MVE_VMLALDAVau16,
1370 => Opcode::MVE_VMLALDAVau32,
1371 => Opcode::MVE_VMLALDAVaxs16,
1372 => Opcode::MVE_VMLALDAVaxs32,
1373 => Opcode::MVE_VMLALDAVs16,
1374 => Opcode::MVE_VMLALDAVs32,
1375 => Opcode::MVE_VMLALDAVu16,
1376 => Opcode::MVE_VMLALDAVu32,
1377 => Opcode::MVE_VMLALDAVxs16,
1378 => Opcode::MVE_VMLALDAVxs32,
1379 => Opcode::MVE_VMLAS_qr_i16,
1380 => Opcode::MVE_VMLAS_qr_i32,
1381 => Opcode::MVE_VMLAS_qr_i8,
1382 => Opcode::MVE_VMLA_qr_i16,
1383 => Opcode::MVE_VMLA_qr_i32,
1384 => Opcode::MVE_VMLA_qr_i8,
1385 => Opcode::MVE_VMLSDAVas16,
1386 => Opcode::MVE_VMLSDAVas32,
1387 => Opcode::MVE_VMLSDAVas8,
1388 => Opcode::MVE_VMLSDAVaxs16,
1389 => Opcode::MVE_VMLSDAVaxs32,
1390 => Opcode::MVE_VMLSDAVaxs8,
1391 => Opcode::MVE_VMLSDAVs16,
1392 => Opcode::MVE_VMLSDAVs32,
1393 => Opcode::MVE_VMLSDAVs8,
1394 => Opcode::MVE_VMLSDAVxs16,
1395 => Opcode::MVE_VMLSDAVxs32,
1396 => Opcode::MVE_VMLSDAVxs8,
1397 => Opcode::MVE_VMLSLDAVas16,
1398 => Opcode::MVE_VMLSLDAVas32,
1399 => Opcode::MVE_VMLSLDAVaxs16,
1400 => Opcode::MVE_VMLSLDAVaxs32,
1401 => Opcode::MVE_VMLSLDAVs16,
1402 => Opcode::MVE_VMLSLDAVs32,
1403 => Opcode::MVE_VMLSLDAVxs16,
1404 => Opcode::MVE_VMLSLDAVxs32,
1405 => Opcode::MVE_VMOVLs16bh,
1406 => Opcode::MVE_VMOVLs16th,
1407 => Opcode::MVE_VMOVLs8bh,
1408 => Opcode::MVE_VMOVLs8th,
1409 => Opcode::MVE_VMOVLu16bh,
1410 => Opcode::MVE_VMOVLu16th,
1411 => Opcode::MVE_VMOVLu8bh,
1412 => Opcode::MVE_VMOVLu8th,
1413 => Opcode::MVE_VMOVNi16bh,
1414 => Opcode::MVE_VMOVNi16th,
1415 => Opcode::MVE_VMOVNi32bh,
1416 => Opcode::MVE_VMOVNi32th,
1417 => Opcode::MVE_VMOV_from_lane_32,
1418 => Opcode::MVE_VMOV_from_lane_s16,
1419 => Opcode::MVE_VMOV_from_lane_s8,
1420 => Opcode::MVE_VMOV_from_lane_u16,
1421 => Opcode::MVE_VMOV_from_lane_u8,
1422 => Opcode::MVE_VMOV_q_rr,
1423 => Opcode::MVE_VMOV_rr_q,
1424 => Opcode::MVE_VMOV_to_lane_16,
1425 => Opcode::MVE_VMOV_to_lane_32,
1426 => Opcode::MVE_VMOV_to_lane_8,
1427 => Opcode::MVE_VMOVimmf32,
1428 => Opcode::MVE_VMOVimmi16,
1429 => Opcode::MVE_VMOVimmi32,
1430 => Opcode::MVE_VMOVimmi64,
1431 => Opcode::MVE_VMOVimmi8,
1432 => Opcode::MVE_VMULHs16,
1433 => Opcode::MVE_VMULHs32,
1434 => Opcode::MVE_VMULHs8,
1435 => Opcode::MVE_VMULHu16,
1436 => Opcode::MVE_VMULHu32,
1437 => Opcode::MVE_VMULHu8,
1438 => Opcode::MVE_VMULLBp16,
1439 => Opcode::MVE_VMULLBp8,
1440 => Opcode::MVE_VMULLBs16,
1441 => Opcode::MVE_VMULLBs32,
1442 => Opcode::MVE_VMULLBs8,
1443 => Opcode::MVE_VMULLBu16,
1444 => Opcode::MVE_VMULLBu32,
1445 => Opcode::MVE_VMULLBu8,
1446 => Opcode::MVE_VMULLTp16,
1447 => Opcode::MVE_VMULLTp8,
1448 => Opcode::MVE_VMULLTs16,
1449 => Opcode::MVE_VMULLTs32,
1450 => Opcode::MVE_VMULLTs8,
1451 => Opcode::MVE_VMULLTu16,
1452 => Opcode::MVE_VMULLTu32,
1453 => Opcode::MVE_VMULLTu8,
1454 => Opcode::MVE_VMUL_qr_f16,
1455 => Opcode::MVE_VMUL_qr_f32,
1456 => Opcode::MVE_VMUL_qr_i16,
1457 => Opcode::MVE_VMUL_qr_i32,
1458 => Opcode::MVE_VMUL_qr_i8,
1459 => Opcode::MVE_VMULf16,
1460 => Opcode::MVE_VMULf32,
1461 => Opcode::MVE_VMULi16,
1462 => Opcode::MVE_VMULi32,
1463 => Opcode::MVE_VMULi8,
1464 => Opcode::MVE_VMVN,
1465 => Opcode::MVE_VMVNimmi16,
1466 => Opcode::MVE_VMVNimmi32,
1467 => Opcode::MVE_VNEGf16,
1468 => Opcode::MVE_VNEGf32,
1469 => Opcode::MVE_VNEGs16,
1470 => Opcode::MVE_VNEGs32,
1471 => Opcode::MVE_VNEGs8,
1472 => Opcode::MVE_VORN,
1473 => Opcode::MVE_VORR,
1474 => Opcode::MVE_VORRimmi16,
1475 => Opcode::MVE_VORRimmi32,
1476 => Opcode::MVE_VPNOT,
1477 => Opcode::MVE_VPSEL,
1478 => Opcode::MVE_VPST,
1479 => Opcode::MVE_VPTv16i8,
1480 => Opcode::MVE_VPTv16i8r,
1481 => Opcode::MVE_VPTv16s8,
1482 => Opcode::MVE_VPTv16s8r,
1483 => Opcode::MVE_VPTv16u8,
1484 => Opcode::MVE_VPTv16u8r,
1485 => Opcode::MVE_VPTv4f32,
1486 => Opcode::MVE_VPTv4f32r,
1487 => Opcode::MVE_VPTv4i32,
1488 => Opcode::MVE_VPTv4i32r,
1489 => Opcode::MVE_VPTv4s32,
1490 => Opcode::MVE_VPTv4s32r,
1491 => Opcode::MVE_VPTv4u32,
1492 => Opcode::MVE_VPTv4u32r,
1493 => Opcode::MVE_VPTv8f16,
1494 => Opcode::MVE_VPTv8f16r,
1495 => Opcode::MVE_VPTv8i16,
1496 => Opcode::MVE_VPTv8i16r,
1497 => Opcode::MVE_VPTv8s16,
1498 => Opcode::MVE_VPTv8s16r,
1499 => Opcode::MVE_VPTv8u16,
1500 => Opcode::MVE_VPTv8u16r,
1501 => Opcode::MVE_VQABSs16,
1502 => Opcode::MVE_VQABSs32,
1503 => Opcode::MVE_VQABSs8,
1504 => Opcode::MVE_VQADD_qr_s16,
1505 => Opcode::MVE_VQADD_qr_s32,
1506 => Opcode::MVE_VQADD_qr_s8,
1507 => Opcode::MVE_VQADD_qr_u16,
1508 => Opcode::MVE_VQADD_qr_u32,
1509 => Opcode::MVE_VQADD_qr_u8,
1510 => Opcode::MVE_VQADDs16,
1511 => Opcode::MVE_VQADDs32,
1512 => Opcode::MVE_VQADDs8,
1513 => Opcode::MVE_VQADDu16,
1514 => Opcode::MVE_VQADDu32,
1515 => Opcode::MVE_VQADDu8,
1516 => Opcode::MVE_VQDMLADHXs16,
1517 => Opcode::MVE_VQDMLADHXs32,
1518 => Opcode::MVE_VQDMLADHXs8,
1519 => Opcode::MVE_VQDMLADHs16,
1520 => Opcode::MVE_VQDMLADHs32,
1521 => Opcode::MVE_VQDMLADHs8,
1522 => Opcode::MVE_VQDMLAH_qrs16,
1523 => Opcode::MVE_VQDMLAH_qrs32,
1524 => Opcode::MVE_VQDMLAH_qrs8,
1525 => Opcode::MVE_VQDMLASH_qrs16,
1526 => Opcode::MVE_VQDMLASH_qrs32,
1527 => Opcode::MVE_VQDMLASH_qrs8,
1528 => Opcode::MVE_VQDMLSDHXs16,
1529 => Opcode::MVE_VQDMLSDHXs32,
1530 => Opcode::MVE_VQDMLSDHXs8,
1531 => Opcode::MVE_VQDMLSDHs16,
1532 => Opcode::MVE_VQDMLSDHs32,
1533 => Opcode::MVE_VQDMLSDHs8,
1534 => Opcode::MVE_VQDMULH_qr_s16,
1535 => Opcode::MVE_VQDMULH_qr_s32,
1536 => Opcode::MVE_VQDMULH_qr_s8,
1537 => Opcode::MVE_VQDMULHi16,
1538 => Opcode::MVE_VQDMULHi32,
1539 => Opcode::MVE_VQDMULHi8,
1540 => Opcode::MVE_VQDMULL_qr_s16bh,
1541 => Opcode::MVE_VQDMULL_qr_s16th,
1542 => Opcode::MVE_VQDMULL_qr_s32bh,
1543 => Opcode::MVE_VQDMULL_qr_s32th,
1544 => Opcode::MVE_VQDMULLs16bh,
1545 => Opcode::MVE_VQDMULLs16th,
1546 => Opcode::MVE_VQDMULLs32bh,
1547 => Opcode::MVE_VQDMULLs32th,
1548 => Opcode::MVE_VQMOVNs16bh,
1549 => Opcode::MVE_VQMOVNs16th,
1550 => Opcode::MVE_VQMOVNs32bh,
1551 => Opcode::MVE_VQMOVNs32th,
1552 => Opcode::MVE_VQMOVNu16bh,
1553 => Opcode::MVE_VQMOVNu16th,
1554 => Opcode::MVE_VQMOVNu32bh,
1555 => Opcode::MVE_VQMOVNu32th,
1556 => Opcode::MVE_VQMOVUNs16bh,
1557 => Opcode::MVE_VQMOVUNs16th,
1558 => Opcode::MVE_VQMOVUNs32bh,
1559 => Opcode::MVE_VQMOVUNs32th,
1560 => Opcode::MVE_VQNEGs16,
1561 => Opcode::MVE_VQNEGs32,
1562 => Opcode::MVE_VQNEGs8,
1563 => Opcode::MVE_VQRDMLADHXs16,
1564 => Opcode::MVE_VQRDMLADHXs32,
1565 => Opcode::MVE_VQRDMLADHXs8,
1566 => Opcode::MVE_VQRDMLADHs16,
1567 => Opcode::MVE_VQRDMLADHs32,
1568 => Opcode::MVE_VQRDMLADHs8,
1569 => Opcode::MVE_VQRDMLAH_qrs16,
1570 => Opcode::MVE_VQRDMLAH_qrs32,
1571 => Opcode::MVE_VQRDMLAH_qrs8,
1572 => Opcode::MVE_VQRDMLASH_qrs16,
1573 => Opcode::MVE_VQRDMLASH_qrs32,
1574 => Opcode::MVE_VQRDMLASH_qrs8,
1575 => Opcode::MVE_VQRDMLSDHXs16,
1576 => Opcode::MVE_VQRDMLSDHXs32,
1577 => Opcode::MVE_VQRDMLSDHXs8,
1578 => Opcode::MVE_VQRDMLSDHs16,
1579 => Opcode::MVE_VQRDMLSDHs32,
1580 => Opcode::MVE_VQRDMLSDHs8,
1581 => Opcode::MVE_VQRDMULH_qr_s16,
1582 => Opcode::MVE_VQRDMULH_qr_s32,
1583 => Opcode::MVE_VQRDMULH_qr_s8,
1584 => Opcode::MVE_VQRDMULHi16,
1585 => Opcode::MVE_VQRDMULHi32,
1586 => Opcode::MVE_VQRDMULHi8,
1587 => Opcode::MVE_VQRSHL_by_vecs16,
1588 => Opcode::MVE_VQRSHL_by_vecs32,
1589 => Opcode::MVE_VQRSHL_by_vecs8,
1590 => Opcode::MVE_VQRSHL_by_vecu16,
1591 => Opcode::MVE_VQRSHL_by_vecu32,
1592 => Opcode::MVE_VQRSHL_by_vecu8,
1593 => Opcode::MVE_VQRSHL_qrs16,
1594 => Opcode::MVE_VQRSHL_qrs32,
1595 => Opcode::MVE_VQRSHL_qrs8,
1596 => Opcode::MVE_VQRSHL_qru16,
1597 => Opcode::MVE_VQRSHL_qru32,
1598 => Opcode::MVE_VQRSHL_qru8,
1599 => Opcode::MVE_VQRSHRNbhs16,
1600 => Opcode::MVE_VQRSHRNbhs32,
1601 => Opcode::MVE_VQRSHRNbhu16,
1602 => Opcode::MVE_VQRSHRNbhu32,
1603 => Opcode::MVE_VQRSHRNths16,
1604 => Opcode::MVE_VQRSHRNths32,
1605 => Opcode::MVE_VQRSHRNthu16,
1606 => Opcode::MVE_VQRSHRNthu32,
1607 => Opcode::MVE_VQRSHRUNs16bh,
1608 => Opcode::MVE_VQRSHRUNs16th,
1609 => Opcode::MVE_VQRSHRUNs32bh,
1610 => Opcode::MVE_VQRSHRUNs32th,
1611 => Opcode::MVE_VQSHLU_imms16,
1612 => Opcode::MVE_VQSHLU_imms32,
1613 => Opcode::MVE_VQSHLU_imms8,
1614 => Opcode::MVE_VQSHL_by_vecs16,
1615 => Opcode::MVE_VQSHL_by_vecs32,
1616 => Opcode::MVE_VQSHL_by_vecs8,
1617 => Opcode::MVE_VQSHL_by_vecu16,
1618 => Opcode::MVE_VQSHL_by_vecu32,
1619 => Opcode::MVE_VQSHL_by_vecu8,
1620 => Opcode::MVE_VQSHL_qrs16,
1621 => Opcode::MVE_VQSHL_qrs32,
1622 => Opcode::MVE_VQSHL_qrs8,
1623 => Opcode::MVE_VQSHL_qru16,
1624 => Opcode::MVE_VQSHL_qru32,
1625 => Opcode::MVE_VQSHL_qru8,
1626 => Opcode::MVE_VQSHLimms16,
1627 => Opcode::MVE_VQSHLimms32,
1628 => Opcode::MVE_VQSHLimms8,
1629 => Opcode::MVE_VQSHLimmu16,
1630 => Opcode::MVE_VQSHLimmu32,
1631 => Opcode::MVE_VQSHLimmu8,
1632 => Opcode::MVE_VQSHRNbhs16,
1633 => Opcode::MVE_VQSHRNbhs32,
1634 => Opcode::MVE_VQSHRNbhu16,
1635 => Opcode::MVE_VQSHRNbhu32,
1636 => Opcode::MVE_VQSHRNths16,
1637 => Opcode::MVE_VQSHRNths32,
1638 => Opcode::MVE_VQSHRNthu16,
1639 => Opcode::MVE_VQSHRNthu32,
1640 => Opcode::MVE_VQSHRUNs16bh,
1641 => Opcode::MVE_VQSHRUNs16th,
1642 => Opcode::MVE_VQSHRUNs32bh,
1643 => Opcode::MVE_VQSHRUNs32th,
1644 => Opcode::MVE_VQSUB_qr_s16,
1645 => Opcode::MVE_VQSUB_qr_s32,
1646 => Opcode::MVE_VQSUB_qr_s8,
1647 => Opcode::MVE_VQSUB_qr_u16,
1648 => Opcode::MVE_VQSUB_qr_u32,
1649 => Opcode::MVE_VQSUB_qr_u8,
1650 => Opcode::MVE_VQSUBs16,
1651 => Opcode::MVE_VQSUBs32,
1652 => Opcode::MVE_VQSUBs8,
1653 => Opcode::MVE_VQSUBu16,
1654 => Opcode::MVE_VQSUBu32,
1655 => Opcode::MVE_VQSUBu8,
1656 => Opcode::MVE_VREV16_8,
1657 => Opcode::MVE_VREV32_16,
1658 => Opcode::MVE_VREV32_8,
1659 => Opcode::MVE_VREV64_16,
1660 => Opcode::MVE_VREV64_32,
1661 => Opcode::MVE_VREV64_8,
1662 => Opcode::MVE_VRHADDs16,
1663 => Opcode::MVE_VRHADDs32,
1664 => Opcode::MVE_VRHADDs8,
1665 => Opcode::MVE_VRHADDu16,
1666 => Opcode::MVE_VRHADDu32,
1667 => Opcode::MVE_VRHADDu8,
1668 => Opcode::MVE_VRINTf16A,
1669 => Opcode::MVE_VRINTf16M,
1670 => Opcode::MVE_VRINTf16N,
1671 => Opcode::MVE_VRINTf16P,
1672 => Opcode::MVE_VRINTf16X,
1673 => Opcode::MVE_VRINTf16Z,
1674 => Opcode::MVE_VRINTf32A,
1675 => Opcode::MVE_VRINTf32M,
1676 => Opcode::MVE_VRINTf32N,
1677 => Opcode::MVE_VRINTf32P,
1678 => Opcode::MVE_VRINTf32X,
1679 => Opcode::MVE_VRINTf32Z,
1680 => Opcode::MVE_VRMLALDAVHas32,
1681 => Opcode::MVE_VRMLALDAVHau32,
1682 => Opcode::MVE_VRMLALDAVHaxs32,
1683 => Opcode::MVE_VRMLALDAVHs32,
1684 => Opcode::MVE_VRMLALDAVHu32,
1685 => Opcode::MVE_VRMLALDAVHxs32,
1686 => Opcode::MVE_VRMLSLDAVHas32,
1687 => Opcode::MVE_VRMLSLDAVHaxs32,
1688 => Opcode::MVE_VRMLSLDAVHs32,
1689 => Opcode::MVE_VRMLSLDAVHxs32,
1690 => Opcode::MVE_VRMULHs16,
1691 => Opcode::MVE_VRMULHs32,
1692 => Opcode::MVE_VRMULHs8,
1693 => Opcode::MVE_VRMULHu16,
1694 => Opcode::MVE_VRMULHu32,
1695 => Opcode::MVE_VRMULHu8,
1696 => Opcode::MVE_VRSHL_by_vecs16,
1697 => Opcode::MVE_VRSHL_by_vecs32,
1698 => Opcode::MVE_VRSHL_by_vecs8,
1699 => Opcode::MVE_VRSHL_by_vecu16,
1700 => Opcode::MVE_VRSHL_by_vecu32,
1701 => Opcode::MVE_VRSHL_by_vecu8,
1702 => Opcode::MVE_VRSHL_qrs16,
1703 => Opcode::MVE_VRSHL_qrs32,
1704 => Opcode::MVE_VRSHL_qrs8,
1705 => Opcode::MVE_VRSHL_qru16,
1706 => Opcode::MVE_VRSHL_qru32,
1707 => Opcode::MVE_VRSHL_qru8,
1708 => Opcode::MVE_VRSHRNi16bh,
1709 => Opcode::MVE_VRSHRNi16th,
1710 => Opcode::MVE_VRSHRNi32bh,
1711 => Opcode::MVE_VRSHRNi32th,
1712 => Opcode::MVE_VRSHR_imms16,
1713 => Opcode::MVE_VRSHR_imms32,
1714 => Opcode::MVE_VRSHR_imms8,
1715 => Opcode::MVE_VRSHR_immu16,
1716 => Opcode::MVE_VRSHR_immu32,
1717 => Opcode::MVE_VRSHR_immu8,
1718 => Opcode::MVE_VSBC,
1719 => Opcode::MVE_VSBCI,
1720 => Opcode::MVE_VSHLC,
1721 => Opcode::MVE_VSHLL_imms16bh,
1722 => Opcode::MVE_VSHLL_imms16th,
1723 => Opcode::MVE_VSHLL_imms8bh,
1724 => Opcode::MVE_VSHLL_imms8th,
1725 => Opcode::MVE_VSHLL_immu16bh,
1726 => Opcode::MVE_VSHLL_immu16th,
1727 => Opcode::MVE_VSHLL_immu8bh,
1728 => Opcode::MVE_VSHLL_immu8th,
1729 => Opcode::MVE_VSHLL_lws16bh,
1730 => Opcode::MVE_VSHLL_lws16th,
1731 => Opcode::MVE_VSHLL_lws8bh,
1732 => Opcode::MVE_VSHLL_lws8th,
1733 => Opcode::MVE_VSHLL_lwu16bh,
1734 => Opcode::MVE_VSHLL_lwu16th,
1735 => Opcode::MVE_VSHLL_lwu8bh,
1736 => Opcode::MVE_VSHLL_lwu8th,
1737 => Opcode::MVE_VSHL_by_vecs16,
1738 => Opcode::MVE_VSHL_by_vecs32,
1739 => Opcode::MVE_VSHL_by_vecs8,
1740 => Opcode::MVE_VSHL_by_vecu16,
1741 => Opcode::MVE_VSHL_by_vecu32,
1742 => Opcode::MVE_VSHL_by_vecu8,
1743 => Opcode::MVE_VSHL_immi16,
1744 => Opcode::MVE_VSHL_immi32,
1745 => Opcode::MVE_VSHL_immi8,
1746 => Opcode::MVE_VSHL_qrs16,
1747 => Opcode::MVE_VSHL_qrs32,
1748 => Opcode::MVE_VSHL_qrs8,
1749 => Opcode::MVE_VSHL_qru16,
1750 => Opcode::MVE_VSHL_qru32,
1751 => Opcode::MVE_VSHL_qru8,
1752 => Opcode::MVE_VSHRNi16bh,
1753 => Opcode::MVE_VSHRNi16th,
1754 => Opcode::MVE_VSHRNi32bh,
1755 => Opcode::MVE_VSHRNi32th,
1756 => Opcode::MVE_VSHR_imms16,
1757 => Opcode::MVE_VSHR_imms32,
1758 => Opcode::MVE_VSHR_imms8,
1759 => Opcode::MVE_VSHR_immu16,
1760 => Opcode::MVE_VSHR_immu32,
1761 => Opcode::MVE_VSHR_immu8,
1762 => Opcode::MVE_VSLIimm16,
1763 => Opcode::MVE_VSLIimm32,
1764 => Opcode::MVE_VSLIimm8,
1765 => Opcode::MVE_VSRIimm16,
1766 => Opcode::MVE_VSRIimm32,
1767 => Opcode::MVE_VSRIimm8,
1768 => Opcode::MVE_VST20_16,
1769 => Opcode::MVE_VST20_16_wb,
1770 => Opcode::MVE_VST20_32,
1771 => Opcode::MVE_VST20_32_wb,
1772 => Opcode::MVE_VST20_8,
1773 => Opcode::MVE_VST20_8_wb,
1774 => Opcode::MVE_VST21_16,
1775 => Opcode::MVE_VST21_16_wb,
1776 => Opcode::MVE_VST21_32,
1777 => Opcode::MVE_VST21_32_wb,
1778 => Opcode::MVE_VST21_8,
1779 => Opcode::MVE_VST21_8_wb,
1780 => Opcode::MVE_VST40_16,
1781 => Opcode::MVE_VST40_16_wb,
1782 => Opcode::MVE_VST40_32,
1783 => Opcode::MVE_VST40_32_wb,
1784 => Opcode::MVE_VST40_8,
1785 => Opcode::MVE_VST40_8_wb,
1786 => Opcode::MVE_VST41_16,
1787 => Opcode::MVE_VST41_16_wb,
1788 => Opcode::MVE_VST41_32,
1789 => Opcode::MVE_VST41_32_wb,
1790 => Opcode::MVE_VST41_8,
1791 => Opcode::MVE_VST41_8_wb,
1792 => Opcode::MVE_VST42_16,
1793 => Opcode::MVE_VST42_16_wb,
1794 => Opcode::MVE_VST42_32,
1795 => Opcode::MVE_VST42_32_wb,
1796 => Opcode::MVE_VST42_8,
1797 => Opcode::MVE_VST42_8_wb,
1798 => Opcode::MVE_VST43_16,
1799 => Opcode::MVE_VST43_16_wb,
1800 => Opcode::MVE_VST43_32,
1801 => Opcode::MVE_VST43_32_wb,
1802 => Opcode::MVE_VST43_8,
1803 => Opcode::MVE_VST43_8_wb,
1804 => Opcode::MVE_VSTRB16,
1805 => Opcode::MVE_VSTRB16_post,
1806 => Opcode::MVE_VSTRB16_pre,
1807 => Opcode::MVE_VSTRB16_rq,
1808 => Opcode::MVE_VSTRB32,
1809 => Opcode::MVE_VSTRB32_post,
1810 => Opcode::MVE_VSTRB32_pre,
1811 => Opcode::MVE_VSTRB32_rq,
1812 => Opcode::MVE_VSTRB8_rq,
1813 => Opcode::MVE_VSTRBU8,
1814 => Opcode::MVE_VSTRBU8_post,
1815 => Opcode::MVE_VSTRBU8_pre,
1816 => Opcode::MVE_VSTRD64_qi,
1817 => Opcode::MVE_VSTRD64_qi_pre,
1818 => Opcode::MVE_VSTRD64_rq,
1819 => Opcode::MVE_VSTRD64_rq_u,
1820 => Opcode::MVE_VSTRH16_rq,
1821 => Opcode::MVE_VSTRH16_rq_u,
1822 => Opcode::MVE_VSTRH32,
1823 => Opcode::MVE_VSTRH32_post,
1824 => Opcode::MVE_VSTRH32_pre,
1825 => Opcode::MVE_VSTRH32_rq,
1826 => Opcode::MVE_VSTRH32_rq_u,
1827 => Opcode::MVE_VSTRHU16,
1828 => Opcode::MVE_VSTRHU16_post,
1829 => Opcode::MVE_VSTRHU16_pre,
1830 => Opcode::MVE_VSTRW32_qi,
1831 => Opcode::MVE_VSTRW32_qi_pre,
1832 => Opcode::MVE_VSTRW32_rq,
1833 => Opcode::MVE_VSTRW32_rq_u,
1834 => Opcode::MVE_VSTRWU32,
1835 => Opcode::MVE_VSTRWU32_post,
1836 => Opcode::MVE_VSTRWU32_pre,
1837 => Opcode::MVE_VSUB_qr_f16,
1838 => Opcode::MVE_VSUB_qr_f32,
1839 => Opcode::MVE_VSUB_qr_i16,
1840 => Opcode::MVE_VSUB_qr_i32,
1841 => Opcode::MVE_VSUB_qr_i8,
1842 => Opcode::MVE_VSUBf16,
1843 => Opcode::MVE_VSUBf32,
1844 => Opcode::MVE_VSUBi16,
1845 => Opcode::MVE_VSUBi32,
1846 => Opcode::MVE_VSUBi8,
1847 => Opcode::MVE_WLSTP_16,
1848 => Opcode::MVE_WLSTP_32,
1849 => Opcode::MVE_WLSTP_64,
1850 => Opcode::MVE_WLSTP_8,
1851 => Opcode::MVNi,
1852 => Opcode::MVNr,
1853 => Opcode::MVNsi,
1854 => Opcode::MVNsr,
1855 => Opcode::NEON_VMAXNMNDf,
1856 => Opcode::NEON_VMAXNMNDh,
1857 => Opcode::NEON_VMAXNMNQf,
1858 => Opcode::NEON_VMAXNMNQh,
1859 => Opcode::NEON_VMINNMNDf,
1860 => Opcode::NEON_VMINNMNDh,
1861 => Opcode::NEON_VMINNMNQf,
1862 => Opcode::NEON_VMINNMNQh,
1863 => Opcode::ORRri,
1864 => Opcode::ORRrr,
1865 => Opcode::ORRrsi,
1866 => Opcode::ORRrsr,
1867 => Opcode::PKHBT,
1868 => Opcode::PKHTB,
1869 => Opcode::PLDWi12,
1870 => Opcode::PLDWrs,
1871 => Opcode::PLDi12,
1872 => Opcode::PLDrs,
1873 => Opcode::PLIi12,
1874 => Opcode::PLIrs,
1875 => Opcode::QADD,
1876 => Opcode::QADD16,
1877 => Opcode::QADD8,
1878 => Opcode::QASX,
1879 => Opcode::QDADD,
1880 => Opcode::QDSUB,
1881 => Opcode::QSAX,
1882 => Opcode::QSUB,
1883 => Opcode::QSUB16,
1884 => Opcode::QSUB8,
1885 => Opcode::RBIT,
1886 => Opcode::REV,
1887 => Opcode::REV16,
1888 => Opcode::REVSH,
1889 => Opcode::RFEDA,
1890 => Opcode::RFEDA_UPD,
1891 => Opcode::RFEDB,
1892 => Opcode::RFEDB_UPD,
1893 => Opcode::RFEIA,
1894 => Opcode::RFEIA_UPD,
1895 => Opcode::RFEIB,
1896 => Opcode::RFEIB_UPD,
1897 => Opcode::RSBri,
1898 => Opcode::RSBrr,
1899 => Opcode::RSBrsi,
1900 => Opcode::RSBrsr,
1901 => Opcode::RSCri,
1902 => Opcode::RSCrr,
1903 => Opcode::RSCrsi,
1904 => Opcode::RSCrsr,
1905 => Opcode::SADD16,
1906 => Opcode::SADD8,
1907 => Opcode::SASX,
1908 => Opcode::SB,
1909 => Opcode::SBCri,
1910 => Opcode::SBCrr,
1911 => Opcode::SBCrsi,
1912 => Opcode::SBCrsr,
1913 => Opcode::SBFX,
1914 => Opcode::SDIV,
1915 => Opcode::SEL,
1916 => Opcode::SETEND,
1917 => Opcode::SETPAN,
1918 => Opcode::SHA1C,
1919 => Opcode::SHA1H,
1920 => Opcode::SHA1M,
1921 => Opcode::SHA1P,
1922 => Opcode::SHA1SU0,
1923 => Opcode::SHA1SU1,
1924 => Opcode::SHA256H,
1925 => Opcode::SHA256H2,
1926 => Opcode::SHA256SU0,
1927 => Opcode::SHA256SU1,
1928 => Opcode::SHADD16,
1929 => Opcode::SHADD8,
1930 => Opcode::SHASX,
1931 => Opcode::SHSAX,
1932 => Opcode::SHSUB16,
1933 => Opcode::SHSUB8,
1934 => Opcode::SMC,
1935 => Opcode::SMLABB,
1936 => Opcode::SMLABT,
1937 => Opcode::SMLAD,
1938 => Opcode::SMLADX,
1939 => Opcode::SMLAL,
1940 => Opcode::SMLALBB,
1941 => Opcode::SMLALBT,
1942 => Opcode::SMLALD,
1943 => Opcode::SMLALDX,
1944 => Opcode::SMLALTB,
1945 => Opcode::SMLALTT,
1946 => Opcode::SMLATB,
1947 => Opcode::SMLATT,
1948 => Opcode::SMLAWB,
1949 => Opcode::SMLAWT,
1950 => Opcode::SMLSD,
1951 => Opcode::SMLSDX,
1952 => Opcode::SMLSLD,
1953 => Opcode::SMLSLDX,
1954 => Opcode::SMMLA,
1955 => Opcode::SMMLAR,
1956 => Opcode::SMMLS,
1957 => Opcode::SMMLSR,
1958 => Opcode::SMMUL,
1959 => Opcode::SMMULR,
1960 => Opcode::SMUAD,
1961 => Opcode::SMUADX,
1962 => Opcode::SMULBB,
1963 => Opcode::SMULBT,
1964 => Opcode::SMULL,
1965 => Opcode::SMULTB,
1966 => Opcode::SMULTT,
1967 => Opcode::SMULWB,
1968 => Opcode::SMULWT,
1969 => Opcode::SMUSD,
1970 => Opcode::SMUSDX,
1971 => Opcode::SRSDA,
1972 => Opcode::SRSDA_UPD,
1973 => Opcode::SRSDB,
1974 => Opcode::SRSDB_UPD,
1975 => Opcode::SRSIA,
1976 => Opcode::SRSIA_UPD,
1977 => Opcode::SRSIB,
1978 => Opcode::SRSIB_UPD,
1979 => Opcode::SSAT,
1980 => Opcode::SSAT16,
1981 => Opcode::SSAX,
1982 => Opcode::SSUB16,
1983 => Opcode::SSUB8,
1984 => Opcode::STC2L_OFFSET,
1985 => Opcode::STC2L_OPTION,
1986 => Opcode::STC2L_POST,
1987 => Opcode::STC2L_PRE,
1988 => Opcode::STC2_OFFSET,
1989 => Opcode::STC2_OPTION,
1990 => Opcode::STC2_POST,
1991 => Opcode::STC2_PRE,
1992 => Opcode::STCL_OFFSET,
1993 => Opcode::STCL_OPTION,
1994 => Opcode::STCL_POST,
1995 => Opcode::STCL_PRE,
1996 => Opcode::STC_OFFSET,
1997 => Opcode::STC_OPTION,
1998 => Opcode::STC_POST,
1999 => Opcode::STC_PRE,
2000 => Opcode::STL,
2001 => Opcode::STLB,
2002 => Opcode::STLEX,
2003 => Opcode::STLEXB,
2004 => Opcode::STLEXD,
2005 => Opcode::STLEXH,
2006 => Opcode::STLH,
2007 => Opcode::STMDA,
2008 => Opcode::STMDA_UPD,
2009 => Opcode::STMDB,
2010 => Opcode::STMDB_UPD,
2011 => Opcode::STMIA,
2012 => Opcode::STMIA_UPD,
2013 => Opcode::STMIB,
2014 => Opcode::STMIB_UPD,
2015 => Opcode::STRBT_POST_IMM,
2016 => Opcode::STRBT_POST_REG,
2017 => Opcode::STRB_POST_IMM,
2018 => Opcode::STRB_POST_REG,
2019 => Opcode::STRB_PRE_IMM,
2020 => Opcode::STRB_PRE_REG,
2021 => Opcode::STRBi12,
2022 => Opcode::STRBrs,
2023 => Opcode::STRD,
2024 => Opcode::STRD_POST,
2025 => Opcode::STRD_PRE,
2026 => Opcode::STREX,
2027 => Opcode::STREXB,
2028 => Opcode::STREXD,
2029 => Opcode::STREXH,
2030 => Opcode::STRH,
2031 => Opcode::STRHTi,
2032 => Opcode::STRHTr,
2033 => Opcode::STRH_POST,
2034 => Opcode::STRH_PRE,
2035 => Opcode::STRT_POST_IMM,
2036 => Opcode::STRT_POST_REG,
2037 => Opcode::STR_POST_IMM,
2038 => Opcode::STR_POST_REG,
2039 => Opcode::STR_PRE_IMM,
2040 => Opcode::STR_PRE_REG,
2041 => Opcode::STRi12,
2042 => Opcode::STRrs,
2043 => Opcode::SUBri,
2044 => Opcode::SUBrr,
2045 => Opcode::SUBrsi,
2046 => Opcode::SUBrsr,
2047 => Opcode::SVC,
2048 => Opcode::SWP,
2049 => Opcode::SWPB,
2050 => Opcode::SXTAB,
2051 => Opcode::SXTAB16,
2052 => Opcode::SXTAH,
2053 => Opcode::SXTB,
2054 => Opcode::SXTB16,
2055 => Opcode::SXTH,
2056 => Opcode::TEQri,
2057 => Opcode::TEQrr,
2058 => Opcode::TEQrsi,
2059 => Opcode::TEQrsr,
2060 => Opcode::TRAP,
2061 => Opcode::TSB,
2062 => Opcode::TSTri,
2063 => Opcode::TSTrr,
2064 => Opcode::TSTrsi,
2065 => Opcode::TSTrsr,
2066 => Opcode::UADD16,
2067 => Opcode::UADD8,
2068 => Opcode::UASX,
2069 => Opcode::UBFX,
2070 => Opcode::UDF,
2071 => Opcode::UDIV,
2072 => Opcode::UHADD16,
2073 => Opcode::UHADD8,
2074 => Opcode::UHASX,
2075 => Opcode::UHSAX,
2076 => Opcode::UHSUB16,
2077 => Opcode::UHSUB8,
2078 => Opcode::UMAAL,
2079 => Opcode::UMLAL,
2080 => Opcode::UMULL,
2081 => Opcode::UQADD16,
2082 => Opcode::UQADD8,
2083 => Opcode::UQASX,
2084 => Opcode::UQSAX,
2085 => Opcode::UQSUB16,
2086 => Opcode::UQSUB8,
2087 => Opcode::USAD8,
2088 => Opcode::USADA8,
2089 => Opcode::USAT,
2090 => Opcode::USAT16,
2091 => Opcode::USAX,
2092 => Opcode::USUB16,
2093 => Opcode::USUB8,
2094 => Opcode::UXTAB,
2095 => Opcode::UXTAB16,
2096 => Opcode::UXTAH,
2097 => Opcode::UXTB,
2098 => Opcode::UXTB16,
2099 => Opcode::UXTH,
2100 => Opcode::VABALsv2i64,
2101 => Opcode::VABALsv4i32,
2102 => Opcode::VABALsv8i16,
2103 => Opcode::VABALuv2i64,
2104 => Opcode::VABALuv4i32,
2105 => Opcode::VABALuv8i16,
2106 => Opcode::VABAsv16i8,
2107 => Opcode::VABAsv2i32,
2108 => Opcode::VABAsv4i16,
2109 => Opcode::VABAsv4i32,
2110 => Opcode::VABAsv8i16,
2111 => Opcode::VABAsv8i8,
2112 => Opcode::VABAuv16i8,
2113 => Opcode::VABAuv2i32,
2114 => Opcode::VABAuv4i16,
2115 => Opcode::VABAuv4i32,
2116 => Opcode::VABAuv8i16,
2117 => Opcode::VABAuv8i8,
2118 => Opcode::VABDLsv2i64,
2119 => Opcode::VABDLsv4i32,
2120 => Opcode::VABDLsv8i16,
2121 => Opcode::VABDLuv2i64,
2122 => Opcode::VABDLuv4i32,
2123 => Opcode::VABDLuv8i16,
2124 => Opcode::VABDfd,
2125 => Opcode::VABDfq,
2126 => Opcode::VABDhd,
2127 => Opcode::VABDhq,
2128 => Opcode::VABDsv16i8,
2129 => Opcode::VABDsv2i32,
2130 => Opcode::VABDsv4i16,
2131 => Opcode::VABDsv4i32,
2132 => Opcode::VABDsv8i16,
2133 => Opcode::VABDsv8i8,
2134 => Opcode::VABDuv16i8,
2135 => Opcode::VABDuv2i32,
2136 => Opcode::VABDuv4i16,
2137 => Opcode::VABDuv4i32,
2138 => Opcode::VABDuv8i16,
2139 => Opcode::VABDuv8i8,
2140 => Opcode::VABSD,
2141 => Opcode::VABSH,
2142 => Opcode::VABSS,
2143 => Opcode::VABSfd,
2144 => Opcode::VABSfq,
2145 => Opcode::VABShd,
2146 => Opcode::VABShq,
2147 => Opcode::VABSv16i8,
2148 => Opcode::VABSv2i32,
2149 => Opcode::VABSv4i16,
2150 => Opcode::VABSv4i32,
2151 => Opcode::VABSv8i16,
2152 => Opcode::VABSv8i8,
2153 => Opcode::VACGEfd,
2154 => Opcode::VACGEfq,
2155 => Opcode::VACGEhd,
2156 => Opcode::VACGEhq,
2157 => Opcode::VACGTfd,
2158 => Opcode::VACGTfq,
2159 => Opcode::VACGThd,
2160 => Opcode::VACGThq,
2161 => Opcode::VADDD,
2162 => Opcode::VADDH,
2163 => Opcode::VADDHNv2i32,
2164 => Opcode::VADDHNv4i16,
2165 => Opcode::VADDHNv8i8,
2166 => Opcode::VADDLsv2i64,
2167 => Opcode::VADDLsv4i32,
2168 => Opcode::VADDLsv8i16,
2169 => Opcode::VADDLuv2i64,
2170 => Opcode::VADDLuv4i32,
2171 => Opcode::VADDLuv8i16,
2172 => Opcode::VADDS,
2173 => Opcode::VADDWsv2i64,
2174 => Opcode::VADDWsv4i32,
2175 => Opcode::VADDWsv8i16,
2176 => Opcode::VADDWuv2i64,
2177 => Opcode::VADDWuv4i32,
2178 => Opcode::VADDWuv8i16,
2179 => Opcode::VADDfd,
2180 => Opcode::VADDfq,
2181 => Opcode::VADDhd,
2182 => Opcode::VADDhq,
2183 => Opcode::VADDv16i8,
2184 => Opcode::VADDv1i64,
2185 => Opcode::VADDv2i32,
2186 => Opcode::VADDv2i64,
2187 => Opcode::VADDv4i16,
2188 => Opcode::VADDv4i32,
2189 => Opcode::VADDv8i16,
2190 => Opcode::VADDv8i8,
2191 => Opcode::VANDd,
2192 => Opcode::VANDq,
2193 => Opcode::VBF16MALBQ,
2194 => Opcode::VBF16MALBQI,
2195 => Opcode::VBF16MALTQ,
2196 => Opcode::VBF16MALTQI,
2197 => Opcode::VBICd,
2198 => Opcode::VBICiv2i32,
2199 => Opcode::VBICiv4i16,
2200 => Opcode::VBICiv4i32,
2201 => Opcode::VBICiv8i16,
2202 => Opcode::VBICq,
2203 => Opcode::VBIFd,
2204 => Opcode::VBIFq,
2205 => Opcode::VBITd,
2206 => Opcode::VBITq,
2207 => Opcode::VBSLd,
2208 => Opcode::VBSLq,
2209 => Opcode::VBSPd,
2210 => Opcode::VBSPq,
2211 => Opcode::VCADDv2f32,
2212 => Opcode::VCADDv4f16,
2213 => Opcode::VCADDv4f32,
2214 => Opcode::VCADDv8f16,
2215 => Opcode::VCEQfd,
2216 => Opcode::VCEQfq,
2217 => Opcode::VCEQhd,
2218 => Opcode::VCEQhq,
2219 => Opcode::VCEQv16i8,
2220 => Opcode::VCEQv2i32,
2221 => Opcode::VCEQv4i16,
2222 => Opcode::VCEQv4i32,
2223 => Opcode::VCEQv8i16,
2224 => Opcode::VCEQv8i8,
2225 => Opcode::VCEQzv16i8,
2226 => Opcode::VCEQzv2f32,
2227 => Opcode::VCEQzv2i32,
2228 => Opcode::VCEQzv4f16,
2229 => Opcode::VCEQzv4f32,
2230 => Opcode::VCEQzv4i16,
2231 => Opcode::VCEQzv4i32,
2232 => Opcode::VCEQzv8f16,
2233 => Opcode::VCEQzv8i16,
2234 => Opcode::VCEQzv8i8,
2235 => Opcode::VCGEfd,
2236 => Opcode::VCGEfq,
2237 => Opcode::VCGEhd,
2238 => Opcode::VCGEhq,
2239 => Opcode::VCGEsv16i8,
2240 => Opcode::VCGEsv2i32,
2241 => Opcode::VCGEsv4i16,
2242 => Opcode::VCGEsv4i32,
2243 => Opcode::VCGEsv8i16,
2244 => Opcode::VCGEsv8i8,
2245 => Opcode::VCGEuv16i8,
2246 => Opcode::VCGEuv2i32,
2247 => Opcode::VCGEuv4i16,
2248 => Opcode::VCGEuv4i32,
2249 => Opcode::VCGEuv8i16,
2250 => Opcode::VCGEuv8i8,
2251 => Opcode::VCGEzv16i8,
2252 => Opcode::VCGEzv2f32,
2253 => Opcode::VCGEzv2i32,
2254 => Opcode::VCGEzv4f16,
2255 => Opcode::VCGEzv4f32,
2256 => Opcode::VCGEzv4i16,
2257 => Opcode::VCGEzv4i32,
2258 => Opcode::VCGEzv8f16,
2259 => Opcode::VCGEzv8i16,
2260 => Opcode::VCGEzv8i8,
2261 => Opcode::VCGTfd,
2262 => Opcode::VCGTfq,
2263 => Opcode::VCGThd,
2264 => Opcode::VCGThq,
2265 => Opcode::VCGTsv16i8,
2266 => Opcode::VCGTsv2i32,
2267 => Opcode::VCGTsv4i16,
2268 => Opcode::VCGTsv4i32,
2269 => Opcode::VCGTsv8i16,
2270 => Opcode::VCGTsv8i8,
2271 => Opcode::VCGTuv16i8,
2272 => Opcode::VCGTuv2i32,
2273 => Opcode::VCGTuv4i16,
2274 => Opcode::VCGTuv4i32,
2275 => Opcode::VCGTuv8i16,
2276 => Opcode::VCGTuv8i8,
2277 => Opcode::VCGTzv16i8,
2278 => Opcode::VCGTzv2f32,
2279 => Opcode::VCGTzv2i32,
2280 => Opcode::VCGTzv4f16,
2281 => Opcode::VCGTzv4f32,
2282 => Opcode::VCGTzv4i16,
2283 => Opcode::VCGTzv4i32,
2284 => Opcode::VCGTzv8f16,
2285 => Opcode::VCGTzv8i16,
2286 => Opcode::VCGTzv8i8,
2287 => Opcode::VCLEzv16i8,
2288 => Opcode::VCLEzv2f32,
2289 => Opcode::VCLEzv2i32,
2290 => Opcode::VCLEzv4f16,
2291 => Opcode::VCLEzv4f32,
2292 => Opcode::VCLEzv4i16,
2293 => Opcode::VCLEzv4i32,
2294 => Opcode::VCLEzv8f16,
2295 => Opcode::VCLEzv8i16,
2296 => Opcode::VCLEzv8i8,
2297 => Opcode::VCLSv16i8,
2298 => Opcode::VCLSv2i32,
2299 => Opcode::VCLSv4i16,
2300 => Opcode::VCLSv4i32,
2301 => Opcode::VCLSv8i16,
2302 => Opcode::VCLSv8i8,
2303 => Opcode::VCLTzv16i8,
2304 => Opcode::VCLTzv2f32,
2305 => Opcode::VCLTzv2i32,
2306 => Opcode::VCLTzv4f16,
2307 => Opcode::VCLTzv4f32,
2308 => Opcode::VCLTzv4i16,
2309 => Opcode::VCLTzv4i32,
2310 => Opcode::VCLTzv8f16,
2311 => Opcode::VCLTzv8i16,
2312 => Opcode::VCLTzv8i8,
2313 => Opcode::VCLZv16i8,
2314 => Opcode::VCLZv2i32,
2315 => Opcode::VCLZv4i16,
2316 => Opcode::VCLZv4i32,
2317 => Opcode::VCLZv8i16,
2318 => Opcode::VCLZv8i8,
2319 => Opcode::VCMLAv2f32,
2320 => Opcode::VCMLAv2f32_indexed,
2321 => Opcode::VCMLAv4f16,
2322 => Opcode::VCMLAv4f16_indexed,
2323 => Opcode::VCMLAv4f32,
2324 => Opcode::VCMLAv4f32_indexed,
2325 => Opcode::VCMLAv8f16,
2326 => Opcode::VCMLAv8f16_indexed,
2327 => Opcode::VCMPD,
2328 => Opcode::VCMPED,
2329 => Opcode::VCMPEH,
2330 => Opcode::VCMPES,
2331 => Opcode::VCMPEZD,
2332 => Opcode::VCMPEZH,
2333 => Opcode::VCMPEZS,
2334 => Opcode::VCMPH,
2335 => Opcode::VCMPS,
2336 => Opcode::VCMPZD,
2337 => Opcode::VCMPZH,
2338 => Opcode::VCMPZS,
2339 => Opcode::VCNTd,
2340 => Opcode::VCNTq,
2341 => Opcode::VCVTANSDf,
2342 => Opcode::VCVTANSDh,
2343 => Opcode::VCVTANSQf,
2344 => Opcode::VCVTANSQh,
2345 => Opcode::VCVTANUDf,
2346 => Opcode::VCVTANUDh,
2347 => Opcode::VCVTANUQf,
2348 => Opcode::VCVTANUQh,
2349 => Opcode::VCVTASD,
2350 => Opcode::VCVTASH,
2351 => Opcode::VCVTASS,
2352 => Opcode::VCVTAUD,
2353 => Opcode::VCVTAUH,
2354 => Opcode::VCVTAUS,
2355 => Opcode::VCVTBDH,
2356 => Opcode::VCVTBHD,
2357 => Opcode::VCVTBHS,
2358 => Opcode::VCVTBSH,
2359 => Opcode::VCVTDS,
2360 => Opcode::VCVTMNSDf,
2361 => Opcode::VCVTMNSDh,
2362 => Opcode::VCVTMNSQf,
2363 => Opcode::VCVTMNSQh,
2364 => Opcode::VCVTMNUDf,
2365 => Opcode::VCVTMNUDh,
2366 => Opcode::VCVTMNUQf,
2367 => Opcode::VCVTMNUQh,
2368 => Opcode::VCVTMSD,
2369 => Opcode::VCVTMSH,
2370 => Opcode::VCVTMSS,
2371 => Opcode::VCVTMUD,
2372 => Opcode::VCVTMUH,
2373 => Opcode::VCVTMUS,
2374 => Opcode::VCVTNNSDf,
2375 => Opcode::VCVTNNSDh,
2376 => Opcode::VCVTNNSQf,
2377 => Opcode::VCVTNNSQh,
2378 => Opcode::VCVTNNUDf,
2379 => Opcode::VCVTNNUDh,
2380 => Opcode::VCVTNNUQf,
2381 => Opcode::VCVTNNUQh,
2382 => Opcode::VCVTNSD,
2383 => Opcode::VCVTNSH,
2384 => Opcode::VCVTNSS,
2385 => Opcode::VCVTNUD,
2386 => Opcode::VCVTNUH,
2387 => Opcode::VCVTNUS,
2388 => Opcode::VCVTPNSDf,
2389 => Opcode::VCVTPNSDh,
2390 => Opcode::VCVTPNSQf,
2391 => Opcode::VCVTPNSQh,
2392 => Opcode::VCVTPNUDf,
2393 => Opcode::VCVTPNUDh,
2394 => Opcode::VCVTPNUQf,
2395 => Opcode::VCVTPNUQh,
2396 => Opcode::VCVTPSD,
2397 => Opcode::VCVTPSH,
2398 => Opcode::VCVTPSS,
2399 => Opcode::VCVTPUD,
2400 => Opcode::VCVTPUH,
2401 => Opcode::VCVTPUS,
2402 => Opcode::VCVTSD,
2403 => Opcode::VCVTTDH,
2404 => Opcode::VCVTTHD,
2405 => Opcode::VCVTTHS,
2406 => Opcode::VCVTTSH,
2407 => Opcode::VCVTf2h,
2408 => Opcode::VCVTf2sd,
2409 => Opcode::VCVTf2sq,
2410 => Opcode::VCVTf2ud,
2411 => Opcode::VCVTf2uq,
2412 => Opcode::VCVTf2xsd,
2413 => Opcode::VCVTf2xsq,
2414 => Opcode::VCVTf2xud,
2415 => Opcode::VCVTf2xuq,
2416 => Opcode::VCVTh2f,
2417 => Opcode::VCVTh2sd,
2418 => Opcode::VCVTh2sq,
2419 => Opcode::VCVTh2ud,
2420 => Opcode::VCVTh2uq,
2421 => Opcode::VCVTh2xsd,
2422 => Opcode::VCVTh2xsq,
2423 => Opcode::VCVTh2xud,
2424 => Opcode::VCVTh2xuq,
2425 => Opcode::VCVTs2fd,
2426 => Opcode::VCVTs2fq,
2427 => Opcode::VCVTs2hd,
2428 => Opcode::VCVTs2hq,
2429 => Opcode::VCVTu2fd,
2430 => Opcode::VCVTu2fq,
2431 => Opcode::VCVTu2hd,
2432 => Opcode::VCVTu2hq,
2433 => Opcode::VCVTxs2fd,
2434 => Opcode::VCVTxs2fq,
2435 => Opcode::VCVTxs2hd,
2436 => Opcode::VCVTxs2hq,
2437 => Opcode::VCVTxu2fd,
2438 => Opcode::VCVTxu2fq,
2439 => Opcode::VCVTxu2hd,
2440 => Opcode::VCVTxu2hq,
2441 => Opcode::VDIVD,
2442 => Opcode::VDIVH,
2443 => Opcode::VDIVS,
2444 => Opcode::VDUP16d,
2445 => Opcode::VDUP16q,
2446 => Opcode::VDUP32d,
2447 => Opcode::VDUP32q,
2448 => Opcode::VDUP8d,
2449 => Opcode::VDUP8q,
2450 => Opcode::VDUPLN16d,
2451 => Opcode::VDUPLN16q,
2452 => Opcode::VDUPLN32d,
2453 => Opcode::VDUPLN32q,
2454 => Opcode::VDUPLN8d,
2455 => Opcode::VDUPLN8q,
2456 => Opcode::VEORd,
2457 => Opcode::VEORq,
2458 => Opcode::VEXTd16,
2459 => Opcode::VEXTd32,
2460 => Opcode::VEXTd8,
2461 => Opcode::VEXTq16,
2462 => Opcode::VEXTq32,
2463 => Opcode::VEXTq64,
2464 => Opcode::VEXTq8,
2465 => Opcode::VFMAD,
2466 => Opcode::VFMAH,
2467 => Opcode::VFMALD,
2468 => Opcode::VFMALDI,
2469 => Opcode::VFMALQ,
2470 => Opcode::VFMALQI,
2471 => Opcode::VFMAS,
2472 => Opcode::VFMAfd,
2473 => Opcode::VFMAfq,
2474 => Opcode::VFMAhd,
2475 => Opcode::VFMAhq,
2476 => Opcode::VFMSD,
2477 => Opcode::VFMSH,
2478 => Opcode::VFMSLD,
2479 => Opcode::VFMSLDI,
2480 => Opcode::VFMSLQ,
2481 => Opcode::VFMSLQI,
2482 => Opcode::VFMSS,
2483 => Opcode::VFMSfd,
2484 => Opcode::VFMSfq,
2485 => Opcode::VFMShd,
2486 => Opcode::VFMShq,
2487 => Opcode::VFNMAD,
2488 => Opcode::VFNMAH,
2489 => Opcode::VFNMAS,
2490 => Opcode::VFNMSD,
2491 => Opcode::VFNMSH,
2492 => Opcode::VFNMSS,
2493 => Opcode::VFP_VMAXNMD,
2494 => Opcode::VFP_VMAXNMH,
2495 => Opcode::VFP_VMAXNMS,
2496 => Opcode::VFP_VMINNMD,
2497 => Opcode::VFP_VMINNMH,
2498 => Opcode::VFP_VMINNMS,
2499 => Opcode::VGETLNi32,
2500 => Opcode::VGETLNs16,
2501 => Opcode::VGETLNs8,
2502 => Opcode::VGETLNu16,
2503 => Opcode::VGETLNu8,
2504 => Opcode::VHADDsv16i8,
2505 => Opcode::VHADDsv2i32,
2506 => Opcode::VHADDsv4i16,
2507 => Opcode::VHADDsv4i32,
2508 => Opcode::VHADDsv8i16,
2509 => Opcode::VHADDsv8i8,
2510 => Opcode::VHADDuv16i8,
2511 => Opcode::VHADDuv2i32,
2512 => Opcode::VHADDuv4i16,
2513 => Opcode::VHADDuv4i32,
2514 => Opcode::VHADDuv8i16,
2515 => Opcode::VHADDuv8i8,
2516 => Opcode::VHSUBsv16i8,
2517 => Opcode::VHSUBsv2i32,
2518 => Opcode::VHSUBsv4i16,
2519 => Opcode::VHSUBsv4i32,
2520 => Opcode::VHSUBsv8i16,
2521 => Opcode::VHSUBsv8i8,
2522 => Opcode::VHSUBuv16i8,
2523 => Opcode::VHSUBuv2i32,
2524 => Opcode::VHSUBuv4i16,
2525 => Opcode::VHSUBuv4i32,
2526 => Opcode::VHSUBuv8i16,
2527 => Opcode::VHSUBuv8i8,
2528 => Opcode::VINSH,
2529 => Opcode::VJCVT,
2530 => Opcode::VLD1DUPd16,
2531 => Opcode::VLD1DUPd16wb_fixed,
2532 => Opcode::VLD1DUPd16wb_register,
2533 => Opcode::VLD1DUPd32,
2534 => Opcode::VLD1DUPd32wb_fixed,
2535 => Opcode::VLD1DUPd32wb_register,
2536 => Opcode::VLD1DUPd8,
2537 => Opcode::VLD1DUPd8wb_fixed,
2538 => Opcode::VLD1DUPd8wb_register,
2539 => Opcode::VLD1DUPq16,
2540 => Opcode::VLD1DUPq16wb_fixed,
2541 => Opcode::VLD1DUPq16wb_register,
2542 => Opcode::VLD1DUPq32,
2543 => Opcode::VLD1DUPq32wb_fixed,
2544 => Opcode::VLD1DUPq32wb_register,
2545 => Opcode::VLD1DUPq8,
2546 => Opcode::VLD1DUPq8wb_fixed,
2547 => Opcode::VLD1DUPq8wb_register,
2548 => Opcode::VLD1LNd16,
2549 => Opcode::VLD1LNd16_UPD,
2550 => Opcode::VLD1LNd32,
2551 => Opcode::VLD1LNd32_UPD,
2552 => Opcode::VLD1LNd8,
2553 => Opcode::VLD1LNd8_UPD,
2554 => Opcode::VLD1LNq16Pseudo,
2555 => Opcode::VLD1LNq16Pseudo_UPD,
2556 => Opcode::VLD1LNq32Pseudo,
2557 => Opcode::VLD1LNq32Pseudo_UPD,
2558 => Opcode::VLD1LNq8Pseudo,
2559 => Opcode::VLD1LNq8Pseudo_UPD,
2560 => Opcode::VLD1d16,
2561 => Opcode::VLD1d16Q,
2562 => Opcode::VLD1d16QPseudo,
2563 => Opcode::VLD1d16QPseudoWB_fixed,
2564 => Opcode::VLD1d16QPseudoWB_register,
2565 => Opcode::VLD1d16Qwb_fixed,
2566 => Opcode::VLD1d16Qwb_register,
2567 => Opcode::VLD1d16T,
2568 => Opcode::VLD1d16TPseudo,
2569 => Opcode::VLD1d16TPseudoWB_fixed,
2570 => Opcode::VLD1d16TPseudoWB_register,
2571 => Opcode::VLD1d16Twb_fixed,
2572 => Opcode::VLD1d16Twb_register,
2573 => Opcode::VLD1d16wb_fixed,
2574 => Opcode::VLD1d16wb_register,
2575 => Opcode::VLD1d32,
2576 => Opcode::VLD1d32Q,
2577 => Opcode::VLD1d32QPseudo,
2578 => Opcode::VLD1d32QPseudoWB_fixed,
2579 => Opcode::VLD1d32QPseudoWB_register,
2580 => Opcode::VLD1d32Qwb_fixed,
2581 => Opcode::VLD1d32Qwb_register,
2582 => Opcode::VLD1d32T,
2583 => Opcode::VLD1d32TPseudo,
2584 => Opcode::VLD1d32TPseudoWB_fixed,
2585 => Opcode::VLD1d32TPseudoWB_register,
2586 => Opcode::VLD1d32Twb_fixed,
2587 => Opcode::VLD1d32Twb_register,
2588 => Opcode::VLD1d32wb_fixed,
2589 => Opcode::VLD1d32wb_register,
2590 => Opcode::VLD1d64,
2591 => Opcode::VLD1d64Q,
2592 => Opcode::VLD1d64QPseudo,
2593 => Opcode::VLD1d64QPseudoWB_fixed,
2594 => Opcode::VLD1d64QPseudoWB_register,
2595 => Opcode::VLD1d64Qwb_fixed,
2596 => Opcode::VLD1d64Qwb_register,
2597 => Opcode::VLD1d64T,
2598 => Opcode::VLD1d64TPseudo,
2599 => Opcode::VLD1d64TPseudoWB_fixed,
2600 => Opcode::VLD1d64TPseudoWB_register,
2601 => Opcode::VLD1d64Twb_fixed,
2602 => Opcode::VLD1d64Twb_register,
2603 => Opcode::VLD1d64wb_fixed,
2604 => Opcode::VLD1d64wb_register,
2605 => Opcode::VLD1d8,
2606 => Opcode::VLD1d8Q,
2607 => Opcode::VLD1d8QPseudo,
2608 => Opcode::VLD1d8QPseudoWB_fixed,
2609 => Opcode::VLD1d8QPseudoWB_register,
2610 => Opcode::VLD1d8Qwb_fixed,
2611 => Opcode::VLD1d8Qwb_register,
2612 => Opcode::VLD1d8T,
2613 => Opcode::VLD1d8TPseudo,
2614 => Opcode::VLD1d8TPseudoWB_fixed,
2615 => Opcode::VLD1d8TPseudoWB_register,
2616 => Opcode::VLD1d8Twb_fixed,
2617 => Opcode::VLD1d8Twb_register,
2618 => Opcode::VLD1d8wb_fixed,
2619 => Opcode::VLD1d8wb_register,
2620 => Opcode::VLD1q16,
2621 => Opcode::VLD1q16HighQPseudo,
2622 => Opcode::VLD1q16HighQPseudo_UPD,
2623 => Opcode::VLD1q16HighTPseudo,
2624 => Opcode::VLD1q16HighTPseudo_UPD,
2625 => Opcode::VLD1q16LowQPseudo_UPD,
2626 => Opcode::VLD1q16LowTPseudo_UPD,
2627 => Opcode::VLD1q16wb_fixed,
2628 => Opcode::VLD1q16wb_register,
2629 => Opcode::VLD1q32,
2630 => Opcode::VLD1q32HighQPseudo,
2631 => Opcode::VLD1q32HighQPseudo_UPD,
2632 => Opcode::VLD1q32HighTPseudo,
2633 => Opcode::VLD1q32HighTPseudo_UPD,
2634 => Opcode::VLD1q32LowQPseudo_UPD,
2635 => Opcode::VLD1q32LowTPseudo_UPD,
2636 => Opcode::VLD1q32wb_fixed,
2637 => Opcode::VLD1q32wb_register,
2638 => Opcode::VLD1q64,
2639 => Opcode::VLD1q64HighQPseudo,
2640 => Opcode::VLD1q64HighQPseudo_UPD,
2641 => Opcode::VLD1q64HighTPseudo,
2642 => Opcode::VLD1q64HighTPseudo_UPD,
2643 => Opcode::VLD1q64LowQPseudo_UPD,
2644 => Opcode::VLD1q64LowTPseudo_UPD,
2645 => Opcode::VLD1q64wb_fixed,
2646 => Opcode::VLD1q64wb_register,
2647 => Opcode::VLD1q8,
2648 => Opcode::VLD1q8HighQPseudo,
2649 => Opcode::VLD1q8HighQPseudo_UPD,
2650 => Opcode::VLD1q8HighTPseudo,
2651 => Opcode::VLD1q8HighTPseudo_UPD,
2652 => Opcode::VLD1q8LowQPseudo_UPD,
2653 => Opcode::VLD1q8LowTPseudo_UPD,
2654 => Opcode::VLD1q8wb_fixed,
2655 => Opcode::VLD1q8wb_register,
2656 => Opcode::VLD2DUPd16,
2657 => Opcode::VLD2DUPd16wb_fixed,
2658 => Opcode::VLD2DUPd16wb_register,
2659 => Opcode::VLD2DUPd16x2,
2660 => Opcode::VLD2DUPd16x2wb_fixed,
2661 => Opcode::VLD2DUPd16x2wb_register,
2662 => Opcode::VLD2DUPd32,
2663 => Opcode::VLD2DUPd32wb_fixed,
2664 => Opcode::VLD2DUPd32wb_register,
2665 => Opcode::VLD2DUPd32x2,
2666 => Opcode::VLD2DUPd32x2wb_fixed,
2667 => Opcode::VLD2DUPd32x2wb_register,
2668 => Opcode::VLD2DUPd8,
2669 => Opcode::VLD2DUPd8wb_fixed,
2670 => Opcode::VLD2DUPd8wb_register,
2671 => Opcode::VLD2DUPd8x2,
2672 => Opcode::VLD2DUPd8x2wb_fixed,
2673 => Opcode::VLD2DUPd8x2wb_register,
2674 => Opcode::VLD2DUPq16EvenPseudo,
2675 => Opcode::VLD2DUPq16OddPseudo,
2676 => Opcode::VLD2DUPq16OddPseudoWB_fixed,
2677 => Opcode::VLD2DUPq16OddPseudoWB_register,
2678 => Opcode::VLD2DUPq32EvenPseudo,
2679 => Opcode::VLD2DUPq32OddPseudo,
2680 => Opcode::VLD2DUPq32OddPseudoWB_fixed,
2681 => Opcode::VLD2DUPq32OddPseudoWB_register,
2682 => Opcode::VLD2DUPq8EvenPseudo,
2683 => Opcode::VLD2DUPq8OddPseudo,
2684 => Opcode::VLD2DUPq8OddPseudoWB_fixed,
2685 => Opcode::VLD2DUPq8OddPseudoWB_register,
2686 => Opcode::VLD2LNd16,
2687 => Opcode::VLD2LNd16Pseudo,
2688 => Opcode::VLD2LNd16Pseudo_UPD,
2689 => Opcode::VLD2LNd16_UPD,
2690 => Opcode::VLD2LNd32,
2691 => Opcode::VLD2LNd32Pseudo,
2692 => Opcode::VLD2LNd32Pseudo_UPD,
2693 => Opcode::VLD2LNd32_UPD,
2694 => Opcode::VLD2LNd8,
2695 => Opcode::VLD2LNd8Pseudo,
2696 => Opcode::VLD2LNd8Pseudo_UPD,
2697 => Opcode::VLD2LNd8_UPD,
2698 => Opcode::VLD2LNq16,
2699 => Opcode::VLD2LNq16Pseudo,
2700 => Opcode::VLD2LNq16Pseudo_UPD,
2701 => Opcode::VLD2LNq16_UPD,
2702 => Opcode::VLD2LNq32,
2703 => Opcode::VLD2LNq32Pseudo,
2704 => Opcode::VLD2LNq32Pseudo_UPD,
2705 => Opcode::VLD2LNq32_UPD,
2706 => Opcode::VLD2b16,
2707 => Opcode::VLD2b16wb_fixed,
2708 => Opcode::VLD2b16wb_register,
2709 => Opcode::VLD2b32,
2710 => Opcode::VLD2b32wb_fixed,
2711 => Opcode::VLD2b32wb_register,
2712 => Opcode::VLD2b8,
2713 => Opcode::VLD2b8wb_fixed,
2714 => Opcode::VLD2b8wb_register,
2715 => Opcode::VLD2d16,
2716 => Opcode::VLD2d16wb_fixed,
2717 => Opcode::VLD2d16wb_register,
2718 => Opcode::VLD2d32,
2719 => Opcode::VLD2d32wb_fixed,
2720 => Opcode::VLD2d32wb_register,
2721 => Opcode::VLD2d8,
2722 => Opcode::VLD2d8wb_fixed,
2723 => Opcode::VLD2d8wb_register,
2724 => Opcode::VLD2q16,
2725 => Opcode::VLD2q16Pseudo,
2726 => Opcode::VLD2q16PseudoWB_fixed,
2727 => Opcode::VLD2q16PseudoWB_register,
2728 => Opcode::VLD2q16wb_fixed,
2729 => Opcode::VLD2q16wb_register,
2730 => Opcode::VLD2q32,
2731 => Opcode::VLD2q32Pseudo,
2732 => Opcode::VLD2q32PseudoWB_fixed,
2733 => Opcode::VLD2q32PseudoWB_register,
2734 => Opcode::VLD2q32wb_fixed,
2735 => Opcode::VLD2q32wb_register,
2736 => Opcode::VLD2q8,
2737 => Opcode::VLD2q8Pseudo,
2738 => Opcode::VLD2q8PseudoWB_fixed,
2739 => Opcode::VLD2q8PseudoWB_register,
2740 => Opcode::VLD2q8wb_fixed,
2741 => Opcode::VLD2q8wb_register,
2742 => Opcode::VLD3DUPd16,
2743 => Opcode::VLD3DUPd16Pseudo,
2744 => Opcode::VLD3DUPd16Pseudo_UPD,
2745 => Opcode::VLD3DUPd16_UPD,
2746 => Opcode::VLD3DUPd32,
2747 => Opcode::VLD3DUPd32Pseudo,
2748 => Opcode::VLD3DUPd32Pseudo_UPD,
2749 => Opcode::VLD3DUPd32_UPD,
2750 => Opcode::VLD3DUPd8,
2751 => Opcode::VLD3DUPd8Pseudo,
2752 => Opcode::VLD3DUPd8Pseudo_UPD,
2753 => Opcode::VLD3DUPd8_UPD,
2754 => Opcode::VLD3DUPq16,
2755 => Opcode::VLD3DUPq16EvenPseudo,
2756 => Opcode::VLD3DUPq16OddPseudo,
2757 => Opcode::VLD3DUPq16OddPseudo_UPD,
2758 => Opcode::VLD3DUPq16_UPD,
2759 => Opcode::VLD3DUPq32,
2760 => Opcode::VLD3DUPq32EvenPseudo,
2761 => Opcode::VLD3DUPq32OddPseudo,
2762 => Opcode::VLD3DUPq32OddPseudo_UPD,
2763 => Opcode::VLD3DUPq32_UPD,
2764 => Opcode::VLD3DUPq8,
2765 => Opcode::VLD3DUPq8EvenPseudo,
2766 => Opcode::VLD3DUPq8OddPseudo,
2767 => Opcode::VLD3DUPq8OddPseudo_UPD,
2768 => Opcode::VLD3DUPq8_UPD,
2769 => Opcode::VLD3LNd16,
2770 => Opcode::VLD3LNd16Pseudo,
2771 => Opcode::VLD3LNd16Pseudo_UPD,
2772 => Opcode::VLD3LNd16_UPD,
2773 => Opcode::VLD3LNd32,
2774 => Opcode::VLD3LNd32Pseudo,
2775 => Opcode::VLD3LNd32Pseudo_UPD,
2776 => Opcode::VLD3LNd32_UPD,
2777 => Opcode::VLD3LNd8,
2778 => Opcode::VLD3LNd8Pseudo,
2779 => Opcode::VLD3LNd8Pseudo_UPD,
2780 => Opcode::VLD3LNd8_UPD,
2781 => Opcode::VLD3LNq16,
2782 => Opcode::VLD3LNq16Pseudo,
2783 => Opcode::VLD3LNq16Pseudo_UPD,
2784 => Opcode::VLD3LNq16_UPD,
2785 => Opcode::VLD3LNq32,
2786 => Opcode::VLD3LNq32Pseudo,
2787 => Opcode::VLD3LNq32Pseudo_UPD,
2788 => Opcode::VLD3LNq32_UPD,
2789 => Opcode::VLD3d16,
2790 => Opcode::VLD3d16Pseudo,
2791 => Opcode::VLD3d16Pseudo_UPD,
2792 => Opcode::VLD3d16_UPD,
2793 => Opcode::VLD3d32,
2794 => Opcode::VLD3d32Pseudo,
2795 => Opcode::VLD3d32Pseudo_UPD,
2796 => Opcode::VLD3d32_UPD,
2797 => Opcode::VLD3d8,
2798 => Opcode::VLD3d8Pseudo,
2799 => Opcode::VLD3d8Pseudo_UPD,
2800 => Opcode::VLD3d8_UPD,
2801 => Opcode::VLD3q16,
2802 => Opcode::VLD3q16Pseudo_UPD,
2803 => Opcode::VLD3q16_UPD,
2804 => Opcode::VLD3q16oddPseudo,
2805 => Opcode::VLD3q16oddPseudo_UPD,
2806 => Opcode::VLD3q32,
2807 => Opcode::VLD3q32Pseudo_UPD,
2808 => Opcode::VLD3q32_UPD,
2809 => Opcode::VLD3q32oddPseudo,
2810 => Opcode::VLD3q32oddPseudo_UPD,
2811 => Opcode::VLD3q8,
2812 => Opcode::VLD3q8Pseudo_UPD,
2813 => Opcode::VLD3q8_UPD,
2814 => Opcode::VLD3q8oddPseudo,
2815 => Opcode::VLD3q8oddPseudo_UPD,
2816 => Opcode::VLD4DUPd16,
2817 => Opcode::VLD4DUPd16Pseudo,
2818 => Opcode::VLD4DUPd16Pseudo_UPD,
2819 => Opcode::VLD4DUPd16_UPD,
2820 => Opcode::VLD4DUPd32,
2821 => Opcode::VLD4DUPd32Pseudo,
2822 => Opcode::VLD4DUPd32Pseudo_UPD,
2823 => Opcode::VLD4DUPd32_UPD,
2824 => Opcode::VLD4DUPd8,
2825 => Opcode::VLD4DUPd8Pseudo,
2826 => Opcode::VLD4DUPd8Pseudo_UPD,
2827 => Opcode::VLD4DUPd8_UPD,
2828 => Opcode::VLD4DUPq16,
2829 => Opcode::VLD4DUPq16EvenPseudo,
2830 => Opcode::VLD4DUPq16OddPseudo,
2831 => Opcode::VLD4DUPq16OddPseudo_UPD,
2832 => Opcode::VLD4DUPq16_UPD,
2833 => Opcode::VLD4DUPq32,
2834 => Opcode::VLD4DUPq32EvenPseudo,
2835 => Opcode::VLD4DUPq32OddPseudo,
2836 => Opcode::VLD4DUPq32OddPseudo_UPD,
2837 => Opcode::VLD4DUPq32_UPD,
2838 => Opcode::VLD4DUPq8,
2839 => Opcode::VLD4DUPq8EvenPseudo,
2840 => Opcode::VLD4DUPq8OddPseudo,
2841 => Opcode::VLD4DUPq8OddPseudo_UPD,
2842 => Opcode::VLD4DUPq8_UPD,
2843 => Opcode::VLD4LNd16,
2844 => Opcode::VLD4LNd16Pseudo,
2845 => Opcode::VLD4LNd16Pseudo_UPD,
2846 => Opcode::VLD4LNd16_UPD,
2847 => Opcode::VLD4LNd32,
2848 => Opcode::VLD4LNd32Pseudo,
2849 => Opcode::VLD4LNd32Pseudo_UPD,
2850 => Opcode::VLD4LNd32_UPD,
2851 => Opcode::VLD4LNd8,
2852 => Opcode::VLD4LNd8Pseudo,
2853 => Opcode::VLD4LNd8Pseudo_UPD,
2854 => Opcode::VLD4LNd8_UPD,
2855 => Opcode::VLD4LNq16,
2856 => Opcode::VLD4LNq16Pseudo,
2857 => Opcode::VLD4LNq16Pseudo_UPD,
2858 => Opcode::VLD4LNq16_UPD,
2859 => Opcode::VLD4LNq32,
2860 => Opcode::VLD4LNq32Pseudo,
2861 => Opcode::VLD4LNq32Pseudo_UPD,
2862 => Opcode::VLD4LNq32_UPD,
2863 => Opcode::VLD4d16,
2864 => Opcode::VLD4d16Pseudo,
2865 => Opcode::VLD4d16Pseudo_UPD,
2866 => Opcode::VLD4d16_UPD,
2867 => Opcode::VLD4d32,
2868 => Opcode::VLD4d32Pseudo,
2869 => Opcode::VLD4d32Pseudo_UPD,
2870 => Opcode::VLD4d32_UPD,
2871 => Opcode::VLD4d8,
2872 => Opcode::VLD4d8Pseudo,
2873 => Opcode::VLD4d8Pseudo_UPD,
2874 => Opcode::VLD4d8_UPD,
2875 => Opcode::VLD4q16,
2876 => Opcode::VLD4q16Pseudo_UPD,
2877 => Opcode::VLD4q16_UPD,
2878 => Opcode::VLD4q16oddPseudo,
2879 => Opcode::VLD4q16oddPseudo_UPD,
2880 => Opcode::VLD4q32,
2881 => Opcode::VLD4q32Pseudo_UPD,
2882 => Opcode::VLD4q32_UPD,
2883 => Opcode::VLD4q32oddPseudo,
2884 => Opcode::VLD4q32oddPseudo_UPD,
2885 => Opcode::VLD4q8,
2886 => Opcode::VLD4q8Pseudo_UPD,
2887 => Opcode::VLD4q8_UPD,
2888 => Opcode::VLD4q8oddPseudo,
2889 => Opcode::VLD4q8oddPseudo_UPD,
2890 => Opcode::VLDMDDB_UPD,
2891 => Opcode::VLDMDIA,
2892 => Opcode::VLDMDIA_UPD,
2893 => Opcode::VLDMQIA,
2894 => Opcode::VLDMSDB_UPD,
2895 => Opcode::VLDMSIA,
2896 => Opcode::VLDMSIA_UPD,
2897 => Opcode::VLDRD,
2898 => Opcode::VLDRH,
2899 => Opcode::VLDRS,
2900 => Opcode::VLDR_FPCXTNS_off,
2901 => Opcode::VLDR_FPCXTNS_post,
2902 => Opcode::VLDR_FPCXTNS_pre,
2903 => Opcode::VLDR_FPCXTS_off,
2904 => Opcode::VLDR_FPCXTS_post,
2905 => Opcode::VLDR_FPCXTS_pre,
2906 => Opcode::VLDR_FPSCR_NZCVQC_off,
2907 => Opcode::VLDR_FPSCR_NZCVQC_post,
2908 => Opcode::VLDR_FPSCR_NZCVQC_pre,
2909 => Opcode::VLDR_FPSCR_off,
2910 => Opcode::VLDR_FPSCR_post,
2911 => Opcode::VLDR_FPSCR_pre,
2912 => Opcode::VLDR_P0_off,
2913 => Opcode::VLDR_P0_post,
2914 => Opcode::VLDR_P0_pre,
2915 => Opcode::VLDR_VPR_off,
2916 => Opcode::VLDR_VPR_post,
2917 => Opcode::VLDR_VPR_pre,
2918 => Opcode::VLLDM,
2919 => Opcode::VLLDM_T2,
2920 => Opcode::VLSTM,
2921 => Opcode::VLSTM_T2,
2922 => Opcode::VMAXfd,
2923 => Opcode::VMAXfq,
2924 => Opcode::VMAXhd,
2925 => Opcode::VMAXhq,
2926 => Opcode::VMAXsv16i8,
2927 => Opcode::VMAXsv2i32,
2928 => Opcode::VMAXsv4i16,
2929 => Opcode::VMAXsv4i32,
2930 => Opcode::VMAXsv8i16,
2931 => Opcode::VMAXsv8i8,
2932 => Opcode::VMAXuv16i8,
2933 => Opcode::VMAXuv2i32,
2934 => Opcode::VMAXuv4i16,
2935 => Opcode::VMAXuv4i32,
2936 => Opcode::VMAXuv8i16,
2937 => Opcode::VMAXuv8i8,
2938 => Opcode::VMINfd,
2939 => Opcode::VMINfq,
2940 => Opcode::VMINhd,
2941 => Opcode::VMINhq,
2942 => Opcode::VMINsv16i8,
2943 => Opcode::VMINsv2i32,
2944 => Opcode::VMINsv4i16,
2945 => Opcode::VMINsv4i32,
2946 => Opcode::VMINsv8i16,
2947 => Opcode::VMINsv8i8,
2948 => Opcode::VMINuv16i8,
2949 => Opcode::VMINuv2i32,
2950 => Opcode::VMINuv4i16,
2951 => Opcode::VMINuv4i32,
2952 => Opcode::VMINuv8i16,
2953 => Opcode::VMINuv8i8,
2954 => Opcode::VMLAD,
2955 => Opcode::VMLAH,
2956 => Opcode::VMLALslsv2i32,
2957 => Opcode::VMLALslsv4i16,
2958 => Opcode::VMLALsluv2i32,
2959 => Opcode::VMLALsluv4i16,
2960 => Opcode::VMLALsv2i64,
2961 => Opcode::VMLALsv4i32,
2962 => Opcode::VMLALsv8i16,
2963 => Opcode::VMLALuv2i64,
2964 => Opcode::VMLALuv4i32,
2965 => Opcode::VMLALuv8i16,
2966 => Opcode::VMLAS,
2967 => Opcode::VMLAfd,
2968 => Opcode::VMLAfq,
2969 => Opcode::VMLAhd,
2970 => Opcode::VMLAhq,
2971 => Opcode::VMLAslfd,
2972 => Opcode::VMLAslfq,
2973 => Opcode::VMLAslhd,
2974 => Opcode::VMLAslhq,
2975 => Opcode::VMLAslv2i32,
2976 => Opcode::VMLAslv4i16,
2977 => Opcode::VMLAslv4i32,
2978 => Opcode::VMLAslv8i16,
2979 => Opcode::VMLAv16i8,
2980 => Opcode::VMLAv2i32,
2981 => Opcode::VMLAv4i16,
2982 => Opcode::VMLAv4i32,
2983 => Opcode::VMLAv8i16,
2984 => Opcode::VMLAv8i8,
2985 => Opcode::VMLSD,
2986 => Opcode::VMLSH,
2987 => Opcode::VMLSLslsv2i32,
2988 => Opcode::VMLSLslsv4i16,
2989 => Opcode::VMLSLsluv2i32,
2990 => Opcode::VMLSLsluv4i16,
2991 => Opcode::VMLSLsv2i64,
2992 => Opcode::VMLSLsv4i32,
2993 => Opcode::VMLSLsv8i16,
2994 => Opcode::VMLSLuv2i64,
2995 => Opcode::VMLSLuv4i32,
2996 => Opcode::VMLSLuv8i16,
2997 => Opcode::VMLSS,
2998 => Opcode::VMLSfd,
2999 => Opcode::VMLSfq,
3000 => Opcode::VMLShd,
3001 => Opcode::VMLShq,
3002 => Opcode::VMLSslfd,
3003 => Opcode::VMLSslfq,
3004 => Opcode::VMLSslhd,
3005 => Opcode::VMLSslhq,
3006 => Opcode::VMLSslv2i32,
3007 => Opcode::VMLSslv4i16,
3008 => Opcode::VMLSslv4i32,
3009 => Opcode::VMLSslv8i16,
3010 => Opcode::VMLSv16i8,
3011 => Opcode::VMLSv2i32,
3012 => Opcode::VMLSv4i16,
3013 => Opcode::VMLSv4i32,
3014 => Opcode::VMLSv8i16,
3015 => Opcode::VMLSv8i8,
3016 => Opcode::VMMLA,
3017 => Opcode::VMOVD,
3018 => Opcode::VMOVDRR,
3019 => Opcode::VMOVH,
3020 => Opcode::VMOVHR,
3021 => Opcode::VMOVLsv2i64,
3022 => Opcode::VMOVLsv4i32,
3023 => Opcode::VMOVLsv8i16,
3024 => Opcode::VMOVLuv2i64,
3025 => Opcode::VMOVLuv4i32,
3026 => Opcode::VMOVLuv8i16,
3027 => Opcode::VMOVNv2i32,
3028 => Opcode::VMOVNv4i16,
3029 => Opcode::VMOVNv8i8,
3030 => Opcode::VMOVRH,
3031 => Opcode::VMOVRRD,
3032 => Opcode::VMOVRRS,
3033 => Opcode::VMOVRS,
3034 => Opcode::VMOVS,
3035 => Opcode::VMOVSR,
3036 => Opcode::VMOVSRR,
3037 => Opcode::VMOVv16i8,
3038 => Opcode::VMOVv1i64,
3039 => Opcode::VMOVv2f32,
3040 => Opcode::VMOVv2i32,
3041 => Opcode::VMOVv2i64,
3042 => Opcode::VMOVv4f32,
3043 => Opcode::VMOVv4i16,
3044 => Opcode::VMOVv4i32,
3045 => Opcode::VMOVv8i16,
3046 => Opcode::VMOVv8i8,
3047 => Opcode::VMRS,
3048 => Opcode::VMRS_FPCXTNS,
3049 => Opcode::VMRS_FPCXTS,
3050 => Opcode::VMRS_FPEXC,
3051 => Opcode::VMRS_FPINST,
3052 => Opcode::VMRS_FPINST2,
3053 => Opcode::VMRS_FPSCR_NZCVQC,
3054 => Opcode::VMRS_FPSID,
3055 => Opcode::VMRS_MVFR0,
3056 => Opcode::VMRS_MVFR1,
3057 => Opcode::VMRS_MVFR2,
3058 => Opcode::VMRS_P0,
3059 => Opcode::VMRS_VPR,
3060 => Opcode::VMSR,
3061 => Opcode::VMSR_FPCXTNS,
3062 => Opcode::VMSR_FPCXTS,
3063 => Opcode::VMSR_FPEXC,
3064 => Opcode::VMSR_FPINST,
3065 => Opcode::VMSR_FPINST2,
3066 => Opcode::VMSR_FPSCR_NZCVQC,
3067 => Opcode::VMSR_FPSID,
3068 => Opcode::VMSR_P0,
3069 => Opcode::VMSR_VPR,
3070 => Opcode::VMULD,
3071 => Opcode::VMULH,
3072 => Opcode::VMULLp64,
3073 => Opcode::VMULLp8,
3074 => Opcode::VMULLslsv2i32,
3075 => Opcode::VMULLslsv4i16,
3076 => Opcode::VMULLsluv2i32,
3077 => Opcode::VMULLsluv4i16,
3078 => Opcode::VMULLsv2i64,
3079 => Opcode::VMULLsv4i32,
3080 => Opcode::VMULLsv8i16,
3081 => Opcode::VMULLuv2i64,
3082 => Opcode::VMULLuv4i32,
3083 => Opcode::VMULLuv8i16,
3084 => Opcode::VMULS,
3085 => Opcode::VMULfd,
3086 => Opcode::VMULfq,
3087 => Opcode::VMULhd,
3088 => Opcode::VMULhq,
3089 => Opcode::VMULpd,
3090 => Opcode::VMULpq,
3091 => Opcode::VMULslfd,
3092 => Opcode::VMULslfq,
3093 => Opcode::VMULslhd,
3094 => Opcode::VMULslhq,
3095 => Opcode::VMULslv2i32,
3096 => Opcode::VMULslv4i16,
3097 => Opcode::VMULslv4i32,
3098 => Opcode::VMULslv8i16,
3099 => Opcode::VMULv16i8,
3100 => Opcode::VMULv2i32,
3101 => Opcode::VMULv4i16,
3102 => Opcode::VMULv4i32,
3103 => Opcode::VMULv8i16,
3104 => Opcode::VMULv8i8,
3105 => Opcode::VMVNd,
3106 => Opcode::VMVNq,
3107 => Opcode::VMVNv2i32,
3108 => Opcode::VMVNv4i16,
3109 => Opcode::VMVNv4i32,
3110 => Opcode::VMVNv8i16,
3111 => Opcode::VNEGD,
3112 => Opcode::VNEGH,
3113 => Opcode::VNEGS,
3114 => Opcode::VNEGf32q,
3115 => Opcode::VNEGfd,
3116 => Opcode::VNEGhd,
3117 => Opcode::VNEGhq,
3118 => Opcode::VNEGs16d,
3119 => Opcode::VNEGs16q,
3120 => Opcode::VNEGs32d,
3121 => Opcode::VNEGs32q,
3122 => Opcode::VNEGs8d,
3123 => Opcode::VNEGs8q,
3124 => Opcode::VNMLAD,
3125 => Opcode::VNMLAH,
3126 => Opcode::VNMLAS,
3127 => Opcode::VNMLSD,
3128 => Opcode::VNMLSH,
3129 => Opcode::VNMLSS,
3130 => Opcode::VNMULD,
3131 => Opcode::VNMULH,
3132 => Opcode::VNMULS,
3133 => Opcode::VORNd,
3134 => Opcode::VORNq,
3135 => Opcode::VORRd,
3136 => Opcode::VORRiv2i32,
3137 => Opcode::VORRiv4i16,
3138 => Opcode::VORRiv4i32,
3139 => Opcode::VORRiv8i16,
3140 => Opcode::VORRq,
3141 => Opcode::VPADALsv16i8,
3142 => Opcode::VPADALsv2i32,
3143 => Opcode::VPADALsv4i16,
3144 => Opcode::VPADALsv4i32,
3145 => Opcode::VPADALsv8i16,
3146 => Opcode::VPADALsv8i8,
3147 => Opcode::VPADALuv16i8,
3148 => Opcode::VPADALuv2i32,
3149 => Opcode::VPADALuv4i16,
3150 => Opcode::VPADALuv4i32,
3151 => Opcode::VPADALuv8i16,
3152 => Opcode::VPADALuv8i8,
3153 => Opcode::VPADDLsv16i8,
3154 => Opcode::VPADDLsv2i32,
3155 => Opcode::VPADDLsv4i16,
3156 => Opcode::VPADDLsv4i32,
3157 => Opcode::VPADDLsv8i16,
3158 => Opcode::VPADDLsv8i8,
3159 => Opcode::VPADDLuv16i8,
3160 => Opcode::VPADDLuv2i32,
3161 => Opcode::VPADDLuv4i16,
3162 => Opcode::VPADDLuv4i32,
3163 => Opcode::VPADDLuv8i16,
3164 => Opcode::VPADDLuv8i8,
3165 => Opcode::VPADDf,
3166 => Opcode::VPADDh,
3167 => Opcode::VPADDi16,
3168 => Opcode::VPADDi32,
3169 => Opcode::VPADDi8,
3170 => Opcode::VPMAXf,
3171 => Opcode::VPMAXh,
3172 => Opcode::VPMAXs16,
3173 => Opcode::VPMAXs32,
3174 => Opcode::VPMAXs8,
3175 => Opcode::VPMAXu16,
3176 => Opcode::VPMAXu32,
3177 => Opcode::VPMAXu8,
3178 => Opcode::VPMINf,
3179 => Opcode::VPMINh,
3180 => Opcode::VPMINs16,
3181 => Opcode::VPMINs32,
3182 => Opcode::VPMINs8,
3183 => Opcode::VPMINu16,
3184 => Opcode::VPMINu32,
3185 => Opcode::VPMINu8,
3186 => Opcode::VQABSv16i8,
3187 => Opcode::VQABSv2i32,
3188 => Opcode::VQABSv4i16,
3189 => Opcode::VQABSv4i32,
3190 => Opcode::VQABSv8i16,
3191 => Opcode::VQABSv8i8,
3192 => Opcode::VQADDsv16i8,
3193 => Opcode::VQADDsv1i64,
3194 => Opcode::VQADDsv2i32,
3195 => Opcode::VQADDsv2i64,
3196 => Opcode::VQADDsv4i16,
3197 => Opcode::VQADDsv4i32,
3198 => Opcode::VQADDsv8i16,
3199 => Opcode::VQADDsv8i8,
3200 => Opcode::VQADDuv16i8,
3201 => Opcode::VQADDuv1i64,
3202 => Opcode::VQADDuv2i32,
3203 => Opcode::VQADDuv2i64,
3204 => Opcode::VQADDuv4i16,
3205 => Opcode::VQADDuv4i32,
3206 => Opcode::VQADDuv8i16,
3207 => Opcode::VQADDuv8i8,
3208 => Opcode::VQDMLALslv2i32,
3209 => Opcode::VQDMLALslv4i16,
3210 => Opcode::VQDMLALv2i64,
3211 => Opcode::VQDMLALv4i32,
3212 => Opcode::VQDMLSLslv2i32,
3213 => Opcode::VQDMLSLslv4i16,
3214 => Opcode::VQDMLSLv2i64,
3215 => Opcode::VQDMLSLv4i32,
3216 => Opcode::VQDMULHslv2i32,
3217 => Opcode::VQDMULHslv4i16,
3218 => Opcode::VQDMULHslv4i32,
3219 => Opcode::VQDMULHslv8i16,
3220 => Opcode::VQDMULHv2i32,
3221 => Opcode::VQDMULHv4i16,
3222 => Opcode::VQDMULHv4i32,
3223 => Opcode::VQDMULHv8i16,
3224 => Opcode::VQDMULLslv2i32,
3225 => Opcode::VQDMULLslv4i16,
3226 => Opcode::VQDMULLv2i64,
3227 => Opcode::VQDMULLv4i32,
3228 => Opcode::VQMOVNsuv2i32,
3229 => Opcode::VQMOVNsuv4i16,
3230 => Opcode::VQMOVNsuv8i8,
3231 => Opcode::VQMOVNsv2i32,
3232 => Opcode::VQMOVNsv4i16,
3233 => Opcode::VQMOVNsv8i8,
3234 => Opcode::VQMOVNuv2i32,
3235 => Opcode::VQMOVNuv4i16,
3236 => Opcode::VQMOVNuv8i8,
3237 => Opcode::VQNEGv16i8,
3238 => Opcode::VQNEGv2i32,
3239 => Opcode::VQNEGv4i16,
3240 => Opcode::VQNEGv4i32,
3241 => Opcode::VQNEGv8i16,
3242 => Opcode::VQNEGv8i8,
3243 => Opcode::VQRDMLAHslv2i32,
3244 => Opcode::VQRDMLAHslv4i16,
3245 => Opcode::VQRDMLAHslv4i32,
3246 => Opcode::VQRDMLAHslv8i16,
3247 => Opcode::VQRDMLAHv2i32,
3248 => Opcode::VQRDMLAHv4i16,
3249 => Opcode::VQRDMLAHv4i32,
3250 => Opcode::VQRDMLAHv8i16,
3251 => Opcode::VQRDMLSHslv2i32,
3252 => Opcode::VQRDMLSHslv4i16,
3253 => Opcode::VQRDMLSHslv4i32,
3254 => Opcode::VQRDMLSHslv8i16,
3255 => Opcode::VQRDMLSHv2i32,
3256 => Opcode::VQRDMLSHv4i16,
3257 => Opcode::VQRDMLSHv4i32,
3258 => Opcode::VQRDMLSHv8i16,
3259 => Opcode::VQRDMULHslv2i32,
3260 => Opcode::VQRDMULHslv4i16,
3261 => Opcode::VQRDMULHslv4i32,
3262 => Opcode::VQRDMULHslv8i16,
3263 => Opcode::VQRDMULHv2i32,
3264 => Opcode::VQRDMULHv4i16,
3265 => Opcode::VQRDMULHv4i32,
3266 => Opcode::VQRDMULHv8i16,
3267 => Opcode::VQRSHLsv16i8,
3268 => Opcode::VQRSHLsv1i64,
3269 => Opcode::VQRSHLsv2i32,
3270 => Opcode::VQRSHLsv2i64,
3271 => Opcode::VQRSHLsv4i16,
3272 => Opcode::VQRSHLsv4i32,
3273 => Opcode::VQRSHLsv8i16,
3274 => Opcode::VQRSHLsv8i8,
3275 => Opcode::VQRSHLuv16i8,
3276 => Opcode::VQRSHLuv1i64,
3277 => Opcode::VQRSHLuv2i32,
3278 => Opcode::VQRSHLuv2i64,
3279 => Opcode::VQRSHLuv4i16,
3280 => Opcode::VQRSHLuv4i32,
3281 => Opcode::VQRSHLuv8i16,
3282 => Opcode::VQRSHLuv8i8,
3283 => Opcode::VQRSHRNsv2i32,
3284 => Opcode::VQRSHRNsv4i16,
3285 => Opcode::VQRSHRNsv8i8,
3286 => Opcode::VQRSHRNuv2i32,
3287 => Opcode::VQRSHRNuv4i16,
3288 => Opcode::VQRSHRNuv8i8,
3289 => Opcode::VQRSHRUNv2i32,
3290 => Opcode::VQRSHRUNv4i16,
3291 => Opcode::VQRSHRUNv8i8,
3292 => Opcode::VQSHLsiv16i8,
3293 => Opcode::VQSHLsiv1i64,
3294 => Opcode::VQSHLsiv2i32,
3295 => Opcode::VQSHLsiv2i64,
3296 => Opcode::VQSHLsiv4i16,
3297 => Opcode::VQSHLsiv4i32,
3298 => Opcode::VQSHLsiv8i16,
3299 => Opcode::VQSHLsiv8i8,
3300 => Opcode::VQSHLsuv16i8,
3301 => Opcode::VQSHLsuv1i64,
3302 => Opcode::VQSHLsuv2i32,
3303 => Opcode::VQSHLsuv2i64,
3304 => Opcode::VQSHLsuv4i16,
3305 => Opcode::VQSHLsuv4i32,
3306 => Opcode::VQSHLsuv8i16,
3307 => Opcode::VQSHLsuv8i8,
3308 => Opcode::VQSHLsv16i8,
3309 => Opcode::VQSHLsv1i64,
3310 => Opcode::VQSHLsv2i32,
3311 => Opcode::VQSHLsv2i64,
3312 => Opcode::VQSHLsv4i16,
3313 => Opcode::VQSHLsv4i32,
3314 => Opcode::VQSHLsv8i16,
3315 => Opcode::VQSHLsv8i8,
3316 => Opcode::VQSHLuiv16i8,
3317 => Opcode::VQSHLuiv1i64,
3318 => Opcode::VQSHLuiv2i32,
3319 => Opcode::VQSHLuiv2i64,
3320 => Opcode::VQSHLuiv4i16,
3321 => Opcode::VQSHLuiv4i32,
3322 => Opcode::VQSHLuiv8i16,
3323 => Opcode::VQSHLuiv8i8,
3324 => Opcode::VQSHLuv16i8,
3325 => Opcode::VQSHLuv1i64,
3326 => Opcode::VQSHLuv2i32,
3327 => Opcode::VQSHLuv2i64,
3328 => Opcode::VQSHLuv4i16,
3329 => Opcode::VQSHLuv4i32,
3330 => Opcode::VQSHLuv8i16,
3331 => Opcode::VQSHLuv8i8,
3332 => Opcode::VQSHRNsv2i32,
3333 => Opcode::VQSHRNsv4i16,
3334 => Opcode::VQSHRNsv8i8,
3335 => Opcode::VQSHRNuv2i32,
3336 => Opcode::VQSHRNuv4i16,
3337 => Opcode::VQSHRNuv8i8,
3338 => Opcode::VQSHRUNv2i32,
3339 => Opcode::VQSHRUNv4i16,
3340 => Opcode::VQSHRUNv8i8,
3341 => Opcode::VQSUBsv16i8,
3342 => Opcode::VQSUBsv1i64,
3343 => Opcode::VQSUBsv2i32,
3344 => Opcode::VQSUBsv2i64,
3345 => Opcode::VQSUBsv4i16,
3346 => Opcode::VQSUBsv4i32,
3347 => Opcode::VQSUBsv8i16,
3348 => Opcode::VQSUBsv8i8,
3349 => Opcode::VQSUBuv16i8,
3350 => Opcode::VQSUBuv1i64,
3351 => Opcode::VQSUBuv2i32,
3352 => Opcode::VQSUBuv2i64,
3353 => Opcode::VQSUBuv4i16,
3354 => Opcode::VQSUBuv4i32,
3355 => Opcode::VQSUBuv8i16,
3356 => Opcode::VQSUBuv8i8,
3357 => Opcode::VRADDHNv2i32,
3358 => Opcode::VRADDHNv4i16,
3359 => Opcode::VRADDHNv8i8,
3360 => Opcode::VRECPEd,
3361 => Opcode::VRECPEfd,
3362 => Opcode::VRECPEfq,
3363 => Opcode::VRECPEhd,
3364 => Opcode::VRECPEhq,
3365 => Opcode::VRECPEq,
3366 => Opcode::VRECPSfd,
3367 => Opcode::VRECPSfq,
3368 => Opcode::VRECPShd,
3369 => Opcode::VRECPShq,
3370 => Opcode::VREV16d8,
3371 => Opcode::VREV16q8,
3372 => Opcode::VREV32d16,
3373 => Opcode::VREV32d8,
3374 => Opcode::VREV32q16,
3375 => Opcode::VREV32q8,
3376 => Opcode::VREV64d16,
3377 => Opcode::VREV64d32,
3378 => Opcode::VREV64d8,
3379 => Opcode::VREV64q16,
3380 => Opcode::VREV64q32,
3381 => Opcode::VREV64q8,
3382 => Opcode::VRHADDsv16i8,
3383 => Opcode::VRHADDsv2i32,
3384 => Opcode::VRHADDsv4i16,
3385 => Opcode::VRHADDsv4i32,
3386 => Opcode::VRHADDsv8i16,
3387 => Opcode::VRHADDsv8i8,
3388 => Opcode::VRHADDuv16i8,
3389 => Opcode::VRHADDuv2i32,
3390 => Opcode::VRHADDuv4i16,
3391 => Opcode::VRHADDuv4i32,
3392 => Opcode::VRHADDuv8i16,
3393 => Opcode::VRHADDuv8i8,
3394 => Opcode::VRINTAD,
3395 => Opcode::VRINTAH,
3396 => Opcode::VRINTANDf,
3397 => Opcode::VRINTANDh,
3398 => Opcode::VRINTANQf,
3399 => Opcode::VRINTANQh,
3400 => Opcode::VRINTAS,
3401 => Opcode::VRINTMD,
3402 => Opcode::VRINTMH,
3403 => Opcode::VRINTMNDf,
3404 => Opcode::VRINTMNDh,
3405 => Opcode::VRINTMNQf,
3406 => Opcode::VRINTMNQh,
3407 => Opcode::VRINTMS,
3408 => Opcode::VRINTND,
3409 => Opcode::VRINTNH,
3410 => Opcode::VRINTNNDf,
3411 => Opcode::VRINTNNDh,
3412 => Opcode::VRINTNNQf,
3413 => Opcode::VRINTNNQh,
3414 => Opcode::VRINTNS,
3415 => Opcode::VRINTPD,
3416 => Opcode::VRINTPH,
3417 => Opcode::VRINTPNDf,
3418 => Opcode::VRINTPNDh,
3419 => Opcode::VRINTPNQf,
3420 => Opcode::VRINTPNQh,
3421 => Opcode::VRINTPS,
3422 => Opcode::VRINTRD,
3423 => Opcode::VRINTRH,
3424 => Opcode::VRINTRS,
3425 => Opcode::VRINTXD,
3426 => Opcode::VRINTXH,
3427 => Opcode::VRINTXNDf,
3428 => Opcode::VRINTXNDh,
3429 => Opcode::VRINTXNQf,
3430 => Opcode::VRINTXNQh,
3431 => Opcode::VRINTXS,
3432 => Opcode::VRINTZD,
3433 => Opcode::VRINTZH,
3434 => Opcode::VRINTZNDf,
3435 => Opcode::VRINTZNDh,
3436 => Opcode::VRINTZNQf,
3437 => Opcode::VRINTZNQh,
3438 => Opcode::VRINTZS,
3439 => Opcode::VRSHLsv16i8,
3440 => Opcode::VRSHLsv1i64,
3441 => Opcode::VRSHLsv2i32,
3442 => Opcode::VRSHLsv2i64,
3443 => Opcode::VRSHLsv4i16,
3444 => Opcode::VRSHLsv4i32,
3445 => Opcode::VRSHLsv8i16,
3446 => Opcode::VRSHLsv8i8,
3447 => Opcode::VRSHLuv16i8,
3448 => Opcode::VRSHLuv1i64,
3449 => Opcode::VRSHLuv2i32,
3450 => Opcode::VRSHLuv2i64,
3451 => Opcode::VRSHLuv4i16,
3452 => Opcode::VRSHLuv4i32,
3453 => Opcode::VRSHLuv8i16,
3454 => Opcode::VRSHLuv8i8,
3455 => Opcode::VRSHRNv2i32,
3456 => Opcode::VRSHRNv4i16,
3457 => Opcode::VRSHRNv8i8,
3458 => Opcode::VRSHRsv16i8,
3459 => Opcode::VRSHRsv1i64,
3460 => Opcode::VRSHRsv2i32,
3461 => Opcode::VRSHRsv2i64,
3462 => Opcode::VRSHRsv4i16,
3463 => Opcode::VRSHRsv4i32,
3464 => Opcode::VRSHRsv8i16,
3465 => Opcode::VRSHRsv8i8,
3466 => Opcode::VRSHRuv16i8,
3467 => Opcode::VRSHRuv1i64,
3468 => Opcode::VRSHRuv2i32,
3469 => Opcode::VRSHRuv2i64,
3470 => Opcode::VRSHRuv4i16,
3471 => Opcode::VRSHRuv4i32,
3472 => Opcode::VRSHRuv8i16,
3473 => Opcode::VRSHRuv8i8,
3474 => Opcode::VRSQRTEd,
3475 => Opcode::VRSQRTEfd,
3476 => Opcode::VRSQRTEfq,
3477 => Opcode::VRSQRTEhd,
3478 => Opcode::VRSQRTEhq,
3479 => Opcode::VRSQRTEq,
3480 => Opcode::VRSQRTSfd,
3481 => Opcode::VRSQRTSfq,
3482 => Opcode::VRSQRTShd,
3483 => Opcode::VRSQRTShq,
3484 => Opcode::VRSRAsv16i8,
3485 => Opcode::VRSRAsv1i64,
3486 => Opcode::VRSRAsv2i32,
3487 => Opcode::VRSRAsv2i64,
3488 => Opcode::VRSRAsv4i16,
3489 => Opcode::VRSRAsv4i32,
3490 => Opcode::VRSRAsv8i16,
3491 => Opcode::VRSRAsv8i8,
3492 => Opcode::VRSRAuv16i8,
3493 => Opcode::VRSRAuv1i64,
3494 => Opcode::VRSRAuv2i32,
3495 => Opcode::VRSRAuv2i64,
3496 => Opcode::VRSRAuv4i16,
3497 => Opcode::VRSRAuv4i32,
3498 => Opcode::VRSRAuv8i16,
3499 => Opcode::VRSRAuv8i8,
3500 => Opcode::VRSUBHNv2i32,
3501 => Opcode::VRSUBHNv4i16,
3502 => Opcode::VRSUBHNv8i8,
3503 => Opcode::VSCCLRMD,
3504 => Opcode::VSCCLRMS,
3505 => Opcode::VSDOTD,
3506 => Opcode::VSDOTDI,
3507 => Opcode::VSDOTQ,
3508 => Opcode::VSDOTQI,
3509 => Opcode::VSELEQD,
3510 => Opcode::VSELEQH,
3511 => Opcode::VSELEQS,
3512 => Opcode::VSELGED,
3513 => Opcode::VSELGEH,
3514 => Opcode::VSELGES,
3515 => Opcode::VSELGTD,
3516 => Opcode::VSELGTH,
3517 => Opcode::VSELGTS,
3518 => Opcode::VSELVSD,
3519 => Opcode::VSELVSH,
3520 => Opcode::VSELVSS,
3521 => Opcode::VSETLNi16,
3522 => Opcode::VSETLNi32,
3523 => Opcode::VSETLNi8,
3524 => Opcode::VSHLLi16,
3525 => Opcode::VSHLLi32,
3526 => Opcode::VSHLLi8,
3527 => Opcode::VSHLLsv2i64,
3528 => Opcode::VSHLLsv4i32,
3529 => Opcode::VSHLLsv8i16,
3530 => Opcode::VSHLLuv2i64,
3531 => Opcode::VSHLLuv4i32,
3532 => Opcode::VSHLLuv8i16,
3533 => Opcode::VSHLiv16i8,
3534 => Opcode::VSHLiv1i64,
3535 => Opcode::VSHLiv2i32,
3536 => Opcode::VSHLiv2i64,
3537 => Opcode::VSHLiv4i16,
3538 => Opcode::VSHLiv4i32,
3539 => Opcode::VSHLiv8i16,
3540 => Opcode::VSHLiv8i8,
3541 => Opcode::VSHLsv16i8,
3542 => Opcode::VSHLsv1i64,
3543 => Opcode::VSHLsv2i32,
3544 => Opcode::VSHLsv2i64,
3545 => Opcode::VSHLsv4i16,
3546 => Opcode::VSHLsv4i32,
3547 => Opcode::VSHLsv8i16,
3548 => Opcode::VSHLsv8i8,
3549 => Opcode::VSHLuv16i8,
3550 => Opcode::VSHLuv1i64,
3551 => Opcode::VSHLuv2i32,
3552 => Opcode::VSHLuv2i64,
3553 => Opcode::VSHLuv4i16,
3554 => Opcode::VSHLuv4i32,
3555 => Opcode::VSHLuv8i16,
3556 => Opcode::VSHLuv8i8,
3557 => Opcode::VSHRNv2i32,
3558 => Opcode::VSHRNv4i16,
3559 => Opcode::VSHRNv8i8,
3560 => Opcode::VSHRsv16i8,
3561 => Opcode::VSHRsv1i64,
3562 => Opcode::VSHRsv2i32,
3563 => Opcode::VSHRsv2i64,
3564 => Opcode::VSHRsv4i16,
3565 => Opcode::VSHRsv4i32,
3566 => Opcode::VSHRsv8i16,
3567 => Opcode::VSHRsv8i8,
3568 => Opcode::VSHRuv16i8,
3569 => Opcode::VSHRuv1i64,
3570 => Opcode::VSHRuv2i32,
3571 => Opcode::VSHRuv2i64,
3572 => Opcode::VSHRuv4i16,
3573 => Opcode::VSHRuv4i32,
3574 => Opcode::VSHRuv8i16,
3575 => Opcode::VSHRuv8i8,
3576 => Opcode::VSHTOD,
3577 => Opcode::VSHTOH,
3578 => Opcode::VSHTOS,
3579 => Opcode::VSITOD,
3580 => Opcode::VSITOH,
3581 => Opcode::VSITOS,
3582 => Opcode::VSLIv16i8,
3583 => Opcode::VSLIv1i64,
3584 => Opcode::VSLIv2i32,
3585 => Opcode::VSLIv2i64,
3586 => Opcode::VSLIv4i16,
3587 => Opcode::VSLIv4i32,
3588 => Opcode::VSLIv8i16,
3589 => Opcode::VSLIv8i8,
3590 => Opcode::VSLTOD,
3591 => Opcode::VSLTOH,
3592 => Opcode::VSLTOS,
3593 => Opcode::VSMMLA,
3594 => Opcode::VSQRTD,
3595 => Opcode::VSQRTH,
3596 => Opcode::VSQRTS,
3597 => Opcode::VSRAsv16i8,
3598 => Opcode::VSRAsv1i64,
3599 => Opcode::VSRAsv2i32,
3600 => Opcode::VSRAsv2i64,
3601 => Opcode::VSRAsv4i16,
3602 => Opcode::VSRAsv4i32,
3603 => Opcode::VSRAsv8i16,
3604 => Opcode::VSRAsv8i8,
3605 => Opcode::VSRAuv16i8,
3606 => Opcode::VSRAuv1i64,
3607 => Opcode::VSRAuv2i32,
3608 => Opcode::VSRAuv2i64,
3609 => Opcode::VSRAuv4i16,
3610 => Opcode::VSRAuv4i32,
3611 => Opcode::VSRAuv8i16,
3612 => Opcode::VSRAuv8i8,
3613 => Opcode::VSRIv16i8,
3614 => Opcode::VSRIv1i64,
3615 => Opcode::VSRIv2i32,
3616 => Opcode::VSRIv2i64,
3617 => Opcode::VSRIv4i16,
3618 => Opcode::VSRIv4i32,
3619 => Opcode::VSRIv8i16,
3620 => Opcode::VSRIv8i8,
3621 => Opcode::VST1LNd16,
3622 => Opcode::VST1LNd16_UPD,
3623 => Opcode::VST1LNd32,
3624 => Opcode::VST1LNd32_UPD,
3625 => Opcode::VST1LNd8,
3626 => Opcode::VST1LNd8_UPD,
3627 => Opcode::VST1LNq16Pseudo,
3628 => Opcode::VST1LNq16Pseudo_UPD,
3629 => Opcode::VST1LNq32Pseudo,
3630 => Opcode::VST1LNq32Pseudo_UPD,
3631 => Opcode::VST1LNq8Pseudo,
3632 => Opcode::VST1LNq8Pseudo_UPD,
3633 => Opcode::VST1d16,
3634 => Opcode::VST1d16Q,
3635 => Opcode::VST1d16QPseudo,
3636 => Opcode::VST1d16QPseudoWB_fixed,
3637 => Opcode::VST1d16QPseudoWB_register,
3638 => Opcode::VST1d16Qwb_fixed,
3639 => Opcode::VST1d16Qwb_register,
3640 => Opcode::VST1d16T,
3641 => Opcode::VST1d16TPseudo,
3642 => Opcode::VST1d16TPseudoWB_fixed,
3643 => Opcode::VST1d16TPseudoWB_register,
3644 => Opcode::VST1d16Twb_fixed,
3645 => Opcode::VST1d16Twb_register,
3646 => Opcode::VST1d16wb_fixed,
3647 => Opcode::VST1d16wb_register,
3648 => Opcode::VST1d32,
3649 => Opcode::VST1d32Q,
3650 => Opcode::VST1d32QPseudo,
3651 => Opcode::VST1d32QPseudoWB_fixed,
3652 => Opcode::VST1d32QPseudoWB_register,
3653 => Opcode::VST1d32Qwb_fixed,
3654 => Opcode::VST1d32Qwb_register,
3655 => Opcode::VST1d32T,
3656 => Opcode::VST1d32TPseudo,
3657 => Opcode::VST1d32TPseudoWB_fixed,
3658 => Opcode::VST1d32TPseudoWB_register,
3659 => Opcode::VST1d32Twb_fixed,
3660 => Opcode::VST1d32Twb_register,
3661 => Opcode::VST1d32wb_fixed,
3662 => Opcode::VST1d32wb_register,
3663 => Opcode::VST1d64,
3664 => Opcode::VST1d64Q,
3665 => Opcode::VST1d64QPseudo,
3666 => Opcode::VST1d64QPseudoWB_fixed,
3667 => Opcode::VST1d64QPseudoWB_register,
3668 => Opcode::VST1d64Qwb_fixed,
3669 => Opcode::VST1d64Qwb_register,
3670 => Opcode::VST1d64T,
3671 => Opcode::VST1d64TPseudo,
3672 => Opcode::VST1d64TPseudoWB_fixed,
3673 => Opcode::VST1d64TPseudoWB_register,
3674 => Opcode::VST1d64Twb_fixed,
3675 => Opcode::VST1d64Twb_register,
3676 => Opcode::VST1d64wb_fixed,
3677 => Opcode::VST1d64wb_register,
3678 => Opcode::VST1d8,
3679 => Opcode::VST1d8Q,
3680 => Opcode::VST1d8QPseudo,
3681 => Opcode::VST1d8QPseudoWB_fixed,
3682 => Opcode::VST1d8QPseudoWB_register,
3683 => Opcode::VST1d8Qwb_fixed,
3684 => Opcode::VST1d8Qwb_register,
3685 => Opcode::VST1d8T,
3686 => Opcode::VST1d8TPseudo,
3687 => Opcode::VST1d8TPseudoWB_fixed,
3688 => Opcode::VST1d8TPseudoWB_register,
3689 => Opcode::VST1d8Twb_fixed,
3690 => Opcode::VST1d8Twb_register,
3691 => Opcode::VST1d8wb_fixed,
3692 => Opcode::VST1d8wb_register,
3693 => Opcode::VST1q16,
3694 => Opcode::VST1q16HighQPseudo,
3695 => Opcode::VST1q16HighQPseudo_UPD,
3696 => Opcode::VST1q16HighTPseudo,
3697 => Opcode::VST1q16HighTPseudo_UPD,
3698 => Opcode::VST1q16LowQPseudo_UPD,
3699 => Opcode::VST1q16LowTPseudo_UPD,
3700 => Opcode::VST1q16wb_fixed,
3701 => Opcode::VST1q16wb_register,
3702 => Opcode::VST1q32,
3703 => Opcode::VST1q32HighQPseudo,
3704 => Opcode::VST1q32HighQPseudo_UPD,
3705 => Opcode::VST1q32HighTPseudo,
3706 => Opcode::VST1q32HighTPseudo_UPD,
3707 => Opcode::VST1q32LowQPseudo_UPD,
3708 => Opcode::VST1q32LowTPseudo_UPD,
3709 => Opcode::VST1q32wb_fixed,
3710 => Opcode::VST1q32wb_register,
3711 => Opcode::VST1q64,
3712 => Opcode::VST1q64HighQPseudo,
3713 => Opcode::VST1q64HighQPseudo_UPD,
3714 => Opcode::VST1q64HighTPseudo,
3715 => Opcode::VST1q64HighTPseudo_UPD,
3716 => Opcode::VST1q64LowQPseudo_UPD,
3717 => Opcode::VST1q64LowTPseudo_UPD,
3718 => Opcode::VST1q64wb_fixed,
3719 => Opcode::VST1q64wb_register,
3720 => Opcode::VST1q8,
3721 => Opcode::VST1q8HighQPseudo,
3722 => Opcode::VST1q8HighQPseudo_UPD,
3723 => Opcode::VST1q8HighTPseudo,
3724 => Opcode::VST1q8HighTPseudo_UPD,
3725 => Opcode::VST1q8LowQPseudo_UPD,
3726 => Opcode::VST1q8LowTPseudo_UPD,
3727 => Opcode::VST1q8wb_fixed,
3728 => Opcode::VST1q8wb_register,
3729 => Opcode::VST2LNd16,
3730 => Opcode::VST2LNd16Pseudo,
3731 => Opcode::VST2LNd16Pseudo_UPD,
3732 => Opcode::VST2LNd16_UPD,
3733 => Opcode::VST2LNd32,
3734 => Opcode::VST2LNd32Pseudo,
3735 => Opcode::VST2LNd32Pseudo_UPD,
3736 => Opcode::VST2LNd32_UPD,
3737 => Opcode::VST2LNd8,
3738 => Opcode::VST2LNd8Pseudo,
3739 => Opcode::VST2LNd8Pseudo_UPD,
3740 => Opcode::VST2LNd8_UPD,
3741 => Opcode::VST2LNq16,
3742 => Opcode::VST2LNq16Pseudo,
3743 => Opcode::VST2LNq16Pseudo_UPD,
3744 => Opcode::VST2LNq16_UPD,
3745 => Opcode::VST2LNq32,
3746 => Opcode::VST2LNq32Pseudo,
3747 => Opcode::VST2LNq32Pseudo_UPD,
3748 => Opcode::VST2LNq32_UPD,
3749 => Opcode::VST2b16,
3750 => Opcode::VST2b16wb_fixed,
3751 => Opcode::VST2b16wb_register,
3752 => Opcode::VST2b32,
3753 => Opcode::VST2b32wb_fixed,
3754 => Opcode::VST2b32wb_register,
3755 => Opcode::VST2b8,
3756 => Opcode::VST2b8wb_fixed,
3757 => Opcode::VST2b8wb_register,
3758 => Opcode::VST2d16,
3759 => Opcode::VST2d16wb_fixed,
3760 => Opcode::VST2d16wb_register,
3761 => Opcode::VST2d32,
3762 => Opcode::VST2d32wb_fixed,
3763 => Opcode::VST2d32wb_register,
3764 => Opcode::VST2d8,
3765 => Opcode::VST2d8wb_fixed,
3766 => Opcode::VST2d8wb_register,
3767 => Opcode::VST2q16,
3768 => Opcode::VST2q16Pseudo,
3769 => Opcode::VST2q16PseudoWB_fixed,
3770 => Opcode::VST2q16PseudoWB_register,
3771 => Opcode::VST2q16wb_fixed,
3772 => Opcode::VST2q16wb_register,
3773 => Opcode::VST2q32,
3774 => Opcode::VST2q32Pseudo,
3775 => Opcode::VST2q32PseudoWB_fixed,
3776 => Opcode::VST2q32PseudoWB_register,
3777 => Opcode::VST2q32wb_fixed,
3778 => Opcode::VST2q32wb_register,
3779 => Opcode::VST2q8,
3780 => Opcode::VST2q8Pseudo,
3781 => Opcode::VST2q8PseudoWB_fixed,
3782 => Opcode::VST2q8PseudoWB_register,
3783 => Opcode::VST2q8wb_fixed,
3784 => Opcode::VST2q8wb_register,
3785 => Opcode::VST3LNd16,
3786 => Opcode::VST3LNd16Pseudo,
3787 => Opcode::VST3LNd16Pseudo_UPD,
3788 => Opcode::VST3LNd16_UPD,
3789 => Opcode::VST3LNd32,
3790 => Opcode::VST3LNd32Pseudo,
3791 => Opcode::VST3LNd32Pseudo_UPD,
3792 => Opcode::VST3LNd32_UPD,
3793 => Opcode::VST3LNd8,
3794 => Opcode::VST3LNd8Pseudo,
3795 => Opcode::VST3LNd8Pseudo_UPD,
3796 => Opcode::VST3LNd8_UPD,
3797 => Opcode::VST3LNq16,
3798 => Opcode::VST3LNq16Pseudo,
3799 => Opcode::VST3LNq16Pseudo_UPD,
3800 => Opcode::VST3LNq16_UPD,
3801 => Opcode::VST3LNq32,
3802 => Opcode::VST3LNq32Pseudo,
3803 => Opcode::VST3LNq32Pseudo_UPD,
3804 => Opcode::VST3LNq32_UPD,
3805 => Opcode::VST3d16,
3806 => Opcode::VST3d16Pseudo,
3807 => Opcode::VST3d16Pseudo_UPD,
3808 => Opcode::VST3d16_UPD,
3809 => Opcode::VST3d32,
3810 => Opcode::VST3d32Pseudo,
3811 => Opcode::VST3d32Pseudo_UPD,
3812 => Opcode::VST3d32_UPD,
3813 => Opcode::VST3d8,
3814 => Opcode::VST3d8Pseudo,
3815 => Opcode::VST3d8Pseudo_UPD,
3816 => Opcode::VST3d8_UPD,
3817 => Opcode::VST3q16,
3818 => Opcode::VST3q16Pseudo_UPD,
3819 => Opcode::VST3q16_UPD,
3820 => Opcode::VST3q16oddPseudo,
3821 => Opcode::VST3q16oddPseudo_UPD,
3822 => Opcode::VST3q32,
3823 => Opcode::VST3q32Pseudo_UPD,
3824 => Opcode::VST3q32_UPD,
3825 => Opcode::VST3q32oddPseudo,
3826 => Opcode::VST3q32oddPseudo_UPD,
3827 => Opcode::VST3q8,
3828 => Opcode::VST3q8Pseudo_UPD,
3829 => Opcode::VST3q8_UPD,
3830 => Opcode::VST3q8oddPseudo,
3831 => Opcode::VST3q8oddPseudo_UPD,
3832 => Opcode::VST4LNd16,
3833 => Opcode::VST4LNd16Pseudo,
3834 => Opcode::VST4LNd16Pseudo_UPD,
3835 => Opcode::VST4LNd16_UPD,
3836 => Opcode::VST4LNd32,
3837 => Opcode::VST4LNd32Pseudo,
3838 => Opcode::VST4LNd32Pseudo_UPD,
3839 => Opcode::VST4LNd32_UPD,
3840 => Opcode::VST4LNd8,
3841 => Opcode::VST4LNd8Pseudo,
3842 => Opcode::VST4LNd8Pseudo_UPD,
3843 => Opcode::VST4LNd8_UPD,
3844 => Opcode::VST4LNq16,
3845 => Opcode::VST4LNq16Pseudo,
3846 => Opcode::VST4LNq16Pseudo_UPD,
3847 => Opcode::VST4LNq16_UPD,
3848 => Opcode::VST4LNq32,
3849 => Opcode::VST4LNq32Pseudo,
3850 => Opcode::VST4LNq32Pseudo_UPD,
3851 => Opcode::VST4LNq32_UPD,
3852 => Opcode::VST4d16,
3853 => Opcode::VST4d16Pseudo,
3854 => Opcode::VST4d16Pseudo_UPD,
3855 => Opcode::VST4d16_UPD,
3856 => Opcode::VST4d32,
3857 => Opcode::VST4d32Pseudo,
3858 => Opcode::VST4d32Pseudo_UPD,
3859 => Opcode::VST4d32_UPD,
3860 => Opcode::VST4d8,
3861 => Opcode::VST4d8Pseudo,
3862 => Opcode::VST4d8Pseudo_UPD,
3863 => Opcode::VST4d8_UPD,
3864 => Opcode::VST4q16,
3865 => Opcode::VST4q16Pseudo_UPD,
3866 => Opcode::VST4q16_UPD,
3867 => Opcode::VST4q16oddPseudo,
3868 => Opcode::VST4q16oddPseudo_UPD,
3869 => Opcode::VST4q32,
3870 => Opcode::VST4q32Pseudo_UPD,
3871 => Opcode::VST4q32_UPD,
3872 => Opcode::VST4q32oddPseudo,
3873 => Opcode::VST4q32oddPseudo_UPD,
3874 => Opcode::VST4q8,
3875 => Opcode::VST4q8Pseudo_UPD,
3876 => Opcode::VST4q8_UPD,
3877 => Opcode::VST4q8oddPseudo,
3878 => Opcode::VST4q8oddPseudo_UPD,
3879 => Opcode::VSTMDDB_UPD,
3880 => Opcode::VSTMDIA,
3881 => Opcode::VSTMDIA_UPD,
3882 => Opcode::VSTMQIA,
3883 => Opcode::VSTMSDB_UPD,
3884 => Opcode::VSTMSIA,
3885 => Opcode::VSTMSIA_UPD,
3886 => Opcode::VSTRD,
3887 => Opcode::VSTRH,
3888 => Opcode::VSTRS,
3889 => Opcode::VSTR_FPCXTNS_off,
3890 => Opcode::VSTR_FPCXTNS_post,
3891 => Opcode::VSTR_FPCXTNS_pre,
3892 => Opcode::VSTR_FPCXTS_off,
3893 => Opcode::VSTR_FPCXTS_post,
3894 => Opcode::VSTR_FPCXTS_pre,
3895 => Opcode::VSTR_FPSCR_NZCVQC_off,
3896 => Opcode::VSTR_FPSCR_NZCVQC_post,
3897 => Opcode::VSTR_FPSCR_NZCVQC_pre,
3898 => Opcode::VSTR_FPSCR_off,
3899 => Opcode::VSTR_FPSCR_post,
3900 => Opcode::VSTR_FPSCR_pre,
3901 => Opcode::VSTR_P0_off,
3902 => Opcode::VSTR_P0_post,
3903 => Opcode::VSTR_P0_pre,
3904 => Opcode::VSTR_VPR_off,
3905 => Opcode::VSTR_VPR_post,
3906 => Opcode::VSTR_VPR_pre,
3907 => Opcode::VSUBD,
3908 => Opcode::VSUBH,
3909 => Opcode::VSUBHNv2i32,
3910 => Opcode::VSUBHNv4i16,
3911 => Opcode::VSUBHNv8i8,
3912 => Opcode::VSUBLsv2i64,
3913 => Opcode::VSUBLsv4i32,
3914 => Opcode::VSUBLsv8i16,
3915 => Opcode::VSUBLuv2i64,
3916 => Opcode::VSUBLuv4i32,
3917 => Opcode::VSUBLuv8i16,
3918 => Opcode::VSUBS,
3919 => Opcode::VSUBWsv2i64,
3920 => Opcode::VSUBWsv4i32,
3921 => Opcode::VSUBWsv8i16,
3922 => Opcode::VSUBWuv2i64,
3923 => Opcode::VSUBWuv4i32,
3924 => Opcode::VSUBWuv8i16,
3925 => Opcode::VSUBfd,
3926 => Opcode::VSUBfq,
3927 => Opcode::VSUBhd,
3928 => Opcode::VSUBhq,
3929 => Opcode::VSUBv16i8,
3930 => Opcode::VSUBv1i64,
3931 => Opcode::VSUBv2i32,
3932 => Opcode::VSUBv2i64,
3933 => Opcode::VSUBv4i16,
3934 => Opcode::VSUBv4i32,
3935 => Opcode::VSUBv8i16,
3936 => Opcode::VSUBv8i8,
3937 => Opcode::VSUDOTDI,
3938 => Opcode::VSUDOTQI,
3939 => Opcode::VSWPd,
3940 => Opcode::VSWPq,
3941 => Opcode::VTBL1,
3942 => Opcode::VTBL2,
3943 => Opcode::VTBL3,
3944 => Opcode::VTBL3Pseudo,
3945 => Opcode::VTBL4,
3946 => Opcode::VTBL4Pseudo,
3947 => Opcode::VTBX1,
3948 => Opcode::VTBX2,
3949 => Opcode::VTBX3,
3950 => Opcode::VTBX3Pseudo,
3951 => Opcode::VTBX4,
3952 => Opcode::VTBX4Pseudo,
3953 => Opcode::VTOSHD,
3954 => Opcode::VTOSHH,
3955 => Opcode::VTOSHS,
3956 => Opcode::VTOSIRD,
3957 => Opcode::VTOSIRH,
3958 => Opcode::VTOSIRS,
3959 => Opcode::VTOSIZD,
3960 => Opcode::VTOSIZH,
3961 => Opcode::VTOSIZS,
3962 => Opcode::VTOSLD,
3963 => Opcode::VTOSLH,
3964 => Opcode::VTOSLS,
3965 => Opcode::VTOUHD,
3966 => Opcode::VTOUHH,
3967 => Opcode::VTOUHS,
3968 => Opcode::VTOUIRD,
3969 => Opcode::VTOUIRH,
3970 => Opcode::VTOUIRS,
3971 => Opcode::VTOUIZD,
3972 => Opcode::VTOUIZH,
3973 => Opcode::VTOUIZS,
3974 => Opcode::VTOULD,
3975 => Opcode::VTOULH,
3976 => Opcode::VTOULS,
3977 => Opcode::VTRNd16,
3978 => Opcode::VTRNd32,
3979 => Opcode::VTRNd8,
3980 => Opcode::VTRNq16,
3981 => Opcode::VTRNq32,
3982 => Opcode::VTRNq8,
3983 => Opcode::VTSTv16i8,
3984 => Opcode::VTSTv2i32,
3985 => Opcode::VTSTv4i16,
3986 => Opcode::VTSTv4i32,
3987 => Opcode::VTSTv8i16,
3988 => Opcode::VTSTv8i8,
3989 => Opcode::VUDOTD,
3990 => Opcode::VUDOTDI,
3991 => Opcode::VUDOTQ,
3992 => Opcode::VUDOTQI,
3993 => Opcode::VUHTOD,
3994 => Opcode::VUHTOH,
3995 => Opcode::VUHTOS,
3996 => Opcode::VUITOD,
3997 => Opcode::VUITOH,
3998 => Opcode::VUITOS,
3999 => Opcode::VULTOD,
4000 => Opcode::VULTOH,
4001 => Opcode::VULTOS,
4002 => Opcode::VUMMLA,
4003 => Opcode::VUSDOTD,
4004 => Opcode::VUSDOTDI,
4005 => Opcode::VUSDOTQ,
4006 => Opcode::VUSDOTQI,
4007 => Opcode::VUSMMLA,
4008 => Opcode::VUZPd16,
4009 => Opcode::VUZPd8,
4010 => Opcode::VUZPq16,
4011 => Opcode::VUZPq32,
4012 => Opcode::VUZPq8,
4013 => Opcode::VZIPd16,
4014 => Opcode::VZIPd8,
4015 => Opcode::VZIPq16,
4016 => Opcode::VZIPq32,
4017 => Opcode::VZIPq8,
4018 => Opcode::sysLDMDA,
4019 => Opcode::sysLDMDA_UPD,
4020 => Opcode::sysLDMDB,
4021 => Opcode::sysLDMDB_UPD,
4022 => Opcode::sysLDMIA,
4023 => Opcode::sysLDMIA_UPD,
4024 => Opcode::sysLDMIB,
4025 => Opcode::sysLDMIB_UPD,
4026 => Opcode::sysSTMDA,
4027 => Opcode::sysSTMDA_UPD,
4028 => Opcode::sysSTMDB,
4029 => Opcode::sysSTMDB_UPD,
4030 => Opcode::sysSTMIA,
4031 => Opcode::sysSTMIA_UPD,
4032 => Opcode::sysSTMIB,
4033 => Opcode::sysSTMIB_UPD,
4034 => Opcode::t2ADCri,
4035 => Opcode::t2ADCrr,
4036 => Opcode::t2ADCrs,
4037 => Opcode::t2ADDri,
4038 => Opcode::t2ADDri12,
4039 => Opcode::t2ADDrr,
4040 => Opcode::t2ADDrs,
4041 => Opcode::t2ADDspImm,
4042 => Opcode::t2ADDspImm12,
4043 => Opcode::t2ADR,
4044 => Opcode::t2ANDri,
4045 => Opcode::t2ANDrr,
4046 => Opcode::t2ANDrs,
4047 => Opcode::t2ASRri,
4048 => Opcode::t2ASRrr,
4049 => Opcode::t2ASRs1,
4050 => Opcode::t2AUT,
4051 => Opcode::t2AUTG,
4052 => Opcode::t2B,
4053 => Opcode::t2BFC,
4054 => Opcode::t2BFI,
4055 => Opcode::t2BFLi,
4056 => Opcode::t2BFLr,
4057 => Opcode::t2BFi,
4058 => Opcode::t2BFic,
4059 => Opcode::t2BFr,
4060 => Opcode::t2BICri,
4061 => Opcode::t2BICrr,
4062 => Opcode::t2BICrs,
4063 => Opcode::t2BTI,
4064 => Opcode::t2BXAUT,
4065 => Opcode::t2BXJ,
4066 => Opcode::t2Bcc,
4067 => Opcode::t2CDP,
4068 => Opcode::t2CDP2,
4069 => Opcode::t2CLREX,
4070 => Opcode::t2CLRM,
4071 => Opcode::t2CLZ,
4072 => Opcode::t2CMNri,
4073 => Opcode::t2CMNzrr,
4074 => Opcode::t2CMNzrs,
4075 => Opcode::t2CMPri,
4076 => Opcode::t2CMPrr,
4077 => Opcode::t2CMPrs,
4078 => Opcode::t2CPS1p,
4079 => Opcode::t2CPS2p,
4080 => Opcode::t2CPS3p,
4081 => Opcode::t2CRC32B,
4082 => Opcode::t2CRC32CB,
4083 => Opcode::t2CRC32CH,
4084 => Opcode::t2CRC32CW,
4085 => Opcode::t2CRC32H,
4086 => Opcode::t2CRC32W,
4087 => Opcode::t2CSEL,
4088 => Opcode::t2CSINC,
4089 => Opcode::t2CSINV,
4090 => Opcode::t2CSNEG,
4091 => Opcode::t2DBG,
4092 => Opcode::t2DCPS1,
4093 => Opcode::t2DCPS2,
4094 => Opcode::t2DCPS3,
4095 => Opcode::t2DLS,
4096 => Opcode::t2DMB,
4097 => Opcode::t2DSB,
4098 => Opcode::t2EORri,
4099 => Opcode::t2EORrr,
4100 => Opcode::t2EORrs,
4101 => Opcode::t2HINT,
4102 => Opcode::t2HVC,
4103 => Opcode::t2ISB,
4104 => Opcode::t2IT,
4105 => Opcode::t2Int_eh_sjlj_setjmp,
4106 => Opcode::t2Int_eh_sjlj_setjmp_nofp,
4107 => Opcode::t2LDA,
4108 => Opcode::t2LDAB,
4109 => Opcode::t2LDAEX,
4110 => Opcode::t2LDAEXB,
4111 => Opcode::t2LDAEXD,
4112 => Opcode::t2LDAEXH,
4113 => Opcode::t2LDAH,
4114 => Opcode::t2LDC2L_OFFSET,
4115 => Opcode::t2LDC2L_OPTION,
4116 => Opcode::t2LDC2L_POST,
4117 => Opcode::t2LDC2L_PRE,
4118 => Opcode::t2LDC2_OFFSET,
4119 => Opcode::t2LDC2_OPTION,
4120 => Opcode::t2LDC2_POST,
4121 => Opcode::t2LDC2_PRE,
4122 => Opcode::t2LDCL_OFFSET,
4123 => Opcode::t2LDCL_OPTION,
4124 => Opcode::t2LDCL_POST,
4125 => Opcode::t2LDCL_PRE,
4126 => Opcode::t2LDC_OFFSET,
4127 => Opcode::t2LDC_OPTION,
4128 => Opcode::t2LDC_POST,
4129 => Opcode::t2LDC_PRE,
4130 => Opcode::t2LDMDB,
4131 => Opcode::t2LDMDB_UPD,
4132 => Opcode::t2LDMIA,
4133 => Opcode::t2LDMIA_UPD,
4134 => Opcode::t2LDRBT,
4135 => Opcode::t2LDRB_POST,
4136 => Opcode::t2LDRB_PRE,
4137 => Opcode::t2LDRBi12,
4138 => Opcode::t2LDRBi8,
4139 => Opcode::t2LDRBpci,
4140 => Opcode::t2LDRBs,
4141 => Opcode::t2LDRD_POST,
4142 => Opcode::t2LDRD_PRE,
4143 => Opcode::t2LDRDi8,
4144 => Opcode::t2LDREX,
4145 => Opcode::t2LDREXB,
4146 => Opcode::t2LDREXD,
4147 => Opcode::t2LDREXH,
4148 => Opcode::t2LDRHT,
4149 => Opcode::t2LDRH_POST,
4150 => Opcode::t2LDRH_PRE,
4151 => Opcode::t2LDRHi12,
4152 => Opcode::t2LDRHi8,
4153 => Opcode::t2LDRHpci,
4154 => Opcode::t2LDRHs,
4155 => Opcode::t2LDRSBT,
4156 => Opcode::t2LDRSB_POST,
4157 => Opcode::t2LDRSB_PRE,
4158 => Opcode::t2LDRSBi12,
4159 => Opcode::t2LDRSBi8,
4160 => Opcode::t2LDRSBpci,
4161 => Opcode::t2LDRSBs,
4162 => Opcode::t2LDRSHT,
4163 => Opcode::t2LDRSH_POST,
4164 => Opcode::t2LDRSH_PRE,
4165 => Opcode::t2LDRSHi12,
4166 => Opcode::t2LDRSHi8,
4167 => Opcode::t2LDRSHpci,
4168 => Opcode::t2LDRSHs,
4169 => Opcode::t2LDRT,
4170 => Opcode::t2LDR_POST,
4171 => Opcode::t2LDR_PRE,
4172 => Opcode::t2LDRi12,
4173 => Opcode::t2LDRi8,
4174 => Opcode::t2LDRpci,
4175 => Opcode::t2LDRs,
4176 => Opcode::t2LE,
4177 => Opcode::t2LEUpdate,
4178 => Opcode::t2LSLri,
4179 => Opcode::t2LSLrr,
4180 => Opcode::t2LSRri,
4181 => Opcode::t2LSRrr,
4182 => Opcode::t2LSRs1,
4183 => Opcode::t2MCR,
4184 => Opcode::t2MCR2,
4185 => Opcode::t2MCRR,
4186 => Opcode::t2MCRR2,
4187 => Opcode::t2MLA,
4188 => Opcode::t2MLS,
4189 => Opcode::t2MOVTi16,
4190 => Opcode::t2MOVi,
4191 => Opcode::t2MOVi16,
4192 => Opcode::t2MOVr,
4193 => Opcode::t2MRC,
4194 => Opcode::t2MRC2,
4195 => Opcode::t2MRRC,
4196 => Opcode::t2MRRC2,
4197 => Opcode::t2MRS_AR,
4198 => Opcode::t2MRS_M,
4199 => Opcode::t2MRSbanked,
4200 => Opcode::t2MRSsys_AR,
4201 => Opcode::t2MSR_AR,
4202 => Opcode::t2MSR_M,
4203 => Opcode::t2MSRbanked,
4204 => Opcode::t2MUL,
4205 => Opcode::t2MVNi,
4206 => Opcode::t2MVNr,
4207 => Opcode::t2MVNs,
4208 => Opcode::t2ORNri,
4209 => Opcode::t2ORNrr,
4210 => Opcode::t2ORNrs,
4211 => Opcode::t2ORRri,
4212 => Opcode::t2ORRrr,
4213 => Opcode::t2ORRrs,
4214 => Opcode::t2PAC,
4215 => Opcode::t2PACBTI,
4216 => Opcode::t2PACG,
4217 => Opcode::t2PKHBT,
4218 => Opcode::t2PKHTB,
4219 => Opcode::t2PLDWi12,
4220 => Opcode::t2PLDWi8,
4221 => Opcode::t2PLDWs,
4222 => Opcode::t2PLDi12,
4223 => Opcode::t2PLDi8,
4224 => Opcode::t2PLDpci,
4225 => Opcode::t2PLDs,
4226 => Opcode::t2PLIi12,
4227 => Opcode::t2PLIi8,
4228 => Opcode::t2PLIpci,
4229 => Opcode::t2PLIs,
4230 => Opcode::t2QADD,
4231 => Opcode::t2QADD16,
4232 => Opcode::t2QADD8,
4233 => Opcode::t2QASX,
4234 => Opcode::t2QDADD,
4235 => Opcode::t2QDSUB,
4236 => Opcode::t2QSAX,
4237 => Opcode::t2QSUB,
4238 => Opcode::t2QSUB16,
4239 => Opcode::t2QSUB8,
4240 => Opcode::t2RBIT,
4241 => Opcode::t2REV,
4242 => Opcode::t2REV16,
4243 => Opcode::t2REVSH,
4244 => Opcode::t2RFEDB,
4245 => Opcode::t2RFEDBW,
4246 => Opcode::t2RFEIA,
4247 => Opcode::t2RFEIAW,
4248 => Opcode::t2RORri,
4249 => Opcode::t2RORrr,
4250 => Opcode::t2RRX,
4251 => Opcode::t2RSBri,
4252 => Opcode::t2RSBrr,
4253 => Opcode::t2RSBrs,
4254 => Opcode::t2SADD16,
4255 => Opcode::t2SADD8,
4256 => Opcode::t2SASX,
4257 => Opcode::t2SB,
4258 => Opcode::t2SBCri,
4259 => Opcode::t2SBCrr,
4260 => Opcode::t2SBCrs,
4261 => Opcode::t2SBFX,
4262 => Opcode::t2SDIV,
4263 => Opcode::t2SEL,
4264 => Opcode::t2SETPAN,
4265 => Opcode::t2SG,
4266 => Opcode::t2SHADD16,
4267 => Opcode::t2SHADD8,
4268 => Opcode::t2SHASX,
4269 => Opcode::t2SHSAX,
4270 => Opcode::t2SHSUB16,
4271 => Opcode::t2SHSUB8,
4272 => Opcode::t2SMC,
4273 => Opcode::t2SMLABB,
4274 => Opcode::t2SMLABT,
4275 => Opcode::t2SMLAD,
4276 => Opcode::t2SMLADX,
4277 => Opcode::t2SMLAL,
4278 => Opcode::t2SMLALBB,
4279 => Opcode::t2SMLALBT,
4280 => Opcode::t2SMLALD,
4281 => Opcode::t2SMLALDX,
4282 => Opcode::t2SMLALTB,
4283 => Opcode::t2SMLALTT,
4284 => Opcode::t2SMLATB,
4285 => Opcode::t2SMLATT,
4286 => Opcode::t2SMLAWB,
4287 => Opcode::t2SMLAWT,
4288 => Opcode::t2SMLSD,
4289 => Opcode::t2SMLSDX,
4290 => Opcode::t2SMLSLD,
4291 => Opcode::t2SMLSLDX,
4292 => Opcode::t2SMMLA,
4293 => Opcode::t2SMMLAR,
4294 => Opcode::t2SMMLS,
4295 => Opcode::t2SMMLSR,
4296 => Opcode::t2SMMUL,
4297 => Opcode::t2SMMULR,
4298 => Opcode::t2SMUAD,
4299 => Opcode::t2SMUADX,
4300 => Opcode::t2SMULBB,
4301 => Opcode::t2SMULBT,
4302 => Opcode::t2SMULL,
4303 => Opcode::t2SMULTB,
4304 => Opcode::t2SMULTT,
4305 => Opcode::t2SMULWB,
4306 => Opcode::t2SMULWT,
4307 => Opcode::t2SMUSD,
4308 => Opcode::t2SMUSDX,
4309 => Opcode::t2SRSDB,
4310 => Opcode::t2SRSDB_UPD,
4311 => Opcode::t2SRSIA,
4312 => Opcode::t2SRSIA_UPD,
4313 => Opcode::t2SSAT,
4314 => Opcode::t2SSAT16,
4315 => Opcode::t2SSAX,
4316 => Opcode::t2SSUB16,
4317 => Opcode::t2SSUB8,
4318 => Opcode::t2STC2L_OFFSET,
4319 => Opcode::t2STC2L_OPTION,
4320 => Opcode::t2STC2L_POST,
4321 => Opcode::t2STC2L_PRE,
4322 => Opcode::t2STC2_OFFSET,
4323 => Opcode::t2STC2_OPTION,
4324 => Opcode::t2STC2_POST,
4325 => Opcode::t2STC2_PRE,
4326 => Opcode::t2STCL_OFFSET,
4327 => Opcode::t2STCL_OPTION,
4328 => Opcode::t2STCL_POST,
4329 => Opcode::t2STCL_PRE,
4330 => Opcode::t2STC_OFFSET,
4331 => Opcode::t2STC_OPTION,
4332 => Opcode::t2STC_POST,
4333 => Opcode::t2STC_PRE,
4334 => Opcode::t2STL,
4335 => Opcode::t2STLB,
4336 => Opcode::t2STLEX,
4337 => Opcode::t2STLEXB,
4338 => Opcode::t2STLEXD,
4339 => Opcode::t2STLEXH,
4340 => Opcode::t2STLH,
4341 => Opcode::t2STMDB,
4342 => Opcode::t2STMDB_UPD,
4343 => Opcode::t2STMIA,
4344 => Opcode::t2STMIA_UPD,
4345 => Opcode::t2STRBT,
4346 => Opcode::t2STRB_POST,
4347 => Opcode::t2STRB_PRE,
4348 => Opcode::t2STRBi12,
4349 => Opcode::t2STRBi8,
4350 => Opcode::t2STRBs,
4351 => Opcode::t2STRD_POST,
4352 => Opcode::t2STRD_PRE,
4353 => Opcode::t2STRDi8,
4354 => Opcode::t2STREX,
4355 => Opcode::t2STREXB,
4356 => Opcode::t2STREXD,
4357 => Opcode::t2STREXH,
4358 => Opcode::t2STRHT,
4359 => Opcode::t2STRH_POST,
4360 => Opcode::t2STRH_PRE,
4361 => Opcode::t2STRHi12,
4362 => Opcode::t2STRHi8,
4363 => Opcode::t2STRHs,
4364 => Opcode::t2STRT,
4365 => Opcode::t2STR_POST,
4366 => Opcode::t2STR_PRE,
4367 => Opcode::t2STRi12,
4368 => Opcode::t2STRi8,
4369 => Opcode::t2STRs,
4370 => Opcode::t2SUBS_PC_LR,
4371 => Opcode::t2SUBri,
4372 => Opcode::t2SUBri12,
4373 => Opcode::t2SUBrr,
4374 => Opcode::t2SUBrs,
4375 => Opcode::t2SUBspImm,
4376 => Opcode::t2SUBspImm12,
4377 => Opcode::t2SXTAB,
4378 => Opcode::t2SXTAB16,
4379 => Opcode::t2SXTAH,
4380 => Opcode::t2SXTB,
4381 => Opcode::t2SXTB16,
4382 => Opcode::t2SXTH,
4383 => Opcode::t2TBB,
4384 => Opcode::t2TBH,
4385 => Opcode::t2TEQri,
4386 => Opcode::t2TEQrr,
4387 => Opcode::t2TEQrs,
4388 => Opcode::t2TSB,
4389 => Opcode::t2TSTri,
4390 => Opcode::t2TSTrr,
4391 => Opcode::t2TSTrs,
4392 => Opcode::t2TT,
4393 => Opcode::t2TTA,
4394 => Opcode::t2TTAT,
4395 => Opcode::t2TTT,
4396 => Opcode::t2UADD16,
4397 => Opcode::t2UADD8,
4398 => Opcode::t2UASX,
4399 => Opcode::t2UBFX,
4400 => Opcode::t2UDF,
4401 => Opcode::t2UDIV,
4402 => Opcode::t2UHADD16,
4403 => Opcode::t2UHADD8,
4404 => Opcode::t2UHASX,
4405 => Opcode::t2UHSAX,
4406 => Opcode::t2UHSUB16,
4407 => Opcode::t2UHSUB8,
4408 => Opcode::t2UMAAL,
4409 => Opcode::t2UMLAL,
4410 => Opcode::t2UMULL,
4411 => Opcode::t2UQADD16,
4412 => Opcode::t2UQADD8,
4413 => Opcode::t2UQASX,
4414 => Opcode::t2UQSAX,
4415 => Opcode::t2UQSUB16,
4416 => Opcode::t2UQSUB8,
4417 => Opcode::t2USAD8,
4418 => Opcode::t2USADA8,
4419 => Opcode::t2USAT,
4420 => Opcode::t2USAT16,
4421 => Opcode::t2USAX,
4422 => Opcode::t2USUB16,
4423 => Opcode::t2USUB8,
4424 => Opcode::t2UXTAB,
4425 => Opcode::t2UXTAB16,
4426 => Opcode::t2UXTAH,
4427 => Opcode::t2UXTB,
4428 => Opcode::t2UXTB16,
4429 => Opcode::t2UXTH,
4430 => Opcode::t2WLS,
4431 => Opcode::tADC,
4432 => Opcode::tADDhirr,
4433 => Opcode::tADDi3,
4434 => Opcode::tADDi8,
4435 => Opcode::tADDrSP,
4436 => Opcode::tADDrSPi,
4437 => Opcode::tADDrr,
4438 => Opcode::tADDspi,
4439 => Opcode::tADDspr,
4440 => Opcode::tADR,
4441 => Opcode::tAND,
4442 => Opcode::tASRri,
4443 => Opcode::tASRrr,
4444 => Opcode::tB,
4445 => Opcode::tBIC,
4446 => Opcode::tBKPT,
4447 => Opcode::tBL,
4448 => Opcode::tBLXNSr,
4449 => Opcode::tBLXi,
4450 => Opcode::tBLXr,
4451 => Opcode::tBX,
4452 => Opcode::tBXNS,
4453 => Opcode::tBcc,
4454 => Opcode::tCBNZ,
4455 => Opcode::tCBZ,
4456 => Opcode::tCMNz,
4457 => Opcode::tCMPhir,
4458 => Opcode::tCMPi8,
4459 => Opcode::tCMPr,
4460 => Opcode::tCPS,
4461 => Opcode::tEOR,
4462 => Opcode::tHINT,
4463 => Opcode::tHLT,
4464 => Opcode::tInt_WIN_eh_sjlj_longjmp,
4465 => Opcode::tInt_eh_sjlj_longjmp,
4466 => Opcode::tInt_eh_sjlj_setjmp,
4467 => Opcode::tLDMIA,
4468 => Opcode::tLDRBi,
4469 => Opcode::tLDRBr,
4470 => Opcode::tLDRHi,
4471 => Opcode::tLDRHr,
4472 => Opcode::tLDRSB,
4473 => Opcode::tLDRSH,
4474 => Opcode::tLDRi,
4475 => Opcode::tLDRpci,
4476 => Opcode::tLDRr,
4477 => Opcode::tLDRspi,
4478 => Opcode::tLSLri,
4479 => Opcode::tLSLrr,
4480 => Opcode::tLSRri,
4481 => Opcode::tLSRrr,
4482 => Opcode::tMOVSr,
4483 => Opcode::tMOVi8,
4484 => Opcode::tMOVr,
4485 => Opcode::tMUL,
4486 => Opcode::tMVN,
4487 => Opcode::tORR,
4488 => Opcode::tPICADD,
4489 => Opcode::tPOP,
4490 => Opcode::tPUSH,
4491 => Opcode::tREV,
4492 => Opcode::tREV16,
4493 => Opcode::tREVSH,
4494 => Opcode::tROR,
4495 => Opcode::tRSB,
4496 => Opcode::tSBC,
4497 => Opcode::tSETEND,
4498 => Opcode::tSTMIA_UPD,
4499 => Opcode::tSTRBi,
4500 => Opcode::tSTRBr,
4501 => Opcode::tSTRHi,
4502 => Opcode::tSTRHr,
4503 => Opcode::tSTRi,
4504 => Opcode::tSTRr,
4505 => Opcode::tSTRspi,
4506 => Opcode::tSUBi3,
4507 => Opcode::tSUBi8,
4508 => Opcode::tSUBrr,
4509 => Opcode::tSUBspi,
4510 => Opcode::tSVC,
4511 => Opcode::tSXTB,
4512 => Opcode::tSXTH,
4513 => Opcode::tTRAP,
4514 => Opcode::tTST,
4515 => Opcode::tUDF,
4516 => Opcode::tUXTB,
4517 => Opcode::tUXTH,
4518 => Opcode::t__brkdiv0,
4519 => Opcode::INSTRUCTION_LIST_END,
_ => Opcode::UNKNOWN(value),
}
}
}