libttl 0.1.1

A library for simulating TTL logic chips
Documentation 
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use libttl::gates::*;
use libttl::logic_level::LogicLevel::{High, Low};

#[test]
fn test_not_gate() {
    let mut gate = NotGate::new();

    gate.update(&[Low]);
    assert_eq!(gate.get_output(0), High);

    gate.update(&[High]);
    assert_eq!(gate.get_output(0), Low);
}

#[test]
fn test_and_gate() {
    let mut gate = AndGate::new();
    let inputs = [(Low, Low), (Low, High), (High, Low), (High, High)];
    let outputs = [Low, Low, Low, High];

    for (i, (in1, in2)) in inputs.iter().enumerate() {
        gate.update(&[*in1, *in2]);
        assert_eq!(gate.get_output(0), outputs[i], "Failed for input {:?}", (*in1, *in2));
    }
}

#[test]
fn test_or_gate() {
    let mut gate = OrGate::new();
    let inputs = [(Low, Low), (Low, High), (High, Low), (High, High)];
    let outputs = [Low, High, High, High];

    for (i, (in1, in2)) in inputs.iter().enumerate() {
        gate.update(&[*in1, *in2]);
        assert_eq!(gate.get_output(0), outputs[i], "Failed for input {:?}", (*in1, *in2));
    }
}

#[test]
fn test_nand_gate() {
    let mut gate = NandGate::new();
    let inputs = [(Low, Low), (Low, High), (High, Low), (High, High)];
    let outputs = [High, High, High, Low];

    for (i, (in1, in2)) in inputs.iter().enumerate() {
        gate.update(&[*in1, *in2]);
        assert_eq!(gate.get_output(0), outputs[i], "Failed for input {:?}", (*in1, *in2));
    }
}

#[test]
#[should_panic]
fn test_gate_update_wrong_input_count() {
    let mut gate = AndGate::new();
    gate.update(&[Low]); // Only one input provided
}

#[test]
#[should_panic]
fn test_gate_get_output_wrong_index() {
     let gate = NotGate::new();
     gate.get_output(1); // Index out of bounds
}