libreda-structural-verilog 0.0.4

Parser for structural verilog as it is created by Yosys.
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# Verilog Netlist I/O for LibrEDA

This crate implements a `NetlistReader` and `NetlistWriter` of the LibrEDA framework for the Verilog netlist format used by Yosys.

Only a subset of Verilog is supported, namely 'structural' or 'netlist' Verilog. Which consists only of modules,
module instantiations and port connections.