libreda_sta/
clock_definition.rs

1// SPDX-FileCopyrightText: 2023 Thomas Kramer <code@tkramer.ch>
2//
3// SPDX-License-Identifier: AGPL-3.0-or-later
4
5//! Datastructures for defining and specifying clock signals.
6
7use num_traits::Zero;
8
9use crate::models::clock_tag::ClockId;
10
11/// Definition of a clock source.
12#[derive(Debug, Clone)]
13pub struct ClockDefinition<Signal> {
14    /// Cycle time of the ideal clock (without any uncertainty).
15    pub(crate) period: uom::si::f64::Time,
16    /// Representation of the rising edge of a clock cycle.
17    /// The `Signal` datatype typically encodes phase/latency and slope.
18    /// Might also encode the clock uncertainty.
19    pub(crate) rising_edge: Signal,
20    /// Representation of the falling edge of a clock cycle.
21    /// The `Signal` datatype typically encodes phase/latency and slope.
22    /// Might also encode the clock uncertainty.
23    pub(crate) falling_edge: Signal,
24    pub(crate) clock_id: Option<ClockId>,
25}
26
27impl<Signal> ClockDefinition<Signal> {
28    /// Create new clock definition.
29    /// # Panics
30    /// Panics if the period is not a positive normal number.
31    pub fn new(period: uom::si::f64::Time, rising_edge: Signal, falling_edge: Signal) -> Self {
32        assert!(
33            period.is_normal() && period.is_sign_positive() && !period.is_zero(),
34            "period must be a positive number but is '{}'",
35            period.value
36        );
37        // TODO: Check that period is larger than delay from rising to falling edge.
38        Self {
39            period,
40            rising_edge,
41            falling_edge,
42            clock_id: None,
43        }
44    }
45}
libreda_sta/clock_definition.rs

libreda_sta/
clock_definition.rs
