libreda-db 0.0.12

Layout and netlist datastructures for chip design.
Documentation 
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// SPDX-FileCopyrightText: 2022 Thomas Kramer
//
// SPDX-License-Identifier: AGPL-3.0-or-later

//! Helper to include all traits and structures related to design rules and technology descriptions.

pub use super::layerstack::*;
pub use super::rules::*;