libmwemu 0.24.5

use crate::*;

// PMULLQ - Multiply Packed Signed Quadword Integers and Store Low Result
//
// Performs a SIMD signed multiply of the packed signed qword integers from
// each element of the first source operand with the corresponding element in
// the second source operand. The low 64 bits of each 128-bit intermediate
// result are stored to the destination operand.
//
// This is an AVX-512DQ instruction available in EVEX encoding only.
//
// Opcodes (AVX-512):
//   EVEX.128.66.0F38.W1 40 /r    VPMULLQ xmm1{k1}{z}, xmm2, xmm3/m128/m64bcst
//   EVEX.256.66.0F38.W1 40 /r    VPMULLQ ymm1{k1}{z}, ymm2, ymm3/m256/m64bcst
//   EVEX.512.66.0F38.W1 40 /r    VPMULLQ zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst

const ALIGNED_ADDR: u64 = 0x3000;

// ============================================================================
// VPMULLQ XMM Tests (128-bit, 2 qwords)
// ============================================================================

#[test]
fn test_vpmullq_xmm_basic() {
    let mut emu = emu64();
    // VPMULLQ XMM0, XMM1, XMM2 - Basic multiplication
    // XMM1: [5, 3]
    // XMM2: [7, 2]
    let code = [
        // Setup XMM1 = [5, 3]
        0x48, 0xb8, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 5
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 3
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [7, 2]
        0x48, 0xb8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 7
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 2
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_zero() {
    let mut emu = emu64();
    // XMM1: [100, 200]
    // XMM2: [0, 0]
    let code = [
        // Setup XMM1 = [100, 200]
        0x48, 0xb8, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 100
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 200
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // XMM2 = [0, 0] (already zero)
        0x66, 0x0f, 0xef, 0xd2, // PXOR XMM2, XMM2

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_one() {
    let mut emu = emu64();
    // XMM1: [42, 99]
    // XMM2: [1, 1]
    let code = [
        // Setup XMM1 = [42, 99]
        0x48, 0xb8, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 42
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 99
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [1, 1]
        0x48, 0xb8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 1
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 1
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_negative() {
    let mut emu = emu64();
    // XMM1: [-5, 10]
    // XMM2: [3, -2]
    let code = [
        // Setup XMM1 = [-5, 10]
        0x48, 0xb8, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // MOV RAX, -5
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 10
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [3, -2]
        0x48, 0xb8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 3
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // MOV RAX, -2
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_overflow() {
    let mut emu = emu64();
    // XMM1: [0x8000000000000000, 0x7FFFFFFFFFFFFFFF]
    // XMM2: [2, 2]
    let code = [
        // Setup XMM1
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, // MOV RAX, 0x8000000000000000
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, // MOV RAX, 0x7FFFFFFFFFFFFFFF
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [2, 2]
        0x48, 0xb8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 2
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_powers_of_two() {
    let mut emu = emu64();
    // XMM1: [16, 256]
    // XMM2: [4, 8]
    let code = [
        // Setup XMM1 = [16, 256]
        0x48, 0xb8, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 16
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xc7, 0xc1, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RCX, 256
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc9, 0x01, // PINSRQ XMM1, RCX, 1

        // Setup XMM2 = [4, 8]
        0x48, 0xb8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 4
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xc7, 0xc1, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RCX, 8
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd1, 0x01, // PINSRQ XMM2, RCX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_large_values() {
    let mut emu = emu64();
    // XMM1: [0x0000000100000000, 0x0000000200000000]
    // XMM2: [0x0000000300000000, 0x0000000400000000]
    let code = [
        // Setup XMM1
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, // MOV RAX, 0x0000000100000000
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, // MOV RAX, 0x0000000200000000
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, // MOV RAX, 0x0000000300000000
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, // MOV RAX, 0x0000000400000000
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

// ============================================================================
// VPMULLQ Memory Operand Tests
// ============================================================================

#[test]
fn test_vpmullq_xmm_memory() {
    let mut emu = emu64();
    // VPMULLQ with memory operand
    let code = [
        // Setup memory at 0x3000 with values [11, 13]
        0x48, 0xb8, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 11
        0x48, 0xa3, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV [0x3000], RAX
        0x48, 0xb8, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 13
        0x48, 0xa3, 0x08, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV [0x3008], RAX

        // Setup XMM1 = [2, 3]
        0x48, 0xb8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 2
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 3
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // VPMULLQ XMM0, XMM1, [0x3000]
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0x04, 0x25, 0x00, 0x30, 0x00, 0x00, // VPMULLQ XMM0, XMM1, [0x3000]

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

// ============================================================================
// VPMULLQ Different Register Combinations
// ============================================================================

#[test]
fn test_vpmullq_xmm_reg_combinations() {
    let mut emu = emu64();
    let code = [
        // Setup XMM3 = [7, 9]
        0x48, 0xb8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 7
        0x66, 0x48, 0x0f, 0x6e, 0xd8, // MOVQ XMM3, RAX
        0x48, 0xb8, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 9
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd8, 0x01, // PINSRQ XMM3, RAX, 1

        // Setup XMM4 = [11, 13]
        0x48, 0xb8, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 11
        0x66, 0x48, 0x0f, 0x6e, 0xe0, // MOVQ XMM4, RAX
        0x48, 0xb8, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 13
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xe0, 0x01, // PINSRQ XMM4, RAX, 1

        // VPMULLQ XMM5, XMM3, XMM4
        0x62, 0xf2, 0xe5, 0x08, 0x40, 0xec, // VPMULLQ XMM5, XMM3, XMM4

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_xmm_same_register() {
    let mut emu = emu64();
    // VPMULLQ with same source registers (square)
    // XMM1: [5, 7]
    // XMM1: [5, 7]
    let code = [
        // Setup XMM1 = [5, 7]
        0x48, 0xb8, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 5
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 7
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM1 (square)
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc1, // VPMULLQ XMM0, XMM1, XMM1

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

// ============================================================================
// VPMULLQ YMM Tests (256-bit, 4 qwords)
// ============================================================================

#[test]
fn test_vpmullq_ymm_basic() {
    let mut emu = emu64();
    // VPMULLQ YMM0, YMM1, YMM2
    let code = [
        // This would require setting up 4 qwords in each YMM register
        // For now, just test that the instruction executes without error

        // VPMULLQ YMM0, YMM1, YMM2
        0x62, 0xf2, 0xf5, 0x28, 0x40, 0xc2, // VPMULLQ YMM0, YMM1, YMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_ymm_different_regs() {
    let mut emu = emu64();
    // VPMULLQ with different YMM register combinations
    let code = [
        // VPMULLQ YMM3, YMM4, YMM5
        0x62, 0xf2, 0xdd, 0x28, 0x40, 0xdd, // VPMULLQ YMM3, YMM4, YMM5

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

// ============================================================================
// VPMULLQ ZMM Tests (512-bit, 8 qwords)
// ============================================================================

#[test]
fn test_vpmullq_zmm_basic() {
    let mut emu = emu64();
    // VPMULLQ ZMM0, ZMM1, ZMM2
    let code = [
        // VPMULLQ ZMM0, ZMM1, ZMM2
        0x62, 0xf2, 0xf5, 0x48, 0x40, 0xc2, // VPMULLQ ZMM0, ZMM1, ZMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_zmm_different_regs() {
    let mut emu = emu64();
    // VPMULLQ with different ZMM register combinations
    let code = [
        // VPMULLQ ZMM7, ZMM6, ZMM5
        0x62, 0xf2, 0xcd, 0x48, 0x40, 0xfd, // VPMULLQ ZMM7, ZMM6, ZMM5

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

// ============================================================================
// Edge Cases and Special Values
// ============================================================================

#[test]
fn test_vpmullq_all_ones() {
    let mut emu = emu64();
    // XMM1: [-1, -1]
    // XMM2: [-1, -1]
    let code = [
        // Setup XMM1 = [-1, -1]
        0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // MOV RAX, -1
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [-1, -1]
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_mixed_signs() {
    let mut emu = emu64();
    // XMM1: [-100, 100]
    // XMM2: [50, -50]
    let code = [
        // Setup XMM1 = [-100, 100]
        0x48, 0xb8, 0x9c, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // MOV RAX, -100
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 100
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [50, -50]
        0x48, 0xb8, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 50
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0xce, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, // MOV RAX, -50
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_sequential_operations() {
    let mut emu = emu64();
    let code = [
        // Setup XMM1 = [2, 3]
        0x48, 0xb8, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 2
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 3
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [4, 5]
        0x48, 0xb8, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 4
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x48, 0xb8, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 5
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // First multiplication: XMM0 = XMM1 * XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        // Second multiplication: XMM3 = XMM0 * XMM1
        0x62, 0xf2, 0xfd, 0x08, 0x40, 0xd9, // VPMULLQ XMM3, XMM0, XMM1

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_high_registers() {
    let mut emu = emu64();
    let code = [
        // VPMULLQ XMM8, XMM9, XMM10
        0x62, 0x72, 0xb5, 0x08, 0x40, 0xc2, // VPMULLQ XMM8, XMM9, XMM10

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}

#[test]
fn test_vpmullq_max_min_values() {
    let mut emu = emu64();
    // XMM1: [0x7FFFFFFFFFFFFFFF, 0x8000000000000000]
    // XMM2: [1, 1]
    let code = [
        // Setup XMM1
        0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, // MOV RAX, 0x7FFFFFFFFFFFFFFF
        0x66, 0x48, 0x0f, 0x6e, 0xc8, // MOVQ XMM1, RAX
        0x48, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, // MOV RAX, 0x8000000000000000
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xc8, 0x01, // PINSRQ XMM1, RAX, 1

        // Setup XMM2 = [1, 1]
        0x48, 0xb8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // MOV RAX, 1
        0x66, 0x48, 0x0f, 0x6e, 0xd0, // MOVQ XMM2, RAX
        0x66, 0x48, 0x0f, 0x3a, 0x22, 0xd0, 0x01, // PINSRQ XMM2, RAX, 1

        // VPMULLQ XMM0, XMM1, XMM2
        0x62, 0xf2, 0xf5, 0x08, 0x40, 0xc2, // VPMULLQ XMM0, XMM1, XMM2

        0xf4, // HLT
    ];
    emu.load_code_bytes(&code);
    emu.run(None).unwrap();
}