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//! All item structure inside
//! `Timing`.
use crate;
use ;
/// The `timing_sense` attribute describes the way an input pin logically affects an output pin.
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =213.11
/// &end
/// =214.6
/// ">Reference-Definition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =203.55
/// &end
/// =203.55
/// ">Reference-Instance</a>
///
///
/// #### Syntax
/// `timing_sense : positive_unate | negative_unate | non_unate ;`
///
/// `positive_unate`: Combines incoming rise delays with local rise delays and
/// compares incoming fall delays with local fall delays.
///
/// `negative_unate`: Combines incoming rise delays with local fall delays and
/// compares incoming fall delays with local rise delays.
///
/// `non_unate`: Combines local delays with the worst-case incoming delay value.
/// The non-unate timing sense represents a function whose output value change cannot
/// be determined from the direction of the change in the input value.
///
/// Timing sense is derived from the logic function of a pin. For example, the value derived for
/// an AND gate is `positive_unate`, the value for a NAND gate is `negative_unate`, and the value
/// for an XOR gate is `non_unate`.
///
/// A function is said to be unate if a rising (falling) change on a positive (negative) unate
/// input variable causes the output function variable to rise (fall) or not change.
/// For a non-unate variable, further state information is required to determine the effects of
/// a particular state transition.
///
/// You can specify half-unate sequential timing arcs if the `timing_type` value is either
/// `rising_edge` or `falling_edge` and the `timing_sense` value is either `positive_unate`
/// or `negative_unate`.
/// + In the case of `rising_edge` and `positive_unate` values, only the `cell_rise` and `rise_transition`
/// information is required.
/// + In the case of `rising_edge` and `negative_unate` values, only the `cell_fall` and `fall_transition`
/// information is required.
/// + In the case of `falling_edge` and `positive_unate` values, only the `cell_rise` and `rise_transition`
/// information is required.
/// + In the case of `falling_edge` and `negative_unate` values, only the `cell_fall` and `fall_transition`
/// information is required.
///
/// Do not define the `timing_sense` value of a pin, except when you need to override the derived value
/// or when you are characterizing a noncombinational gate such as a three-state component. For example,
/// you might want to define the timing sense manually when you model multiple paths between
/// an input pin and an output pin, such as in an XOR gate.
///
/// It is possible that one path is positive unate while another is negative unate. In this case,
/// the first timing arc is given a `positive_unate` designation and the second is given a `negative_unate`
/// designation.
///
/// Timing arcs with a timing type of `clear` or `preset` require a `timing_sense` attribute.
/// If `related_pin` is an output pin, you must define a `timing_sense`` attribute for that pin.
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =213.11
/// &end
/// =214.6
/// ">Reference-Definition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =203.55
/// &end
/// =203.55
/// ">Reference-Instance</a>
/// The `timing_type` attribute distinguishes between combinational
/// and sequential cells by defining the type of timing arc.
/// If this attribute is not assigned, the cell is considered combinational (Default).
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =214.7
/// +214.28
/// +214.50
/// +216.63
/// +217.19
/// &end
/// =214.27
/// +214.49
/// +216.60
/// +217.18
/// +217.35
/// ">Reference-Difinition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =203.56
/// &end
/// =203.70
/// ">Reference-Instance</a>
///
///
/// #### Syntax
/// `timing_type : combinational | combinational_rise | combinational_fall | three_state_disable |
/// three_state_disable_rise | three_state_disable_fall | three_state_enable | three_state_enable_rise |
/// three_state_enable_fall | rising_edge | falling_edge | preset | clear | hold_rising | hold_falling |
/// setup_rising | setup_falling | recovery_rising | recovery_falling | skew_rising | skew_falling |
/// removal_rising | removal_falling | min_pulse_width | minimum_period | max_clock_tree_path |
/// min_clock_tree_path |non_seq_setup_rising | non_seq_setup_falling | non_seq_hold_rising |
/// non_seq_hold_falling | nochange_high_high | nochange_high_low | nochange_low_high | nochange_low_low ;`
///
/// #### Combinational Timing Arcs
/// The timing type and timing sense define the signal propagation pattern. The default timing type is combinational.
/// <table>
/// <thead>
/// <tr>
/// <th>Timing type</th>
/// <th></th>
/// <th>Timing sense</th>
/// <th></th>
/// </tr>
/// <tr>
/// <th></th>
/// <th><code>positive_unate</code></th>
/// <th><code>negative_unate</code></th>
/// <th><code>non_unate</code></th>
/// </tr>
/// </thead>
/// <tbody>
/// <tr>
/// <td><code>combinational</code></td>
/// <td>R->R, F->F</td>
/// <td>R->F, F->R</td>
/// <td>{R,F}->{R,F}</td>
/// </tr>
/// <tr>
/// <td><code>combinational_rise</code></td>
/// <td>R->R</td>
/// <td>F->R</td>
/// <td>{R,F}->R</td>
/// </tr>
/// <tr>
/// <td><code>combinational_fall</code></td>
/// <td>F->F</td>
/// <td>R->F</td>
/// <td>{R,F}->F</td>
/// </tr>
/// <tr>
/// <td><code>three_state_disable</code></td>
/// <td>R->{0Z,1Z}</td>
/// <td>F->{0Z,1Z}</td>
/// <td>{R,F}->{0Z,1Z}</td>
/// </tr>
/// <tr>
/// <td><code>three_state_enable</code></td>
/// <td>R->{Z0,Z1}</td>
/// <td>F->{Z0,Z1}</td>
/// <td>{R,F}->{Z0,Z1}</td>
/// </tr>
/// <tr>
/// <td><code>three_state_disable_rise</code></td>
/// <td>R->0Z</td>
/// <td>F->0Z</td>
/// <td>{R,F}->0Z</td>
/// </tr>
/// <tr>
/// <td><code>three_state_disable_fall</code></td>
/// <td>R->1Z</td>
/// <td>F->1Z</td>
/// <td>{R,F}->1Z</td>
/// </tr>
/// <tr>
/// <td><code>three_state_enable_rise</code></td>
/// <td>R->Z1</td>
/// <td>F->Z1</td>
/// <td>{R,F}->Z1</td>
/// </tr>
/// <tr>
/// <td><code>three_state_enable_fall</code></td>
/// <td>R->Z0</td>
/// <td>F->Z0</td>
/// <td>{R,F}->Z0</td>
/// </tr>
/// </tbody>
/// </table>
///
/// #### Sequential Timing Arcs
/// + `rising_edge`: Identifies a timing arc whose output pin is sensitive to
/// a rising signal at the input pin.
/// + `falling_edge`: Identifies a timing arc whose output pin is sensitive to
/// a falling signal at the input pin.
/// + `preset`: Preset arcs affect only the rise arrival time of the arc’s endpoint pin.
/// A preset arc implies that you are asserting a logic 1 on the output pin when
/// the designated `related_pin` is asserted.
/// + `clear`: Clear arcs affect only the fall arrival time of the arc’s endpoint pin.
/// A clear arc implies that you are asserting a logic 0 on the output pin when
/// the designated `related_pin` is asserted.
/// + `hold_rising`: Designates the rising edge of the related pin for the hold check.
/// + `hold_falling`: Designates the falling edge of the related pin for the hold check.
/// + `setup_rising`: Designates the rising edge of the related pin for the setup check on clocked elements.
/// + `setup_falling`: Designates the falling edge of the related pin for the setup check on clocked elements.
/// + `recovery_rising`: Uses the rising edge of the related pin for the recovery time check.
/// The clock is rising-edge-triggered.
/// + `recovery_falling`: Uses the falling edge of the related pin for the recovery time check.
/// The clock is falling-edge-triggered.
/// + `skew_rising`: The timing constraint interval is measured from the rising edge of
/// the reference pin (specified in `related_pin`) to a transition edge of the parent pin of
/// the timing group. The `intrinsic_rise` value is the maximum skew time between the reference pin rising
/// and the parent pin rising. The `intrinsic_fall` value is the maximum skew time between the reference pin rising
/// and the parent pin falling.
/// + `skew_falling`: The timing constraint interval is measured from the falling edge of
/// the reference pin (specified in `related_pin`) to a transition edge of the parent pin of
/// the timing group. The `intrinsic_rise` value is the maximum skew time between the reference pin falling
/// and the parent pin rising. The `intrinsic_fall` value is the maximum skew time between the reference pin falling
/// and the parent pin falling.
/// + `removal_rising`: Used when the cell is a low-enable latch or a rising-edge-triggered flip-flop.
/// For active-low asynchronous control signals, define the removal time with the `intrinsic_rise` attribute.
/// For active-high asynchronous control signals, define the removal time with the `intrinsic_fall` attribute.
/// + `removal_falling`: Used when the cell is a high-enable latch or a falling-edge-triggered flip-flop.
/// For active-low asynchronous control signals, define the removal time with the `intrinsic_rise` attribute.
/// For active-high asynchronous control signals, define the removal time with the `intrinsic_fall` attribute.
/// + `minimum_pulse_width`: This value, together with the `minimum_period` value, lets you specify
/// the minimum pulse width for a clock pin. The timing check is performed on the pin itself,
/// so the related pin should be the same. As with other timing checks, you can include rise and fall constraints.
/// + `minimum_period`: This value, together with the `minimum_pulse_width` value, lets you specify
/// the minimum pulse width for a clock pin. The timing check is performed on the pin itself,
/// so the related pin should be the same. As with other timing checks, you can include rise and fall constraints.
/// + `max_clock_tree_path`: Used in timing groups under a clock pin. Defines the maximum clock tree path constraint.
/// + `min_clock_tree_path`: Used in timing groups under a clock pin. Defines the minimum clock tree path constraint.
/// #### Example
/// A sample library with the timing_type attribute and minimum_pulse_width and minimum_period values.
/// ``` liberty
/// library(ASIC) {
/// ...
/// delay_model : table_lookup;
/// ...
/// lu_table_template(pulse_width_template) {
/// variable_1 : related_pin_transition;
/// index_1 ("1.0, 2.0, 3.0");
/// }
/// cell(flop) {
/// ...
/// pin(CK) {
/// direction : input;
/// capacitance : 0.00707171;
/// timing() {
/// timing_type : "min_pulse_width";
/// related_pin : "CK";
/// ...
/// rise_constraint("pulse_width_template") {
/// index_1("0.000000, 1.000000, 2.00000");
/// values ("6.000000, 6.250000, 7.2500000" );
/// }
/// fall_constraint("pulse_width_template") {
/// index_1("0.000000, 1.000000, 2.00000");
/// values ("6.000000, 6.250000, 7.2500000" );
/// }
/// }
/// timing() {
/// timing_type : "minimum_period";
/// related_pin : "CK";
/// rise_constraint("pulse_width_template") {
/// index_1(" .000000, 1.000000, 2.00000");
/// values ("6.000000, 6.250000, 7.2500000" );
/// }
/// fall_constraint("pulse_width_template") {
/// index_1("0.000000, 1.000000, 2.00000");
/// values ("6.000000, 6.250000, 7.2500000" );
/// }
/// }
/// }
/// ...
/// } /* end cell */
/// } /* end library */
/// ```
/// #### Nonsequential Timing Arcs
/// In some nonsequential cells, the setup and hold timing constraints are specified on
/// the data pin with a nonclock pin as the `related_pin`. It requires the signal of
/// a pin to be stable for a specified period of time before and after another pin of
/// the same cell range state so that the cell can function as expected.
/// + `non_seq_setup_rising`: Defines (with non_seq_setup_falling) the timing arcs used
/// for setup checks between pins with nonsequential behavior. The related pin in
/// a timing arc is used for the timing check.
/// + `non_seq_setup_falling`: Defines (with non_seq_setup_rising) the timing arcs used
/// for setup checks between pins with nonsequential behavior. The related pin in
/// a timing arc is used for the timing check.
/// + `non_seq_hold_rising`: Defines (with non_seq_hold_falling) the timing arcs used
/// for hold checks between pins with nonsequential behavior. The related pin in
/// a timing arc is used for the timing check.
/// + `non_seq_hold_falling`: Defines (with non_seq_hold_rising) the timing arcs used
/// for hold checks between pins with nonsequential behavior. The related pin in
/// a timing arc is used for the timing check.
/// #### No-Change Timing Arcs
/// This feature models the timing requirement of latch devices with latch-enable signals.
/// The four no-change timing types define the pulse waveforms of both the constrained
/// signal and the related signal in standard CMOS and nonlinear CMOS delay models.
/// The information is used in static timing verification during synthesis.
/// + `nochange_high_high` (positive/positive): Indicates a positive pulse on
/// the constrained pin and a positive pulse on the related pin.
/// + `nochange_high_low` (positive/negative): Indicates a positive pulse on
/// the constrained pin and a negative pulse on the related pin.
/// + `nochange_low_high` (negative/positive): Indicates a negative pulse on
/// the constrained pin and a positive pulse on the related pin.
/// + `nochange_low_low` (negative/negative): Indicates a negative pulse on
/// the constrained pin and a negative pulse on the related pin.
/// You define the mode attribute within a timing group.
/// A mode attribute pertains to an individual timing arc.
/// The timing arc is active when mode is instantiated with a name and a value.
/// You can specify multiple instances of the mode attribute,
/// but only one instance for each timing arc.
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =219.39
/// +220.11
/// &end
/// =220.9
/// +222.73
/// ">Reference-Definition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =204.5
/// &end
/// =204.5
/// ">Reference-Instance</a>
///
/// The `cell_degradation` group describes a cell performance degradation
/// design rule for compiling a design. A cell degradation design rule
/// specifies the maximum capacitive load a cell can drive without causing
/// cell performance degradation during the fall transition.
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =225.4
/// +225.27
/// &end
/// =225.25
/// +227.51
/// ">Reference-Definition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =204.9
/// &end
/// =204.9
/// ">Reference-Instance</a>
///
/// Defines cell delay lookup tables (independently of transition delay) in CMOS nonlinear timing models.
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =227.53
/// +228.27
/// &end
/// =228.25
/// +228.62
/// ">Reference-Definition</a>
/// <a name ="reference_link" href="
/// https://zao111222333.github.io/liberty-rs/2007.03/_user_guide.html
/// ?field=test
/// &bgn
/// =204.10
/// &end
/// =204.10
/// ">Reference-Instance</a>
///
/// **Note:**
/// The same k-factors that scale the cell_fall and cell_rise values also scale the
/// retaining_fall and retaining_rise values. There are no separate k-factors for
/// the retaining_fall and retaining_rise values.
///
/// **Used By:**
/// [Timing](crate::timing::Timing)
///