libcpuname 0.1.3

use super::err::CoreNameError;

// See https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
pub const fn open_core_name(marchid: u64) -> Result<&'static str, CoreNameError> {
    debug_assert!(marchid != 0);

    match marchid {
        1 => Ok("Rocket"),
        2 => Ok("BOOM"),
        3 => Ok("CVA6"),
        4 => Ok("CV32E40P"),
        5 => Ok("Spike"),
        6 => Ok("E-Class"),
        7 => Ok("ORCA"),
        8 => Ok("SCR1"),
        9 => Ok("YARVI"),
        10 => Ok("RVBS"),
        11 => Ok("SweRV EH1"),
        12 => Ok("MSCC"),
        13 => Ok("BlackParrot"),
        14 => Ok("BaseJump Manycore"),
        15 => Ok("C-Class"),
        16 => Ok("SweRV EL2"),
        17 => Ok("SweRV EH2"),
        18 => Ok("SERV"),
        19 => Ok("NEORV32"),
        20 => Ok("CV32E40X"),
        21 => Ok("CV32E40S"),
        22 => Ok("Ibex"),
        23 => Ok("RudolV"),
        24 => Ok("Steel Core"),
        25 => Ok("XiangShan"),
        26 => Ok("Hummingbirdv2 E203"),
        27 => Ok("Hazard3"),
        28 => Ok("CV32E41P"),
        29 => Ok("Rift"),
        30 => Ok("RISu064"),
        31 => Ok("AIRISC"),
        32 => Ok("Proteus"),
        33 => Ok("VexRiscv"),
        34 => Ok("Shuttle"),
        35 => Ok("CV32E2"),
        36 => Ok("Wally"),
        37 => Ok("Boa32"),
        38 => Ok("WIV64"),
        39 => Ok("RV6"),
        40 => Ok("ApogeoRV"),
        41 => Ok("MicroRV32"),
        42 => Ok("QEMU"),
        43 => Ok("KianV"),
        44 => Ok("Coreblocks"),
        45 => Ok("rrv32"),
        46 => Ok("VexiiRiscv"),
        47 => Ok("Wildcat"),
        48 => Ok("CVA5"),
        _ => Err(CoreNameError::NoKnownNamesForMarchid(marchid)),
    }
}

#[cfg(test)]
mod tests {
    use super::*;

    #[test]
    #[should_panic]
    fn invalid_marchid() {
        let _ = open_core_name(0);
    }

    #[test]
    fn valid_inputs_never_panic() {
        for marchid in 1..65535 {
            let _ = open_core_name(marchid);
        }
    }
}