lamina 0.0.10

High-performance compiler backend for Lamina Intermediate Representation
Documentation 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231

//! Utility functions for x86_64 code generation.

use crate::mir::register::{Register, VirtualReg};
use crate::mir::types::MirType;

/// Whether a MirType is a 32-bit float (`f32`).
pub fn is_f32(ty: &MirType) -> bool {
    matches!(ty, MirType::Scalar(crate::mir::types::ScalarType::F32))
}

/// Whether a MirType is a floating-point type (`f32` or `f64`).
pub fn is_float(ty: &MirType) -> bool {
    matches!(
        ty,
        MirType::Scalar(crate::mir::types::ScalarType::F32 | crate::mir::types::ScalarType::F64)
    )
}

/// Load a float operand (stored as integer bits in a GPR stack slot) into an XMM register.
///
/// Strategy: integers hold float bit patterns via `movd` (f32) or `movq` (f64) into xmm.
pub fn load_float_operand_to_xmm<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    operand: &crate::mir::Operand,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
    xmm: &str,
    ty: &MirType,
) -> Result<(), std::io::Error> {
    let mov_to_xmm = if is_f32(ty) { "movd" } else { "movq" };
    match operand {
        crate::mir::Operand::Register(_) => {
            load_operand_to_rax(operand, writer, reg_alloc, stack_slots)?;
            writeln!(writer, "    {} %rax, %{}", mov_to_xmm, xmm)
        }
        crate::mir::Operand::Immediate(imm) => match imm {
            crate::mir::instruction::Immediate::F32(v) => {
                let bits = v.to_bits() as i64;
                writeln!(writer, "    movq ${}, %rax", bits)?;
                writeln!(writer, "    {} %rax, %{}", mov_to_xmm, xmm)
            }
            crate::mir::instruction::Immediate::F64(v) => {
                let bits = v.to_bits() as i64;
                writeln!(writer, "    movq ${}, %rax", bits)?;
                writeln!(writer, "    {} %rax, %{}", mov_to_xmm, xmm)
            }
            _ => {
                // Integer bits treated as float bits
                load_operand_to_rax(operand, writer, reg_alloc, stack_slots)?;
                writeln!(writer, "    {} %rax, %{}", mov_to_xmm, xmm)
            }
        },
    }
}

/// Store the float result from an XMM register back into a virtual register (as integer bits).
pub fn store_xmm_to_register<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    xmm: &str,
    reg: &VirtualReg,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
    ty: &MirType,
) -> Result<(), std::io::Error> {
    let mov_from_xmm = if is_f32(ty) { "movd" } else { "movq" };
    writeln!(writer, "    {} %{}, %rax", mov_from_xmm, xmm)?;
    store_rax_to_register(reg, writer, reg_alloc, stack_slots)
}

/// Load a virtual register into RAX
pub fn load_register_to_rax<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    reg: &VirtualReg,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
) -> Result<(), std::io::Error> {
    if let Some(phys) = reg_alloc.get_mapping(reg) {
        writeln!(writer, "    movq %{}, %rax", phys)?;
    } else if let Some(offset) = stack_slots.get(reg) {
        writeln!(writer, "    movq {}(%rbp), %rax", offset)?;
    } else {
        return Err(std::io::Error::new(
            std::io::ErrorKind::InvalidData,
            format!("Virtual register {:?} has no mapping or stack slot", reg),
        ));
    }
    Ok(())
}

/// Store RAX to a virtual register
pub fn store_rax_to_register<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    reg: &VirtualReg,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
) -> Result<(), std::io::Error> {
    if let Some(phys) = reg_alloc.get_mapping(reg) {
        writeln!(writer, "    movq %rax, %{}", phys)?;
    } else if let Some(offset) = stack_slots.get(reg) {
        writeln!(writer, "    movq %rax, {}(%rbp)", offset)?;
    } else {
        return Err(std::io::Error::new(
            std::io::ErrorKind::InvalidData,
            format!("Virtual register {:?} has no mapping or stack slot", reg),
        ));
    }
    Ok(())
}

/// Load a register to another register
pub fn load_register_to_register<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    src: &VirtualReg,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
    target_reg: &str,
) -> Result<(), std::io::Error> {
    if let Some(phys) = reg_alloc.get_mapping(src) {
        writeln!(writer, "    movq %{}, %{}", phys, target_reg)?;
    } else if let Some(offset) = stack_slots.get(src) {
        writeln!(writer, "    movq {}(%rbp), %{}", offset, target_reg)?;
    } else {
        return Err(std::io::Error::new(
            std::io::ErrorKind::InvalidData,
            format!("Virtual register {:?} has no mapping or stack slot", src),
        ));
    }
    Ok(())
}

/// Load an operand into RAX
pub fn load_operand_to_rax<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    operand: &crate::mir::Operand,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
) -> Result<(), std::io::Error> {
    match operand {
        crate::mir::Operand::Register(reg) => match reg {
            Register::Virtual(v) => load_register_to_rax(v, writer, reg_alloc, stack_slots),
            Register::Physical(p) => {
                writeln!(writer, "    movq %{}, %rax", p.name)?;
                Ok(())
            }
        },
        crate::mir::Operand::Immediate(imm) => match imm {
            crate::mir::instruction::Immediate::I8(v) => {
                writeln!(writer, "    movq ${}, %rax", *v as i64)
            }
            crate::mir::instruction::Immediate::I16(v) => {
                writeln!(writer, "    movq ${}, %rax", *v as i64)
            }
            crate::mir::instruction::Immediate::I32(v) => {
                writeln!(writer, "    movq ${}, %rax", *v as i64)
            }
            crate::mir::instruction::Immediate::I64(v) => writeln!(writer, "    movq ${}, %rax", v),
            crate::mir::instruction::Immediate::F32(_)
            | crate::mir::instruction::Immediate::F64(_) => {
                writeln!(
                    writer,
                    "    # Floating point immediates not yet implemented"
                )?;
                Ok(())
            }
        },
    }
}

/// Load an operand into a specific register
pub fn load_operand_to_register<
    W: std::io::Write,
    RA: crate::mir_codegen::regalloc::RegisterAllocator<PhysReg = &'static str>,
>(
    operand: &crate::mir::Operand,
    writer: &mut W,
    reg_alloc: &RA,
    stack_slots: &std::collections::HashMap<VirtualReg, i32>,
    target_reg: &str,
) -> Result<(), std::io::Error> {
    match operand {
        crate::mir::Operand::Register(reg) => match reg {
            Register::Virtual(v) => {
                load_register_to_register(v, writer, reg_alloc, stack_slots, target_reg)
            }
            Register::Physical(p) => {
                writeln!(writer, "    movq %{}, %{}", p.name, target_reg)?;
                Ok(())
            }
        },
        crate::mir::Operand::Immediate(imm) => match imm {
            crate::mir::instruction::Immediate::I8(v) => {
                writeln!(writer, "    movq ${}, %{}", *v as i64, target_reg)
            }
            crate::mir::instruction::Immediate::I16(v) => {
                writeln!(writer, "    movq ${}, %{}", *v as i64, target_reg)
            }
            crate::mir::instruction::Immediate::I32(v) => {
                writeln!(writer, "    movq ${}, %{}", *v as i64, target_reg)
            }
            crate::mir::instruction::Immediate::I64(v) => {
                writeln!(writer, "    movq ${}, %{}", v, target_reg)
            }
            crate::mir::instruction::Immediate::F32(_)
            | crate::mir::instruction::Immediate::F64(_) => {
                writeln!(
                    writer,
                    "    # Floating point immediates not yet implemented"
                )?;
                Ok(())
            }
        },
    }
}