#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::AC {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `IP`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IPR {
#[doc = "Take no action."]
_0,
#[doc = "A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block."]
_1,
}
impl IPR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IPR::_0 => false,
IPR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IPR {
match value {
false => IPR::_0,
true => IPR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == IPR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == IPR::_1
}
}
#[doc = "Possible values of the field `PS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum PSR {
#[doc = "32-bit port"]
_00,
#[doc = "8-bit port"]
_01,
#[doc = "16-bit port"]
_10,
#[doc = "16-bit port"]
_11,
}
impl PSR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
match *self {
PSR::_00 => 0,
PSR::_01 => 1,
PSR::_10 => 2,
PSR::_11 => 3,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: u8) -> PSR {
match value {
0 => PSR::_00,
1 => PSR::_01,
2 => PSR::_10,
3 => PSR::_11,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `_00`"]
#[inline]
pub fn is_00(&self) -> bool {
*self == PSR::_00
}
#[doc = "Checks if the value of the field is `_01`"]
#[inline]
pub fn is_01(&self) -> bool {
*self == PSR::_01
}
#[doc = "Checks if the value of the field is `_10`"]
#[inline]
pub fn is_10(&self) -> bool {
*self == PSR::_10
}
#[doc = "Checks if the value of the field is `_11`"]
#[inline]
pub fn is_11(&self) -> bool {
*self == PSR::_11
}
}
#[doc = "Possible values of the field `IMRS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum IMRSR {
#[doc = "Take no action"]
_0,
#[doc = "Initiate mrs command"]
_1,
}
impl IMRSR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
IMRSR::_0 => false,
IMRSR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> IMRSR {
match value {
false => IMRSR::_0,
true => IMRSR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == IMRSR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == IMRSR::_1
}
}
#[doc = r" Value of the field"]
pub struct CBMR {
bits: u8,
}
impl CBMR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = r" Value of the field"]
pub struct CASLR {
bits: u8,
}
impl CASLR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u8 {
self.bits
}
}
#[doc = "Possible values of the field `RE`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum RER {
#[doc = "Do not refresh associated DRAM block"]
_0,
#[doc = "Refresh associated DRAM block"]
_1,
}
impl RER {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
RER::_0 => false,
RER::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> RER {
match value {
false => RER::_0,
true => RER::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == RER::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == RER::_1
}
}
#[doc = r" Value of the field"]
pub struct BAR {
bits: u16,
}
impl BAR {
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bits(&self) -> u16 {
self.bits
}
}
#[doc = "Values that can be written to the field `IP`"]
pub enum IPW {
#[doc = "Take no action."]
_0,
#[doc = "A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block."]
_1,
}
impl IPW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
IPW::_0 => false,
IPW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _IPW<'a> {
w: &'a mut W,
}
impl<'a> _IPW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: IPW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Take no action."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(IPW::_0)
}
#[doc = "A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(IPW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 3;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `PS`"]
pub enum PSW {
#[doc = "32-bit port"]
_00,
#[doc = "8-bit port"]
_01,
#[doc = "16-bit port"]
_10,
#[doc = "16-bit port"]
_11,
}
impl PSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> u8 {
match *self {
PSW::_00 => 0,
PSW::_01 => 1,
PSW::_10 => 2,
PSW::_11 => 3,
}
}
}
#[doc = r" Proxy"]
pub struct _PSW<'a> {
w: &'a mut W,
}
impl<'a> _PSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: PSW) -> &'a mut W {
{
self.bits(variant._bits())
}
}
#[doc = "32-bit port"]
#[inline]
pub fn _00(self) -> &'a mut W {
self.variant(PSW::_00)
}
#[doc = "8-bit port"]
#[inline]
pub fn _01(self) -> &'a mut W {
self.variant(PSW::_01)
}
#[doc = "16-bit port"]
#[inline]
pub fn _10(self) -> &'a mut W {
self.variant(PSW::_10)
}
#[doc = "16-bit port"]
#[inline]
pub fn _11(self) -> &'a mut W {
self.variant(PSW::_11)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 4;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `IMRS`"]
pub enum IMRSW {
#[doc = "Take no action"]
_0,
#[doc = "Initiate mrs command"]
_1,
}
impl IMRSW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
IMRSW::_0 => false,
IMRSW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _IMRSW<'a> {
w: &'a mut W,
}
impl<'a> _IMRSW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: IMRSW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Take no action"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(IMRSW::_0)
}
#[doc = "Initiate mrs command"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(IMRSW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 6;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CBMW<'a> {
w: &'a mut W,
}
impl<'a> _CBMW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _CASLW<'a> {
w: &'a mut W,
}
impl<'a> _CASLW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
const MASK: u8 = 3;
const OFFSET: u8 = 12;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `RE`"]
pub enum REW {
#[doc = "Do not refresh associated DRAM block"]
_0,
#[doc = "Refresh associated DRAM block"]
_1,
}
impl REW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
REW::_0 => false,
REW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _REW<'a> {
w: &'a mut W,
}
impl<'a> _REW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: REW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Do not refresh associated DRAM block"]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(REW::_0)
}
#[doc = "Refresh associated DRAM block"]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(REW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 15;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = r" Proxy"]
pub struct _BAW<'a> {
w: &'a mut W,
}
impl<'a> _BAW<'a> {
#[doc = r" Writes raw bits to the field"]
#[inline]
pub unsafe fn bits(self, value: u16) -> &'a mut W {
const MASK: u16 = 16383;
const OFFSET: u8 = 18;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 3 - Initiate precharge all (pall) command."]
#[inline]
pub fn ip(&self) -> IPR {
IPR::_from({
const MASK: bool = true;
const OFFSET: u8 = 3;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 4:5 - Port size."]
#[inline]
pub fn ps(&self) -> PSR {
PSR::_from({
const MASK: u8 = 3;
const OFFSET: u8 = 4;
((self.bits >> OFFSET) & MASK as u32) as u8
})
}
#[doc = "Bit 6 - Initiate mode register set (mrs) command."]
#[inline]
pub fn imrs(&self) -> IMRSR {
IMRSR::_from({
const MASK: bool = true;
const OFFSET: u8 = 6;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 8:10 - Command bit location"]
#[inline]
pub fn cbm(&self) -> CBMR {
let bits = {
const MASK: u8 = 7;
const OFFSET: u8 = 8;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CBMR { bits }
}
#[doc = "Bits 12:13 - CAS Latency"]
#[inline]
pub fn casl(&self) -> CASLR {
let bits = {
const MASK: u8 = 3;
const OFFSET: u8 = 12;
((self.bits >> OFFSET) & MASK as u32) as u8
};
CASLR { bits }
}
#[doc = "Bit 15 - Refresh enable"]
#[inline]
pub fn re(&self) -> RER {
RER::_from({
const MASK: bool = true;
const OFFSET: u8 = 15;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bits 18:31 - Base address register."]
#[inline]
pub fn ba(&self) -> BAR {
let bits = {
const MASK: u16 = 16383;
const OFFSET: u8 = 18;
((self.bits >> OFFSET) & MASK as u32) as u16
};
BAR { bits }
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 0 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 3 - Initiate precharge all (pall) command."]
#[inline]
pub fn ip(&mut self) -> _IPW {
_IPW { w: self }
}
#[doc = "Bits 4:5 - Port size."]
#[inline]
pub fn ps(&mut self) -> _PSW {
_PSW { w: self }
}
#[doc = "Bit 6 - Initiate mode register set (mrs) command."]
#[inline]
pub fn imrs(&mut self) -> _IMRSW {
_IMRSW { w: self }
}
#[doc = "Bits 8:10 - Command bit location"]
#[inline]
pub fn cbm(&mut self) -> _CBMW {
_CBMW { w: self }
}
#[doc = "Bits 12:13 - CAS Latency"]
#[inline]
pub fn casl(&mut self) -> _CASLW {
_CASLW { w: self }
}
#[doc = "Bit 15 - Refresh enable"]
#[inline]
pub fn re(&mut self) -> _REW {
_REW { w: self }
}
#[doc = "Bits 18:31 - Base address register."]
#[inline]
pub fn ba(&mut self) -> _BAW {
_BAW { w: self }
}
}