#[doc = r" Value read from the register"]
pub struct R {
bits: u32,
}
#[doc = r" Value to write to the register"]
pub struct W {
bits: u32,
}
impl super::MCR {
#[doc = r" Modifies the contents of the register"]
#[inline]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
{
let bits = self.register.get();
let r = R { bits: bits };
let mut w = W { bits: bits };
f(&r, &mut w);
self.register.set(w.bits);
}
#[doc = r" Reads the contents of the register"]
#[inline]
pub fn read(&self) -> R {
R {
bits: self.register.get(),
}
}
#[doc = r" Writes to the register"]
#[inline]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W) -> &mut W,
{
let mut w = W::reset_value();
f(&mut w);
self.register.set(w.bits);
}
#[doc = r" Writes the reset value to the register"]
#[inline]
pub fn reset(&self) {
self.write(|w| w)
}
}
#[doc = "Possible values of the field `FRZ`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum FRZR {
#[doc = "Timers continue to run in Debug mode."]
_0,
#[doc = "Timers are stopped in Debug mode."]
_1,
}
impl FRZR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
FRZR::_0 => false,
FRZR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> FRZR {
match value {
false => FRZR::_0,
true => FRZR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == FRZR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == FRZR::_1
}
}
#[doc = "Possible values of the field `MDIS`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum MDISR {
#[doc = "Clock for standard PIT timers is enabled."]
_0,
#[doc = "Clock for standard PIT timers is disabled."]
_1,
}
impl MDISR {
#[doc = r" Returns `true` if the bit is clear (0)"]
#[inline]
pub fn bit_is_clear(&self) -> bool {
!self.bit()
}
#[doc = r" Returns `true` if the bit is set (1)"]
#[inline]
pub fn bit_is_set(&self) -> bool {
self.bit()
}
#[doc = r" Value of the field as raw bits"]
#[inline]
pub fn bit(&self) -> bool {
match *self {
MDISR::_0 => false,
MDISR::_1 => true,
}
}
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _from(value: bool) -> MDISR {
match value {
false => MDISR::_0,
true => MDISR::_1,
}
}
#[doc = "Checks if the value of the field is `_0`"]
#[inline]
pub fn is_0(&self) -> bool {
*self == MDISR::_0
}
#[doc = "Checks if the value of the field is `_1`"]
#[inline]
pub fn is_1(&self) -> bool {
*self == MDISR::_1
}
}
#[doc = "Values that can be written to the field `FRZ`"]
pub enum FRZW {
#[doc = "Timers continue to run in Debug mode."]
_0,
#[doc = "Timers are stopped in Debug mode."]
_1,
}
impl FRZW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
FRZW::_0 => false,
FRZW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _FRZW<'a> {
w: &'a mut W,
}
impl<'a> _FRZW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: FRZW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Timers continue to run in Debug mode."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(FRZW::_0)
}
#[doc = "Timers are stopped in Debug mode."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(FRZW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 0;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
#[doc = "Values that can be written to the field `MDIS`"]
pub enum MDISW {
#[doc = "Clock for standard PIT timers is enabled."]
_0,
#[doc = "Clock for standard PIT timers is disabled."]
_1,
}
impl MDISW {
#[allow(missing_docs)]
#[doc(hidden)]
#[inline]
pub fn _bits(&self) -> bool {
match *self {
MDISW::_0 => false,
MDISW::_1 => true,
}
}
}
#[doc = r" Proxy"]
pub struct _MDISW<'a> {
w: &'a mut W,
}
impl<'a> _MDISW<'a> {
#[doc = r" Writes `variant` to the field"]
#[inline]
pub fn variant(self, variant: MDISW) -> &'a mut W {
{
self.bit(variant._bits())
}
}
#[doc = "Clock for standard PIT timers is enabled."]
#[inline]
pub fn _0(self) -> &'a mut W {
self.variant(MDISW::_0)
}
#[doc = "Clock for standard PIT timers is disabled."]
#[inline]
pub fn _1(self) -> &'a mut W {
self.variant(MDISW::_1)
}
#[doc = r" Sets the field bit"]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r" Clears the field bit"]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r" Writes raw bits to the field"]
#[inline]
pub fn bit(self, value: bool) -> &'a mut W {
const MASK: bool = true;
const OFFSET: u8 = 1;
self.w.bits &= !((MASK as u32) << OFFSET);
self.w.bits |= ((value & MASK) as u32) << OFFSET;
self.w
}
}
impl R {
#[doc = r" Value of the register as raw bits"]
#[inline]
pub fn bits(&self) -> u32 {
self.bits
}
#[doc = "Bit 0 - Freeze"]
#[inline]
pub fn frz(&self) -> FRZR {
FRZR::_from({
const MASK: bool = true;
const OFFSET: u8 = 0;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
#[doc = "Bit 1 - Module Disable - (PIT section)"]
#[inline]
pub fn mdis(&self) -> MDISR {
MDISR::_from({
const MASK: bool = true;
const OFFSET: u8 = 1;
((self.bits >> OFFSET) & MASK as u32) != 0
})
}
}
impl W {
#[doc = r" Reset value of the register"]
#[inline]
pub fn reset_value() -> W {
W { bits: 6 }
}
#[doc = r" Writes raw bits to the register"]
#[inline]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
#[doc = "Bit 0 - Freeze"]
#[inline]
pub fn frz(&mut self) -> _FRZW {
_FRZW { w: self }
}
#[doc = "Bit 1 - Module Disable - (PIT section)"]
#[inline]
pub fn mdis(&mut self) -> _MDISW {
_MDISW { w: self }
}
}