1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5impl super::SR {
6 #[doc = r" Reads the contents of the register"]
7 #[inline]
8 pub fn read(&self) -> R {
9 R {
10 bits: self.register.get(),
11 }
12 }
13}
14#[doc = "Possible values of the field `SECV`"]
15#[derive(Clone, Copy, Debug, PartialEq)]
16pub enum SECVR {
17 #[doc = "No security violation"]
18 _0,
19 #[doc = "Security violation"]
20 _1,
21}
22impl SECVR {
23 #[doc = r" Returns `true` if the bit is clear (0)"]
24 #[inline]
25 pub fn bit_is_clear(&self) -> bool {
26 !self.bit()
27 }
28 #[doc = r" Returns `true` if the bit is set (1)"]
29 #[inline]
30 pub fn bit_is_set(&self) -> bool {
31 self.bit()
32 }
33 #[doc = r" Value of the field as raw bits"]
34 #[inline]
35 pub fn bit(&self) -> bool {
36 match *self {
37 SECVR::_0 => false,
38 SECVR::_1 => true,
39 }
40 }
41 #[allow(missing_docs)]
42 #[doc(hidden)]
43 #[inline]
44 pub fn _from(value: bool) -> SECVR {
45 match value {
46 false => SECVR::_0,
47 true => SECVR::_1,
48 }
49 }
50 #[doc = "Checks if the value of the field is `_0`"]
51 #[inline]
52 pub fn is_0(&self) -> bool {
53 *self == SECVR::_0
54 }
55 #[doc = "Checks if the value of the field is `_1`"]
56 #[inline]
57 pub fn is_1(&self) -> bool {
58 *self == SECVR::_1
59 }
60}
61#[doc = "Possible values of the field `LRS`"]
62#[derive(Clone, Copy, Debug, PartialEq)]
63pub enum LRSR {
64 #[doc = "No underflow"]
65 _0,
66 #[doc = "Underflow"]
67 _1,
68}
69impl LRSR {
70 #[doc = r" Returns `true` if the bit is clear (0)"]
71 #[inline]
72 pub fn bit_is_clear(&self) -> bool {
73 !self.bit()
74 }
75 #[doc = r" Returns `true` if the bit is set (1)"]
76 #[inline]
77 pub fn bit_is_set(&self) -> bool {
78 self.bit()
79 }
80 #[doc = r" Value of the field as raw bits"]
81 #[inline]
82 pub fn bit(&self) -> bool {
83 match *self {
84 LRSR::_0 => false,
85 LRSR::_1 => true,
86 }
87 }
88 #[allow(missing_docs)]
89 #[doc(hidden)]
90 #[inline]
91 pub fn _from(value: bool) -> LRSR {
92 match value {
93 false => LRSR::_0,
94 true => LRSR::_1,
95 }
96 }
97 #[doc = "Checks if the value of the field is `_0`"]
98 #[inline]
99 pub fn is_0(&self) -> bool {
100 *self == LRSR::_0
101 }
102 #[doc = "Checks if the value of the field is `_1`"]
103 #[inline]
104 pub fn is_1(&self) -> bool {
105 *self == LRSR::_1
106 }
107}
108#[doc = "Possible values of the field `ORU`"]
109#[derive(Clone, Copy, Debug, PartialEq)]
110pub enum ORUR {
111 #[doc = "No underflow"]
112 _0,
113 #[doc = "Underflow"]
114 _1,
115}
116impl ORUR {
117 #[doc = r" Returns `true` if the bit is clear (0)"]
118 #[inline]
119 pub fn bit_is_clear(&self) -> bool {
120 !self.bit()
121 }
122 #[doc = r" Returns `true` if the bit is set (1)"]
123 #[inline]
124 pub fn bit_is_set(&self) -> bool {
125 self.bit()
126 }
127 #[doc = r" Value of the field as raw bits"]
128 #[inline]
129 pub fn bit(&self) -> bool {
130 match *self {
131 ORUR::_0 => false,
132 ORUR::_1 => true,
133 }
134 }
135 #[allow(missing_docs)]
136 #[doc(hidden)]
137 #[inline]
138 pub fn _from(value: bool) -> ORUR {
139 match value {
140 false => ORUR::_0,
141 true => ORUR::_1,
142 }
143 }
144 #[doc = "Checks if the value of the field is `_0`"]
145 #[inline]
146 pub fn is_0(&self) -> bool {
147 *self == ORUR::_0
148 }
149 #[doc = "Checks if the value of the field is `_1`"]
150 #[inline]
151 pub fn is_1(&self) -> bool {
152 *self == ORUR::_1
153 }
154}
155#[doc = "Possible values of the field `ERRI`"]
156#[derive(Clone, Copy, Debug, PartialEq)]
157pub enum ERRIR {
158 #[doc = "No underflow"]
159 _0,
160 #[doc = "Underflow"]
161 _1,
162}
163impl ERRIR {
164 #[doc = r" Returns `true` if the bit is clear (0)"]
165 #[inline]
166 pub fn bit_is_clear(&self) -> bool {
167 !self.bit()
168 }
169 #[doc = r" Returns `true` if the bit is set (1)"]
170 #[inline]
171 pub fn bit_is_set(&self) -> bool {
172 self.bit()
173 }
174 #[doc = r" Value of the field as raw bits"]
175 #[inline]
176 pub fn bit(&self) -> bool {
177 match *self {
178 ERRIR::_0 => false,
179 ERRIR::_1 => true,
180 }
181 }
182 #[allow(missing_docs)]
183 #[doc(hidden)]
184 #[inline]
185 pub fn _from(value: bool) -> ERRIR {
186 match value {
187 false => ERRIR::_0,
188 true => ERRIR::_1,
189 }
190 }
191 #[doc = "Checks if the value of the field is `_0`"]
192 #[inline]
193 pub fn is_0(&self) -> bool {
194 *self == ERRIR::_0
195 }
196 #[doc = "Checks if the value of the field is `_1`"]
197 #[inline]
198 pub fn is_1(&self) -> bool {
199 *self == ERRIR::_1
200 }
201}
202#[doc = "Possible values of the field `SLP`"]
203#[derive(Clone, Copy, Debug, PartialEq)]
204pub enum SLPR {
205 #[doc = "Normal mode"]
206 _0,
207 #[doc = "Sleep (low-power) mode"]
208 _1,
209}
210impl SLPR {
211 #[doc = r" Returns `true` if the bit is clear (0)"]
212 #[inline]
213 pub fn bit_is_clear(&self) -> bool {
214 !self.bit()
215 }
216 #[doc = r" Returns `true` if the bit is set (1)"]
217 #[inline]
218 pub fn bit_is_set(&self) -> bool {
219 self.bit()
220 }
221 #[doc = r" Value of the field as raw bits"]
222 #[inline]
223 pub fn bit(&self) -> bool {
224 match *self {
225 SLPR::_0 => false,
226 SLPR::_1 => true,
227 }
228 }
229 #[allow(missing_docs)]
230 #[doc(hidden)]
231 #[inline]
232 pub fn _from(value: bool) -> SLPR {
233 match value {
234 false => SLPR::_0,
235 true => SLPR::_1,
236 }
237 }
238 #[doc = "Checks if the value of the field is `_0`"]
239 #[inline]
240 pub fn is_0(&self) -> bool {
241 *self == SLPR::_0
242 }
243 #[doc = "Checks if the value of the field is `_1`"]
244 #[inline]
245 pub fn is_1(&self) -> bool {
246 *self == SLPR::_1
247 }
248}
249#[doc = "Possible values of the field `OREG_LVL`"]
250#[derive(Clone, Copy, Debug, PartialEq)]
251pub enum OREG_LVLR {
252 #[doc = "No words (empty)"]
253 _0,
254 #[doc = "One word (valid)"]
255 _1,
256 #[doc = r" Reserved"]
257 _Reserved(u8),
258}
259impl OREG_LVLR {
260 #[doc = r" Value of the field as raw bits"]
261 #[inline]
262 pub fn bits(&self) -> u8 {
263 match *self {
264 OREG_LVLR::_0 => 0,
265 OREG_LVLR::_1 => 1,
266 OREG_LVLR::_Reserved(bits) => bits,
267 }
268 }
269 #[allow(missing_docs)]
270 #[doc(hidden)]
271 #[inline]
272 pub fn _from(value: u8) -> OREG_LVLR {
273 match value {
274 0 => OREG_LVLR::_0,
275 1 => OREG_LVLR::_1,
276 i => OREG_LVLR::_Reserved(i),
277 }
278 }
279 #[doc = "Checks if the value of the field is `_0`"]
280 #[inline]
281 pub fn is_0(&self) -> bool {
282 *self == OREG_LVLR::_0
283 }
284 #[doc = "Checks if the value of the field is `_1`"]
285 #[inline]
286 pub fn is_1(&self) -> bool {
287 *self == OREG_LVLR::_1
288 }
289}
290#[doc = "Possible values of the field `OREG_SIZE`"]
291#[derive(Clone, Copy, Debug, PartialEq)]
292pub enum OREG_SIZER {
293 #[doc = "One word (this value is fixed)"]
294 _1,
295 #[doc = r" Reserved"]
296 _Reserved(u8),
297}
298impl OREG_SIZER {
299 #[doc = r" Value of the field as raw bits"]
300 #[inline]
301 pub fn bits(&self) -> u8 {
302 match *self {
303 OREG_SIZER::_1 => 1,
304 OREG_SIZER::_Reserved(bits) => bits,
305 }
306 }
307 #[allow(missing_docs)]
308 #[doc(hidden)]
309 #[inline]
310 pub fn _from(value: u8) -> OREG_SIZER {
311 match value {
312 1 => OREG_SIZER::_1,
313 i => OREG_SIZER::_Reserved(i),
314 }
315 }
316 #[doc = "Checks if the value of the field is `_1`"]
317 #[inline]
318 pub fn is_1(&self) -> bool {
319 *self == OREG_SIZER::_1
320 }
321}
322impl R {
323 #[doc = r" Value of the register as raw bits"]
324 #[inline]
325 pub fn bits(&self) -> u32 {
326 self.bits
327 }
328 #[doc = "Bit 0 - Security Violation"]
329 #[inline]
330 pub fn secv(&self) -> SECVR {
331 SECVR::_from({
332 const MASK: bool = true;
333 const OFFSET: u8 = 0;
334 ((self.bits >> OFFSET) & MASK as u32) != 0
335 })
336 }
337 #[doc = "Bit 1 - Last Read Status"]
338 #[inline]
339 pub fn lrs(&self) -> LRSR {
340 LRSR::_from({
341 const MASK: bool = true;
342 const OFFSET: u8 = 1;
343 ((self.bits >> OFFSET) & MASK as u32) != 0
344 })
345 }
346 #[doc = "Bit 2 - Output Register Underflow"]
347 #[inline]
348 pub fn oru(&self) -> ORUR {
349 ORUR::_from({
350 const MASK: bool = true;
351 const OFFSET: u8 = 2;
352 ((self.bits >> OFFSET) & MASK as u32) != 0
353 })
354 }
355 #[doc = "Bit 3 - Error Interrupt"]
356 #[inline]
357 pub fn erri(&self) -> ERRIR {
358 ERRIR::_from({
359 const MASK: bool = true;
360 const OFFSET: u8 = 3;
361 ((self.bits >> OFFSET) & MASK as u32) != 0
362 })
363 }
364 #[doc = "Bit 4 - Sleep"]
365 #[inline]
366 pub fn slp(&self) -> SLPR {
367 SLPR::_from({
368 const MASK: bool = true;
369 const OFFSET: u8 = 4;
370 ((self.bits >> OFFSET) & MASK as u32) != 0
371 })
372 }
373 #[doc = "Bits 8:15 - Output Register Level"]
374 #[inline]
375 pub fn oreg_lvl(&self) -> OREG_LVLR {
376 OREG_LVLR::_from({
377 const MASK: u8 = 255;
378 const OFFSET: u8 = 8;
379 ((self.bits >> OFFSET) & MASK as u32) as u8
380 })
381 }
382 #[doc = "Bits 16:23 - Output Register Size"]
383 #[inline]
384 pub fn oreg_size(&self) -> OREG_SIZER {
385 OREG_SIZER::_from({
386 const MASK: u8 = 255;
387 const OFFSET: u8 = 16;
388 ((self.bits >> OFFSET) & MASK as u32) as u8
389 })
390 }
391}