1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::CESR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `VLD`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum VLDR {
48 #[doc = "MPU is disabled. All accesses from all bus masters are allowed."]
49 _0,
50 #[doc = "MPU is enabled"]
51 _1,
52}
53impl VLDR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 VLDR::_0 => false,
69 VLDR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> VLDR {
76 match value {
77 false => VLDR::_0,
78 true => VLDR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == VLDR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == VLDR::_1
90 }
91}
92#[doc = "Possible values of the field `NRGD`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum NRGDR {
95 #[doc = "8 region descriptors"]
96 _0000,
97 #[doc = "12 region descriptors"]
98 _0001,
99 #[doc = "16 region descriptors"]
100 _0010,
101 #[doc = r" Reserved"]
102 _Reserved(u8),
103}
104impl NRGDR {
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bits(&self) -> u8 {
108 match *self {
109 NRGDR::_0000 => 0,
110 NRGDR::_0001 => 1,
111 NRGDR::_0010 => 2,
112 NRGDR::_Reserved(bits) => bits,
113 }
114 }
115 #[allow(missing_docs)]
116 #[doc(hidden)]
117 #[inline]
118 pub fn _from(value: u8) -> NRGDR {
119 match value {
120 0 => NRGDR::_0000,
121 1 => NRGDR::_0001,
122 2 => NRGDR::_0010,
123 i => NRGDR::_Reserved(i),
124 }
125 }
126 #[doc = "Checks if the value of the field is `_0000`"]
127 #[inline]
128 pub fn is_0000(&self) -> bool {
129 *self == NRGDR::_0000
130 }
131 #[doc = "Checks if the value of the field is `_0001`"]
132 #[inline]
133 pub fn is_0001(&self) -> bool {
134 *self == NRGDR::_0001
135 }
136 #[doc = "Checks if the value of the field is `_0010`"]
137 #[inline]
138 pub fn is_0010(&self) -> bool {
139 *self == NRGDR::_0010
140 }
141}
142#[doc = r" Value of the field"]
143pub struct NSPR {
144 bits: u8,
145}
146impl NSPR {
147 #[doc = r" Value of the field as raw bits"]
148 #[inline]
149 pub fn bits(&self) -> u8 {
150 self.bits
151 }
152}
153#[doc = r" Value of the field"]
154pub struct HRLR {
155 bits: u8,
156}
157impl HRLR {
158 #[doc = r" Value of the field as raw bits"]
159 #[inline]
160 pub fn bits(&self) -> u8 {
161 self.bits
162 }
163}
164#[doc = "Possible values of the field `SPERR`"]
165#[derive(Clone, Copy, Debug, PartialEq)]
166pub enum SPERRR {
167 #[doc = "No error has occurred for slave port n."]
168 _0,
169 #[doc = "An error has occurred for slave port n."]
170 _1,
171 #[doc = r" Reserved"]
172 _Reserved(u8),
173}
174impl SPERRR {
175 #[doc = r" Value of the field as raw bits"]
176 #[inline]
177 pub fn bits(&self) -> u8 {
178 match *self {
179 SPERRR::_0 => 0,
180 SPERRR::_1 => 1,
181 SPERRR::_Reserved(bits) => bits,
182 }
183 }
184 #[allow(missing_docs)]
185 #[doc(hidden)]
186 #[inline]
187 pub fn _from(value: u8) -> SPERRR {
188 match value {
189 0 => SPERRR::_0,
190 1 => SPERRR::_1,
191 i => SPERRR::_Reserved(i),
192 }
193 }
194 #[doc = "Checks if the value of the field is `_0`"]
195 #[inline]
196 pub fn is_0(&self) -> bool {
197 *self == SPERRR::_0
198 }
199 #[doc = "Checks if the value of the field is `_1`"]
200 #[inline]
201 pub fn is_1(&self) -> bool {
202 *self == SPERRR::_1
203 }
204}
205#[doc = "Values that can be written to the field `VLD`"]
206pub enum VLDW {
207 #[doc = "MPU is disabled. All accesses from all bus masters are allowed."]
208 _0,
209 #[doc = "MPU is enabled"]
210 _1,
211}
212impl VLDW {
213 #[allow(missing_docs)]
214 #[doc(hidden)]
215 #[inline]
216 pub fn _bits(&self) -> bool {
217 match *self {
218 VLDW::_0 => false,
219 VLDW::_1 => true,
220 }
221 }
222}
223#[doc = r" Proxy"]
224pub struct _VLDW<'a> {
225 w: &'a mut W,
226}
227impl<'a> _VLDW<'a> {
228 #[doc = r" Writes `variant` to the field"]
229 #[inline]
230 pub fn variant(self, variant: VLDW) -> &'a mut W {
231 {
232 self.bit(variant._bits())
233 }
234 }
235 #[doc = "MPU is disabled. All accesses from all bus masters are allowed."]
236 #[inline]
237 pub fn _0(self) -> &'a mut W {
238 self.variant(VLDW::_0)
239 }
240 #[doc = "MPU is enabled"]
241 #[inline]
242 pub fn _1(self) -> &'a mut W {
243 self.variant(VLDW::_1)
244 }
245 #[doc = r" Sets the field bit"]
246 pub fn set_bit(self) -> &'a mut W {
247 self.bit(true)
248 }
249 #[doc = r" Clears the field bit"]
250 pub fn clear_bit(self) -> &'a mut W {
251 self.bit(false)
252 }
253 #[doc = r" Writes raw bits to the field"]
254 #[inline]
255 pub fn bit(self, value: bool) -> &'a mut W {
256 const MASK: bool = true;
257 const OFFSET: u8 = 0;
258 self.w.bits &= !((MASK as u32) << OFFSET);
259 self.w.bits |= ((value & MASK) as u32) << OFFSET;
260 self.w
261 }
262}
263#[doc = "Values that can be written to the field `SPERR`"]
264pub enum SPERRW {
265 #[doc = "No error has occurred for slave port n."]
266 _0,
267 #[doc = "An error has occurred for slave port n."]
268 _1,
269}
270impl SPERRW {
271 #[allow(missing_docs)]
272 #[doc(hidden)]
273 #[inline]
274 pub fn _bits(&self) -> u8 {
275 match *self {
276 SPERRW::_0 => 0,
277 SPERRW::_1 => 1,
278 }
279 }
280}
281#[doc = r" Proxy"]
282pub struct _SPERRW<'a> {
283 w: &'a mut W,
284}
285impl<'a> _SPERRW<'a> {
286 #[doc = r" Writes `variant` to the field"]
287 #[inline]
288 pub fn variant(self, variant: SPERRW) -> &'a mut W {
289 unsafe { self.bits(variant._bits()) }
290 }
291 #[doc = "No error has occurred for slave port n."]
292 #[inline]
293 pub fn _0(self) -> &'a mut W {
294 self.variant(SPERRW::_0)
295 }
296 #[doc = "An error has occurred for slave port n."]
297 #[inline]
298 pub fn _1(self) -> &'a mut W {
299 self.variant(SPERRW::_1)
300 }
301 #[doc = r" Writes raw bits to the field"]
302 #[inline]
303 pub unsafe fn bits(self, value: u8) -> &'a mut W {
304 const MASK: u8 = 31;
305 const OFFSET: u8 = 27;
306 self.w.bits &= !((MASK as u32) << OFFSET);
307 self.w.bits |= ((value & MASK) as u32) << OFFSET;
308 self.w
309 }
310}
311impl R {
312 #[doc = r" Value of the register as raw bits"]
313 #[inline]
314 pub fn bits(&self) -> u32 {
315 self.bits
316 }
317 #[doc = "Bit 0 - Valid"]
318 #[inline]
319 pub fn vld(&self) -> VLDR {
320 VLDR::_from({
321 const MASK: bool = true;
322 const OFFSET: u8 = 0;
323 ((self.bits >> OFFSET) & MASK as u32) != 0
324 })
325 }
326 #[doc = "Bits 8:11 - Number Of Region Descriptors"]
327 #[inline]
328 pub fn nrgd(&self) -> NRGDR {
329 NRGDR::_from({
330 const MASK: u8 = 15;
331 const OFFSET: u8 = 8;
332 ((self.bits >> OFFSET) & MASK as u32) as u8
333 })
334 }
335 #[doc = "Bits 12:15 - Number Of Slave Ports"]
336 #[inline]
337 pub fn nsp(&self) -> NSPR {
338 let bits = {
339 const MASK: u8 = 15;
340 const OFFSET: u8 = 12;
341 ((self.bits >> OFFSET) & MASK as u32) as u8
342 };
343 NSPR { bits }
344 }
345 #[doc = "Bits 16:19 - Hardware Revision Level"]
346 #[inline]
347 pub fn hrl(&self) -> HRLR {
348 let bits = {
349 const MASK: u8 = 15;
350 const OFFSET: u8 = 16;
351 ((self.bits >> OFFSET) & MASK as u32) as u8
352 };
353 HRLR { bits }
354 }
355 #[doc = "Bits 27:31 - Slave Port n Error"]
356 #[inline]
357 pub fn sperr(&self) -> SPERRR {
358 SPERRR::_from({
359 const MASK: u8 = 31;
360 const OFFSET: u8 = 27;
361 ((self.bits >> OFFSET) & MASK as u32) as u8
362 })
363 }
364}
365impl W {
366 #[doc = r" Reset value of the register"]
367 #[inline]
368 pub fn reset_value() -> W {
369 W { bits: 8474881 }
370 }
371 #[doc = r" Writes raw bits to the register"]
372 #[inline]
373 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
374 self.bits = bits;
375 self
376 }
377 #[doc = "Bit 0 - Valid"]
378 #[inline]
379 pub fn vld(&mut self) -> _VLDW {
380 _VLDW { w: self }
381 }
382 #[doc = "Bits 27:31 - Slave Port n Error"]
383 #[inline]
384 pub fn sperr(&mut self) -> _SPERRW {
385 _SPERRW { w: self }
386 }
387}