1#[doc = r" Value read from the register"]
2pub struct R {
3 bits: u32,
4}
5#[doc = r" Value to write to the register"]
6pub struct W {
7 bits: u32,
8}
9impl super::MCR {
10 #[doc = r" Modifies the contents of the register"]
11 #[inline]
12 pub fn modify<F>(&self, f: F)
13 where
14 for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
15 {
16 let bits = self.register.get();
17 let r = R { bits: bits };
18 let mut w = W { bits: bits };
19 f(&r, &mut w);
20 self.register.set(w.bits);
21 }
22 #[doc = r" Reads the contents of the register"]
23 #[inline]
24 pub fn read(&self) -> R {
25 R {
26 bits: self.register.get(),
27 }
28 }
29 #[doc = r" Writes to the register"]
30 #[inline]
31 pub fn write<F>(&self, f: F)
32 where
33 F: FnOnce(&mut W) -> &mut W,
34 {
35 let mut w = W::reset_value();
36 f(&mut w);
37 self.register.set(w.bits);
38 }
39 #[doc = r" Writes the reset value to the register"]
40 #[inline]
41 pub fn reset(&self) {
42 self.write(|w| w)
43 }
44}
45#[doc = "Possible values of the field `HALT`"]
46#[derive(Clone, Copy, Debug, PartialEq)]
47pub enum HALTR {
48 #[doc = "Start transfers."]
49 _0,
50 #[doc = "Stop transfers."]
51 _1,
52}
53impl HALTR {
54 #[doc = r" Returns `true` if the bit is clear (0)"]
55 #[inline]
56 pub fn bit_is_clear(&self) -> bool {
57 !self.bit()
58 }
59 #[doc = r" Returns `true` if the bit is set (1)"]
60 #[inline]
61 pub fn bit_is_set(&self) -> bool {
62 self.bit()
63 }
64 #[doc = r" Value of the field as raw bits"]
65 #[inline]
66 pub fn bit(&self) -> bool {
67 match *self {
68 HALTR::_0 => false,
69 HALTR::_1 => true,
70 }
71 }
72 #[allow(missing_docs)]
73 #[doc(hidden)]
74 #[inline]
75 pub fn _from(value: bool) -> HALTR {
76 match value {
77 false => HALTR::_0,
78 true => HALTR::_1,
79 }
80 }
81 #[doc = "Checks if the value of the field is `_0`"]
82 #[inline]
83 pub fn is_0(&self) -> bool {
84 *self == HALTR::_0
85 }
86 #[doc = "Checks if the value of the field is `_1`"]
87 #[inline]
88 pub fn is_1(&self) -> bool {
89 *self == HALTR::_1
90 }
91}
92#[doc = "Possible values of the field `SMPL_PT`"]
93#[derive(Clone, Copy, Debug, PartialEq)]
94pub enum SMPL_PTR {
95 #[doc = "0 protocol clock cycles between SCK edge and SIN sample"]
96 _00,
97 #[doc = "1 protocol clock cycle between SCK edge and SIN sample"]
98 _01,
99 #[doc = "2 protocol clock cycles between SCK edge and SIN sample"]
100 _10,
101 #[doc = r" Reserved"]
102 _Reserved(u8),
103}
104impl SMPL_PTR {
105 #[doc = r" Value of the field as raw bits"]
106 #[inline]
107 pub fn bits(&self) -> u8 {
108 match *self {
109 SMPL_PTR::_00 => 0,
110 SMPL_PTR::_01 => 1,
111 SMPL_PTR::_10 => 2,
112 SMPL_PTR::_Reserved(bits) => bits,
113 }
114 }
115 #[allow(missing_docs)]
116 #[doc(hidden)]
117 #[inline]
118 pub fn _from(value: u8) -> SMPL_PTR {
119 match value {
120 0 => SMPL_PTR::_00,
121 1 => SMPL_PTR::_01,
122 2 => SMPL_PTR::_10,
123 i => SMPL_PTR::_Reserved(i),
124 }
125 }
126 #[doc = "Checks if the value of the field is `_00`"]
127 #[inline]
128 pub fn is_00(&self) -> bool {
129 *self == SMPL_PTR::_00
130 }
131 #[doc = "Checks if the value of the field is `_01`"]
132 #[inline]
133 pub fn is_01(&self) -> bool {
134 *self == SMPL_PTR::_01
135 }
136 #[doc = "Checks if the value of the field is `_10`"]
137 #[inline]
138 pub fn is_10(&self) -> bool {
139 *self == SMPL_PTR::_10
140 }
141}
142#[doc = "Possible values of the field `DIS_RXF`"]
143#[derive(Clone, Copy, Debug, PartialEq)]
144pub enum DIS_RXFR {
145 #[doc = "RX FIFO is enabled."]
146 _0,
147 #[doc = "RX FIFO is disabled."]
148 _1,
149}
150impl DIS_RXFR {
151 #[doc = r" Returns `true` if the bit is clear (0)"]
152 #[inline]
153 pub fn bit_is_clear(&self) -> bool {
154 !self.bit()
155 }
156 #[doc = r" Returns `true` if the bit is set (1)"]
157 #[inline]
158 pub fn bit_is_set(&self) -> bool {
159 self.bit()
160 }
161 #[doc = r" Value of the field as raw bits"]
162 #[inline]
163 pub fn bit(&self) -> bool {
164 match *self {
165 DIS_RXFR::_0 => false,
166 DIS_RXFR::_1 => true,
167 }
168 }
169 #[allow(missing_docs)]
170 #[doc(hidden)]
171 #[inline]
172 pub fn _from(value: bool) -> DIS_RXFR {
173 match value {
174 false => DIS_RXFR::_0,
175 true => DIS_RXFR::_1,
176 }
177 }
178 #[doc = "Checks if the value of the field is `_0`"]
179 #[inline]
180 pub fn is_0(&self) -> bool {
181 *self == DIS_RXFR::_0
182 }
183 #[doc = "Checks if the value of the field is `_1`"]
184 #[inline]
185 pub fn is_1(&self) -> bool {
186 *self == DIS_RXFR::_1
187 }
188}
189#[doc = "Possible values of the field `DIS_TXF`"]
190#[derive(Clone, Copy, Debug, PartialEq)]
191pub enum DIS_TXFR {
192 #[doc = "TX FIFO is enabled."]
193 _0,
194 #[doc = "TX FIFO is disabled."]
195 _1,
196}
197impl DIS_TXFR {
198 #[doc = r" Returns `true` if the bit is clear (0)"]
199 #[inline]
200 pub fn bit_is_clear(&self) -> bool {
201 !self.bit()
202 }
203 #[doc = r" Returns `true` if the bit is set (1)"]
204 #[inline]
205 pub fn bit_is_set(&self) -> bool {
206 self.bit()
207 }
208 #[doc = r" Value of the field as raw bits"]
209 #[inline]
210 pub fn bit(&self) -> bool {
211 match *self {
212 DIS_TXFR::_0 => false,
213 DIS_TXFR::_1 => true,
214 }
215 }
216 #[allow(missing_docs)]
217 #[doc(hidden)]
218 #[inline]
219 pub fn _from(value: bool) -> DIS_TXFR {
220 match value {
221 false => DIS_TXFR::_0,
222 true => DIS_TXFR::_1,
223 }
224 }
225 #[doc = "Checks if the value of the field is `_0`"]
226 #[inline]
227 pub fn is_0(&self) -> bool {
228 *self == DIS_TXFR::_0
229 }
230 #[doc = "Checks if the value of the field is `_1`"]
231 #[inline]
232 pub fn is_1(&self) -> bool {
233 *self == DIS_TXFR::_1
234 }
235}
236#[doc = "Possible values of the field `MDIS`"]
237#[derive(Clone, Copy, Debug, PartialEq)]
238pub enum MDISR {
239 #[doc = "Enables the module clocks."]
240 _0,
241 #[doc = "Allows external logic to disable the module clocks."]
242 _1,
243}
244impl MDISR {
245 #[doc = r" Returns `true` if the bit is clear (0)"]
246 #[inline]
247 pub fn bit_is_clear(&self) -> bool {
248 !self.bit()
249 }
250 #[doc = r" Returns `true` if the bit is set (1)"]
251 #[inline]
252 pub fn bit_is_set(&self) -> bool {
253 self.bit()
254 }
255 #[doc = r" Value of the field as raw bits"]
256 #[inline]
257 pub fn bit(&self) -> bool {
258 match *self {
259 MDISR::_0 => false,
260 MDISR::_1 => true,
261 }
262 }
263 #[allow(missing_docs)]
264 #[doc(hidden)]
265 #[inline]
266 pub fn _from(value: bool) -> MDISR {
267 match value {
268 false => MDISR::_0,
269 true => MDISR::_1,
270 }
271 }
272 #[doc = "Checks if the value of the field is `_0`"]
273 #[inline]
274 pub fn is_0(&self) -> bool {
275 *self == MDISR::_0
276 }
277 #[doc = "Checks if the value of the field is `_1`"]
278 #[inline]
279 pub fn is_1(&self) -> bool {
280 *self == MDISR::_1
281 }
282}
283#[doc = "Possible values of the field `DOZE`"]
284#[derive(Clone, Copy, Debug, PartialEq)]
285pub enum DOZER {
286 #[doc = "Doze mode has no effect on the module."]
287 _0,
288 #[doc = "Doze mode disables the module."]
289 _1,
290}
291impl DOZER {
292 #[doc = r" Returns `true` if the bit is clear (0)"]
293 #[inline]
294 pub fn bit_is_clear(&self) -> bool {
295 !self.bit()
296 }
297 #[doc = r" Returns `true` if the bit is set (1)"]
298 #[inline]
299 pub fn bit_is_set(&self) -> bool {
300 self.bit()
301 }
302 #[doc = r" Value of the field as raw bits"]
303 #[inline]
304 pub fn bit(&self) -> bool {
305 match *self {
306 DOZER::_0 => false,
307 DOZER::_1 => true,
308 }
309 }
310 #[allow(missing_docs)]
311 #[doc(hidden)]
312 #[inline]
313 pub fn _from(value: bool) -> DOZER {
314 match value {
315 false => DOZER::_0,
316 true => DOZER::_1,
317 }
318 }
319 #[doc = "Checks if the value of the field is `_0`"]
320 #[inline]
321 pub fn is_0(&self) -> bool {
322 *self == DOZER::_0
323 }
324 #[doc = "Checks if the value of the field is `_1`"]
325 #[inline]
326 pub fn is_1(&self) -> bool {
327 *self == DOZER::_1
328 }
329}
330#[doc = "Possible values of the field `PCSIS0`"]
331#[derive(Clone, Copy, Debug, PartialEq)]
332pub enum PCSIS0R {
333 #[doc = "The inactive state of PCSx is low."]
334 _0,
335 #[doc = "The inactive state of PCSx is high."]
336 _1,
337}
338impl PCSIS0R {
339 #[doc = r" Returns `true` if the bit is clear (0)"]
340 #[inline]
341 pub fn bit_is_clear(&self) -> bool {
342 !self.bit()
343 }
344 #[doc = r" Returns `true` if the bit is set (1)"]
345 #[inline]
346 pub fn bit_is_set(&self) -> bool {
347 self.bit()
348 }
349 #[doc = r" Value of the field as raw bits"]
350 #[inline]
351 pub fn bit(&self) -> bool {
352 match *self {
353 PCSIS0R::_0 => false,
354 PCSIS0R::_1 => true,
355 }
356 }
357 #[allow(missing_docs)]
358 #[doc(hidden)]
359 #[inline]
360 pub fn _from(value: bool) -> PCSIS0R {
361 match value {
362 false => PCSIS0R::_0,
363 true => PCSIS0R::_1,
364 }
365 }
366 #[doc = "Checks if the value of the field is `_0`"]
367 #[inline]
368 pub fn is_0(&self) -> bool {
369 *self == PCSIS0R::_0
370 }
371 #[doc = "Checks if the value of the field is `_1`"]
372 #[inline]
373 pub fn is_1(&self) -> bool {
374 *self == PCSIS0R::_1
375 }
376}
377#[doc = "Possible values of the field `PCSIS1`"]
378#[derive(Clone, Copy, Debug, PartialEq)]
379pub enum PCSIS1R {
380 #[doc = "The inactive state of PCSx is low."]
381 _0,
382 #[doc = "The inactive state of PCSx is high."]
383 _1,
384}
385impl PCSIS1R {
386 #[doc = r" Returns `true` if the bit is clear (0)"]
387 #[inline]
388 pub fn bit_is_clear(&self) -> bool {
389 !self.bit()
390 }
391 #[doc = r" Returns `true` if the bit is set (1)"]
392 #[inline]
393 pub fn bit_is_set(&self) -> bool {
394 self.bit()
395 }
396 #[doc = r" Value of the field as raw bits"]
397 #[inline]
398 pub fn bit(&self) -> bool {
399 match *self {
400 PCSIS1R::_0 => false,
401 PCSIS1R::_1 => true,
402 }
403 }
404 #[allow(missing_docs)]
405 #[doc(hidden)]
406 #[inline]
407 pub fn _from(value: bool) -> PCSIS1R {
408 match value {
409 false => PCSIS1R::_0,
410 true => PCSIS1R::_1,
411 }
412 }
413 #[doc = "Checks if the value of the field is `_0`"]
414 #[inline]
415 pub fn is_0(&self) -> bool {
416 *self == PCSIS1R::_0
417 }
418 #[doc = "Checks if the value of the field is `_1`"]
419 #[inline]
420 pub fn is_1(&self) -> bool {
421 *self == PCSIS1R::_1
422 }
423}
424#[doc = "Possible values of the field `PCSIS2`"]
425#[derive(Clone, Copy, Debug, PartialEq)]
426pub enum PCSIS2R {
427 #[doc = "The inactive state of PCSx is low."]
428 _0,
429 #[doc = "The inactive state of PCSx is high."]
430 _1,
431}
432impl PCSIS2R {
433 #[doc = r" Returns `true` if the bit is clear (0)"]
434 #[inline]
435 pub fn bit_is_clear(&self) -> bool {
436 !self.bit()
437 }
438 #[doc = r" Returns `true` if the bit is set (1)"]
439 #[inline]
440 pub fn bit_is_set(&self) -> bool {
441 self.bit()
442 }
443 #[doc = r" Value of the field as raw bits"]
444 #[inline]
445 pub fn bit(&self) -> bool {
446 match *self {
447 PCSIS2R::_0 => false,
448 PCSIS2R::_1 => true,
449 }
450 }
451 #[allow(missing_docs)]
452 #[doc(hidden)]
453 #[inline]
454 pub fn _from(value: bool) -> PCSIS2R {
455 match value {
456 false => PCSIS2R::_0,
457 true => PCSIS2R::_1,
458 }
459 }
460 #[doc = "Checks if the value of the field is `_0`"]
461 #[inline]
462 pub fn is_0(&self) -> bool {
463 *self == PCSIS2R::_0
464 }
465 #[doc = "Checks if the value of the field is `_1`"]
466 #[inline]
467 pub fn is_1(&self) -> bool {
468 *self == PCSIS2R::_1
469 }
470}
471#[doc = "Possible values of the field `PCSIS3`"]
472#[derive(Clone, Copy, Debug, PartialEq)]
473pub enum PCSIS3R {
474 #[doc = "The inactive state of PCSx is low."]
475 _0,
476 #[doc = "The inactive state of PCSx is high."]
477 _1,
478}
479impl PCSIS3R {
480 #[doc = r" Returns `true` if the bit is clear (0)"]
481 #[inline]
482 pub fn bit_is_clear(&self) -> bool {
483 !self.bit()
484 }
485 #[doc = r" Returns `true` if the bit is set (1)"]
486 #[inline]
487 pub fn bit_is_set(&self) -> bool {
488 self.bit()
489 }
490 #[doc = r" Value of the field as raw bits"]
491 #[inline]
492 pub fn bit(&self) -> bool {
493 match *self {
494 PCSIS3R::_0 => false,
495 PCSIS3R::_1 => true,
496 }
497 }
498 #[allow(missing_docs)]
499 #[doc(hidden)]
500 #[inline]
501 pub fn _from(value: bool) -> PCSIS3R {
502 match value {
503 false => PCSIS3R::_0,
504 true => PCSIS3R::_1,
505 }
506 }
507 #[doc = "Checks if the value of the field is `_0`"]
508 #[inline]
509 pub fn is_0(&self) -> bool {
510 *self == PCSIS3R::_0
511 }
512 #[doc = "Checks if the value of the field is `_1`"]
513 #[inline]
514 pub fn is_1(&self) -> bool {
515 *self == PCSIS3R::_1
516 }
517}
518#[doc = "Possible values of the field `PCSIS4`"]
519#[derive(Clone, Copy, Debug, PartialEq)]
520pub enum PCSIS4R {
521 #[doc = "The inactive state of PCSx is low."]
522 _0,
523 #[doc = "The inactive state of PCSx is high."]
524 _1,
525}
526impl PCSIS4R {
527 #[doc = r" Returns `true` if the bit is clear (0)"]
528 #[inline]
529 pub fn bit_is_clear(&self) -> bool {
530 !self.bit()
531 }
532 #[doc = r" Returns `true` if the bit is set (1)"]
533 #[inline]
534 pub fn bit_is_set(&self) -> bool {
535 self.bit()
536 }
537 #[doc = r" Value of the field as raw bits"]
538 #[inline]
539 pub fn bit(&self) -> bool {
540 match *self {
541 PCSIS4R::_0 => false,
542 PCSIS4R::_1 => true,
543 }
544 }
545 #[allow(missing_docs)]
546 #[doc(hidden)]
547 #[inline]
548 pub fn _from(value: bool) -> PCSIS4R {
549 match value {
550 false => PCSIS4R::_0,
551 true => PCSIS4R::_1,
552 }
553 }
554 #[doc = "Checks if the value of the field is `_0`"]
555 #[inline]
556 pub fn is_0(&self) -> bool {
557 *self == PCSIS4R::_0
558 }
559 #[doc = "Checks if the value of the field is `_1`"]
560 #[inline]
561 pub fn is_1(&self) -> bool {
562 *self == PCSIS4R::_1
563 }
564}
565#[doc = "Possible values of the field `PCSIS5`"]
566#[derive(Clone, Copy, Debug, PartialEq)]
567pub enum PCSIS5R {
568 #[doc = "The inactive state of PCSx is low."]
569 _0,
570 #[doc = "The inactive state of PCSx is high."]
571 _1,
572}
573impl PCSIS5R {
574 #[doc = r" Returns `true` if the bit is clear (0)"]
575 #[inline]
576 pub fn bit_is_clear(&self) -> bool {
577 !self.bit()
578 }
579 #[doc = r" Returns `true` if the bit is set (1)"]
580 #[inline]
581 pub fn bit_is_set(&self) -> bool {
582 self.bit()
583 }
584 #[doc = r" Value of the field as raw bits"]
585 #[inline]
586 pub fn bit(&self) -> bool {
587 match *self {
588 PCSIS5R::_0 => false,
589 PCSIS5R::_1 => true,
590 }
591 }
592 #[allow(missing_docs)]
593 #[doc(hidden)]
594 #[inline]
595 pub fn _from(value: bool) -> PCSIS5R {
596 match value {
597 false => PCSIS5R::_0,
598 true => PCSIS5R::_1,
599 }
600 }
601 #[doc = "Checks if the value of the field is `_0`"]
602 #[inline]
603 pub fn is_0(&self) -> bool {
604 *self == PCSIS5R::_0
605 }
606 #[doc = "Checks if the value of the field is `_1`"]
607 #[inline]
608 pub fn is_1(&self) -> bool {
609 *self == PCSIS5R::_1
610 }
611}
612#[doc = "Possible values of the field `ROOE`"]
613#[derive(Clone, Copy, Debug, PartialEq)]
614pub enum ROOER {
615 #[doc = "Incoming data is ignored."]
616 _0,
617 #[doc = "Incoming data is shifted into the shift register."]
618 _1,
619}
620impl ROOER {
621 #[doc = r" Returns `true` if the bit is clear (0)"]
622 #[inline]
623 pub fn bit_is_clear(&self) -> bool {
624 !self.bit()
625 }
626 #[doc = r" Returns `true` if the bit is set (1)"]
627 #[inline]
628 pub fn bit_is_set(&self) -> bool {
629 self.bit()
630 }
631 #[doc = r" Value of the field as raw bits"]
632 #[inline]
633 pub fn bit(&self) -> bool {
634 match *self {
635 ROOER::_0 => false,
636 ROOER::_1 => true,
637 }
638 }
639 #[allow(missing_docs)]
640 #[doc(hidden)]
641 #[inline]
642 pub fn _from(value: bool) -> ROOER {
643 match value {
644 false => ROOER::_0,
645 true => ROOER::_1,
646 }
647 }
648 #[doc = "Checks if the value of the field is `_0`"]
649 #[inline]
650 pub fn is_0(&self) -> bool {
651 *self == ROOER::_0
652 }
653 #[doc = "Checks if the value of the field is `_1`"]
654 #[inline]
655 pub fn is_1(&self) -> bool {
656 *self == ROOER::_1
657 }
658}
659#[doc = "Possible values of the field `PCSSE`"]
660#[derive(Clone, Copy, Debug, PartialEq)]
661pub enum PCSSER {
662 #[doc = "PCS5/ PCSS is used as the Peripheral Chip Select\\[5\\] signal."]
663 _0,
664 #[doc = "PCS5/ PCSS is used as an active-low PCS Strobe signal."]
665 _1,
666}
667impl PCSSER {
668 #[doc = r" Returns `true` if the bit is clear (0)"]
669 #[inline]
670 pub fn bit_is_clear(&self) -> bool {
671 !self.bit()
672 }
673 #[doc = r" Returns `true` if the bit is set (1)"]
674 #[inline]
675 pub fn bit_is_set(&self) -> bool {
676 self.bit()
677 }
678 #[doc = r" Value of the field as raw bits"]
679 #[inline]
680 pub fn bit(&self) -> bool {
681 match *self {
682 PCSSER::_0 => false,
683 PCSSER::_1 => true,
684 }
685 }
686 #[allow(missing_docs)]
687 #[doc(hidden)]
688 #[inline]
689 pub fn _from(value: bool) -> PCSSER {
690 match value {
691 false => PCSSER::_0,
692 true => PCSSER::_1,
693 }
694 }
695 #[doc = "Checks if the value of the field is `_0`"]
696 #[inline]
697 pub fn is_0(&self) -> bool {
698 *self == PCSSER::_0
699 }
700 #[doc = "Checks if the value of the field is `_1`"]
701 #[inline]
702 pub fn is_1(&self) -> bool {
703 *self == PCSSER::_1
704 }
705}
706#[doc = "Possible values of the field `MTFE`"]
707#[derive(Clone, Copy, Debug, PartialEq)]
708pub enum MTFER {
709 #[doc = "Modified SPI transfer format disabled."]
710 _0,
711 #[doc = "Modified SPI transfer format enabled."]
712 _1,
713}
714impl MTFER {
715 #[doc = r" Returns `true` if the bit is clear (0)"]
716 #[inline]
717 pub fn bit_is_clear(&self) -> bool {
718 !self.bit()
719 }
720 #[doc = r" Returns `true` if the bit is set (1)"]
721 #[inline]
722 pub fn bit_is_set(&self) -> bool {
723 self.bit()
724 }
725 #[doc = r" Value of the field as raw bits"]
726 #[inline]
727 pub fn bit(&self) -> bool {
728 match *self {
729 MTFER::_0 => false,
730 MTFER::_1 => true,
731 }
732 }
733 #[allow(missing_docs)]
734 #[doc(hidden)]
735 #[inline]
736 pub fn _from(value: bool) -> MTFER {
737 match value {
738 false => MTFER::_0,
739 true => MTFER::_1,
740 }
741 }
742 #[doc = "Checks if the value of the field is `_0`"]
743 #[inline]
744 pub fn is_0(&self) -> bool {
745 *self == MTFER::_0
746 }
747 #[doc = "Checks if the value of the field is `_1`"]
748 #[inline]
749 pub fn is_1(&self) -> bool {
750 *self == MTFER::_1
751 }
752}
753#[doc = "Possible values of the field `FRZ`"]
754#[derive(Clone, Copy, Debug, PartialEq)]
755pub enum FRZR {
756 #[doc = "Do not halt serial transfers in Debug mode."]
757 _0,
758 #[doc = "Halt serial transfers in Debug mode."]
759 _1,
760}
761impl FRZR {
762 #[doc = r" Returns `true` if the bit is clear (0)"]
763 #[inline]
764 pub fn bit_is_clear(&self) -> bool {
765 !self.bit()
766 }
767 #[doc = r" Returns `true` if the bit is set (1)"]
768 #[inline]
769 pub fn bit_is_set(&self) -> bool {
770 self.bit()
771 }
772 #[doc = r" Value of the field as raw bits"]
773 #[inline]
774 pub fn bit(&self) -> bool {
775 match *self {
776 FRZR::_0 => false,
777 FRZR::_1 => true,
778 }
779 }
780 #[allow(missing_docs)]
781 #[doc(hidden)]
782 #[inline]
783 pub fn _from(value: bool) -> FRZR {
784 match value {
785 false => FRZR::_0,
786 true => FRZR::_1,
787 }
788 }
789 #[doc = "Checks if the value of the field is `_0`"]
790 #[inline]
791 pub fn is_0(&self) -> bool {
792 *self == FRZR::_0
793 }
794 #[doc = "Checks if the value of the field is `_1`"]
795 #[inline]
796 pub fn is_1(&self) -> bool {
797 *self == FRZR::_1
798 }
799}
800#[doc = "Possible values of the field `DCONF`"]
801#[derive(Clone, Copy, Debug, PartialEq)]
802pub enum DCONFR {
803 #[doc = "SPI"]
804 _00,
805 #[doc = r" Reserved"]
806 _Reserved(u8),
807}
808impl DCONFR {
809 #[doc = r" Value of the field as raw bits"]
810 #[inline]
811 pub fn bits(&self) -> u8 {
812 match *self {
813 DCONFR::_00 => 0,
814 DCONFR::_Reserved(bits) => bits,
815 }
816 }
817 #[allow(missing_docs)]
818 #[doc(hidden)]
819 #[inline]
820 pub fn _from(value: u8) -> DCONFR {
821 match value {
822 0 => DCONFR::_00,
823 i => DCONFR::_Reserved(i),
824 }
825 }
826 #[doc = "Checks if the value of the field is `_00`"]
827 #[inline]
828 pub fn is_00(&self) -> bool {
829 *self == DCONFR::_00
830 }
831}
832#[doc = "Possible values of the field `CONT_SCKE`"]
833#[derive(Clone, Copy, Debug, PartialEq)]
834pub enum CONT_SCKER {
835 #[doc = "Continuous SCK disabled."]
836 _0,
837 #[doc = "Continuous SCK enabled."]
838 _1,
839}
840impl CONT_SCKER {
841 #[doc = r" Returns `true` if the bit is clear (0)"]
842 #[inline]
843 pub fn bit_is_clear(&self) -> bool {
844 !self.bit()
845 }
846 #[doc = r" Returns `true` if the bit is set (1)"]
847 #[inline]
848 pub fn bit_is_set(&self) -> bool {
849 self.bit()
850 }
851 #[doc = r" Value of the field as raw bits"]
852 #[inline]
853 pub fn bit(&self) -> bool {
854 match *self {
855 CONT_SCKER::_0 => false,
856 CONT_SCKER::_1 => true,
857 }
858 }
859 #[allow(missing_docs)]
860 #[doc(hidden)]
861 #[inline]
862 pub fn _from(value: bool) -> CONT_SCKER {
863 match value {
864 false => CONT_SCKER::_0,
865 true => CONT_SCKER::_1,
866 }
867 }
868 #[doc = "Checks if the value of the field is `_0`"]
869 #[inline]
870 pub fn is_0(&self) -> bool {
871 *self == CONT_SCKER::_0
872 }
873 #[doc = "Checks if the value of the field is `_1`"]
874 #[inline]
875 pub fn is_1(&self) -> bool {
876 *self == CONT_SCKER::_1
877 }
878}
879#[doc = "Possible values of the field `MSTR`"]
880#[derive(Clone, Copy, Debug, PartialEq)]
881pub enum MSTRR {
882 #[doc = "Enables Slave mode"]
883 _0,
884 #[doc = "Enables Master mode"]
885 _1,
886}
887impl MSTRR {
888 #[doc = r" Returns `true` if the bit is clear (0)"]
889 #[inline]
890 pub fn bit_is_clear(&self) -> bool {
891 !self.bit()
892 }
893 #[doc = r" Returns `true` if the bit is set (1)"]
894 #[inline]
895 pub fn bit_is_set(&self) -> bool {
896 self.bit()
897 }
898 #[doc = r" Value of the field as raw bits"]
899 #[inline]
900 pub fn bit(&self) -> bool {
901 match *self {
902 MSTRR::_0 => false,
903 MSTRR::_1 => true,
904 }
905 }
906 #[allow(missing_docs)]
907 #[doc(hidden)]
908 #[inline]
909 pub fn _from(value: bool) -> MSTRR {
910 match value {
911 false => MSTRR::_0,
912 true => MSTRR::_1,
913 }
914 }
915 #[doc = "Checks if the value of the field is `_0`"]
916 #[inline]
917 pub fn is_0(&self) -> bool {
918 *self == MSTRR::_0
919 }
920 #[doc = "Checks if the value of the field is `_1`"]
921 #[inline]
922 pub fn is_1(&self) -> bool {
923 *self == MSTRR::_1
924 }
925}
926#[doc = "Values that can be written to the field `HALT`"]
927pub enum HALTW {
928 #[doc = "Start transfers."]
929 _0,
930 #[doc = "Stop transfers."]
931 _1,
932}
933impl HALTW {
934 #[allow(missing_docs)]
935 #[doc(hidden)]
936 #[inline]
937 pub fn _bits(&self) -> bool {
938 match *self {
939 HALTW::_0 => false,
940 HALTW::_1 => true,
941 }
942 }
943}
944#[doc = r" Proxy"]
945pub struct _HALTW<'a> {
946 w: &'a mut W,
947}
948impl<'a> _HALTW<'a> {
949 #[doc = r" Writes `variant` to the field"]
950 #[inline]
951 pub fn variant(self, variant: HALTW) -> &'a mut W {
952 {
953 self.bit(variant._bits())
954 }
955 }
956 #[doc = "Start transfers."]
957 #[inline]
958 pub fn _0(self) -> &'a mut W {
959 self.variant(HALTW::_0)
960 }
961 #[doc = "Stop transfers."]
962 #[inline]
963 pub fn _1(self) -> &'a mut W {
964 self.variant(HALTW::_1)
965 }
966 #[doc = r" Sets the field bit"]
967 pub fn set_bit(self) -> &'a mut W {
968 self.bit(true)
969 }
970 #[doc = r" Clears the field bit"]
971 pub fn clear_bit(self) -> &'a mut W {
972 self.bit(false)
973 }
974 #[doc = r" Writes raw bits to the field"]
975 #[inline]
976 pub fn bit(self, value: bool) -> &'a mut W {
977 const MASK: bool = true;
978 const OFFSET: u8 = 0;
979 self.w.bits &= !((MASK as u32) << OFFSET);
980 self.w.bits |= ((value & MASK) as u32) << OFFSET;
981 self.w
982 }
983}
984#[doc = "Values that can be written to the field `SMPL_PT`"]
985pub enum SMPL_PTW {
986 #[doc = "0 protocol clock cycles between SCK edge and SIN sample"]
987 _00,
988 #[doc = "1 protocol clock cycle between SCK edge and SIN sample"]
989 _01,
990 #[doc = "2 protocol clock cycles between SCK edge and SIN sample"]
991 _10,
992}
993impl SMPL_PTW {
994 #[allow(missing_docs)]
995 #[doc(hidden)]
996 #[inline]
997 pub fn _bits(&self) -> u8 {
998 match *self {
999 SMPL_PTW::_00 => 0,
1000 SMPL_PTW::_01 => 1,
1001 SMPL_PTW::_10 => 2,
1002 }
1003 }
1004}
1005#[doc = r" Proxy"]
1006pub struct _SMPL_PTW<'a> {
1007 w: &'a mut W,
1008}
1009impl<'a> _SMPL_PTW<'a> {
1010 #[doc = r" Writes `variant` to the field"]
1011 #[inline]
1012 pub fn variant(self, variant: SMPL_PTW) -> &'a mut W {
1013 unsafe { self.bits(variant._bits()) }
1014 }
1015 #[doc = "0 protocol clock cycles between SCK edge and SIN sample"]
1016 #[inline]
1017 pub fn _00(self) -> &'a mut W {
1018 self.variant(SMPL_PTW::_00)
1019 }
1020 #[doc = "1 protocol clock cycle between SCK edge and SIN sample"]
1021 #[inline]
1022 pub fn _01(self) -> &'a mut W {
1023 self.variant(SMPL_PTW::_01)
1024 }
1025 #[doc = "2 protocol clock cycles between SCK edge and SIN sample"]
1026 #[inline]
1027 pub fn _10(self) -> &'a mut W {
1028 self.variant(SMPL_PTW::_10)
1029 }
1030 #[doc = r" Writes raw bits to the field"]
1031 #[inline]
1032 pub unsafe fn bits(self, value: u8) -> &'a mut W {
1033 const MASK: u8 = 3;
1034 const OFFSET: u8 = 8;
1035 self.w.bits &= !((MASK as u32) << OFFSET);
1036 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1037 self.w
1038 }
1039}
1040#[doc = "Values that can be written to the field `CLR_RXF`"]
1041pub enum CLR_RXFW {
1042 #[doc = "Do not clear the RX FIFO counter."]
1043 _0,
1044 #[doc = "Clear the RX FIFO counter."]
1045 _1,
1046}
1047impl CLR_RXFW {
1048 #[allow(missing_docs)]
1049 #[doc(hidden)]
1050 #[inline]
1051 pub fn _bits(&self) -> bool {
1052 match *self {
1053 CLR_RXFW::_0 => false,
1054 CLR_RXFW::_1 => true,
1055 }
1056 }
1057}
1058#[doc = r" Proxy"]
1059pub struct _CLR_RXFW<'a> {
1060 w: &'a mut W,
1061}
1062impl<'a> _CLR_RXFW<'a> {
1063 #[doc = r" Writes `variant` to the field"]
1064 #[inline]
1065 pub fn variant(self, variant: CLR_RXFW) -> &'a mut W {
1066 {
1067 self.bit(variant._bits())
1068 }
1069 }
1070 #[doc = "Do not clear the RX FIFO counter."]
1071 #[inline]
1072 pub fn _0(self) -> &'a mut W {
1073 self.variant(CLR_RXFW::_0)
1074 }
1075 #[doc = "Clear the RX FIFO counter."]
1076 #[inline]
1077 pub fn _1(self) -> &'a mut W {
1078 self.variant(CLR_RXFW::_1)
1079 }
1080 #[doc = r" Sets the field bit"]
1081 pub fn set_bit(self) -> &'a mut W {
1082 self.bit(true)
1083 }
1084 #[doc = r" Clears the field bit"]
1085 pub fn clear_bit(self) -> &'a mut W {
1086 self.bit(false)
1087 }
1088 #[doc = r" Writes raw bits to the field"]
1089 #[inline]
1090 pub fn bit(self, value: bool) -> &'a mut W {
1091 const MASK: bool = true;
1092 const OFFSET: u8 = 10;
1093 self.w.bits &= !((MASK as u32) << OFFSET);
1094 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1095 self.w
1096 }
1097}
1098#[doc = "Values that can be written to the field `CLR_TXF`"]
1099pub enum CLR_TXFW {
1100 #[doc = "Do not clear the TX FIFO counter."]
1101 _0,
1102 #[doc = "Clear the TX FIFO counter."]
1103 _1,
1104}
1105impl CLR_TXFW {
1106 #[allow(missing_docs)]
1107 #[doc(hidden)]
1108 #[inline]
1109 pub fn _bits(&self) -> bool {
1110 match *self {
1111 CLR_TXFW::_0 => false,
1112 CLR_TXFW::_1 => true,
1113 }
1114 }
1115}
1116#[doc = r" Proxy"]
1117pub struct _CLR_TXFW<'a> {
1118 w: &'a mut W,
1119}
1120impl<'a> _CLR_TXFW<'a> {
1121 #[doc = r" Writes `variant` to the field"]
1122 #[inline]
1123 pub fn variant(self, variant: CLR_TXFW) -> &'a mut W {
1124 {
1125 self.bit(variant._bits())
1126 }
1127 }
1128 #[doc = "Do not clear the TX FIFO counter."]
1129 #[inline]
1130 pub fn _0(self) -> &'a mut W {
1131 self.variant(CLR_TXFW::_0)
1132 }
1133 #[doc = "Clear the TX FIFO counter."]
1134 #[inline]
1135 pub fn _1(self) -> &'a mut W {
1136 self.variant(CLR_TXFW::_1)
1137 }
1138 #[doc = r" Sets the field bit"]
1139 pub fn set_bit(self) -> &'a mut W {
1140 self.bit(true)
1141 }
1142 #[doc = r" Clears the field bit"]
1143 pub fn clear_bit(self) -> &'a mut W {
1144 self.bit(false)
1145 }
1146 #[doc = r" Writes raw bits to the field"]
1147 #[inline]
1148 pub fn bit(self, value: bool) -> &'a mut W {
1149 const MASK: bool = true;
1150 const OFFSET: u8 = 11;
1151 self.w.bits &= !((MASK as u32) << OFFSET);
1152 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1153 self.w
1154 }
1155}
1156#[doc = "Values that can be written to the field `DIS_RXF`"]
1157pub enum DIS_RXFW {
1158 #[doc = "RX FIFO is enabled."]
1159 _0,
1160 #[doc = "RX FIFO is disabled."]
1161 _1,
1162}
1163impl DIS_RXFW {
1164 #[allow(missing_docs)]
1165 #[doc(hidden)]
1166 #[inline]
1167 pub fn _bits(&self) -> bool {
1168 match *self {
1169 DIS_RXFW::_0 => false,
1170 DIS_RXFW::_1 => true,
1171 }
1172 }
1173}
1174#[doc = r" Proxy"]
1175pub struct _DIS_RXFW<'a> {
1176 w: &'a mut W,
1177}
1178impl<'a> _DIS_RXFW<'a> {
1179 #[doc = r" Writes `variant` to the field"]
1180 #[inline]
1181 pub fn variant(self, variant: DIS_RXFW) -> &'a mut W {
1182 {
1183 self.bit(variant._bits())
1184 }
1185 }
1186 #[doc = "RX FIFO is enabled."]
1187 #[inline]
1188 pub fn _0(self) -> &'a mut W {
1189 self.variant(DIS_RXFW::_0)
1190 }
1191 #[doc = "RX FIFO is disabled."]
1192 #[inline]
1193 pub fn _1(self) -> &'a mut W {
1194 self.variant(DIS_RXFW::_1)
1195 }
1196 #[doc = r" Sets the field bit"]
1197 pub fn set_bit(self) -> &'a mut W {
1198 self.bit(true)
1199 }
1200 #[doc = r" Clears the field bit"]
1201 pub fn clear_bit(self) -> &'a mut W {
1202 self.bit(false)
1203 }
1204 #[doc = r" Writes raw bits to the field"]
1205 #[inline]
1206 pub fn bit(self, value: bool) -> &'a mut W {
1207 const MASK: bool = true;
1208 const OFFSET: u8 = 12;
1209 self.w.bits &= !((MASK as u32) << OFFSET);
1210 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1211 self.w
1212 }
1213}
1214#[doc = "Values that can be written to the field `DIS_TXF`"]
1215pub enum DIS_TXFW {
1216 #[doc = "TX FIFO is enabled."]
1217 _0,
1218 #[doc = "TX FIFO is disabled."]
1219 _1,
1220}
1221impl DIS_TXFW {
1222 #[allow(missing_docs)]
1223 #[doc(hidden)]
1224 #[inline]
1225 pub fn _bits(&self) -> bool {
1226 match *self {
1227 DIS_TXFW::_0 => false,
1228 DIS_TXFW::_1 => true,
1229 }
1230 }
1231}
1232#[doc = r" Proxy"]
1233pub struct _DIS_TXFW<'a> {
1234 w: &'a mut W,
1235}
1236impl<'a> _DIS_TXFW<'a> {
1237 #[doc = r" Writes `variant` to the field"]
1238 #[inline]
1239 pub fn variant(self, variant: DIS_TXFW) -> &'a mut W {
1240 {
1241 self.bit(variant._bits())
1242 }
1243 }
1244 #[doc = "TX FIFO is enabled."]
1245 #[inline]
1246 pub fn _0(self) -> &'a mut W {
1247 self.variant(DIS_TXFW::_0)
1248 }
1249 #[doc = "TX FIFO is disabled."]
1250 #[inline]
1251 pub fn _1(self) -> &'a mut W {
1252 self.variant(DIS_TXFW::_1)
1253 }
1254 #[doc = r" Sets the field bit"]
1255 pub fn set_bit(self) -> &'a mut W {
1256 self.bit(true)
1257 }
1258 #[doc = r" Clears the field bit"]
1259 pub fn clear_bit(self) -> &'a mut W {
1260 self.bit(false)
1261 }
1262 #[doc = r" Writes raw bits to the field"]
1263 #[inline]
1264 pub fn bit(self, value: bool) -> &'a mut W {
1265 const MASK: bool = true;
1266 const OFFSET: u8 = 13;
1267 self.w.bits &= !((MASK as u32) << OFFSET);
1268 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1269 self.w
1270 }
1271}
1272#[doc = "Values that can be written to the field `MDIS`"]
1273pub enum MDISW {
1274 #[doc = "Enables the module clocks."]
1275 _0,
1276 #[doc = "Allows external logic to disable the module clocks."]
1277 _1,
1278}
1279impl MDISW {
1280 #[allow(missing_docs)]
1281 #[doc(hidden)]
1282 #[inline]
1283 pub fn _bits(&self) -> bool {
1284 match *self {
1285 MDISW::_0 => false,
1286 MDISW::_1 => true,
1287 }
1288 }
1289}
1290#[doc = r" Proxy"]
1291pub struct _MDISW<'a> {
1292 w: &'a mut W,
1293}
1294impl<'a> _MDISW<'a> {
1295 #[doc = r" Writes `variant` to the field"]
1296 #[inline]
1297 pub fn variant(self, variant: MDISW) -> &'a mut W {
1298 {
1299 self.bit(variant._bits())
1300 }
1301 }
1302 #[doc = "Enables the module clocks."]
1303 #[inline]
1304 pub fn _0(self) -> &'a mut W {
1305 self.variant(MDISW::_0)
1306 }
1307 #[doc = "Allows external logic to disable the module clocks."]
1308 #[inline]
1309 pub fn _1(self) -> &'a mut W {
1310 self.variant(MDISW::_1)
1311 }
1312 #[doc = r" Sets the field bit"]
1313 pub fn set_bit(self) -> &'a mut W {
1314 self.bit(true)
1315 }
1316 #[doc = r" Clears the field bit"]
1317 pub fn clear_bit(self) -> &'a mut W {
1318 self.bit(false)
1319 }
1320 #[doc = r" Writes raw bits to the field"]
1321 #[inline]
1322 pub fn bit(self, value: bool) -> &'a mut W {
1323 const MASK: bool = true;
1324 const OFFSET: u8 = 14;
1325 self.w.bits &= !((MASK as u32) << OFFSET);
1326 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1327 self.w
1328 }
1329}
1330#[doc = "Values that can be written to the field `DOZE`"]
1331pub enum DOZEW {
1332 #[doc = "Doze mode has no effect on the module."]
1333 _0,
1334 #[doc = "Doze mode disables the module."]
1335 _1,
1336}
1337impl DOZEW {
1338 #[allow(missing_docs)]
1339 #[doc(hidden)]
1340 #[inline]
1341 pub fn _bits(&self) -> bool {
1342 match *self {
1343 DOZEW::_0 => false,
1344 DOZEW::_1 => true,
1345 }
1346 }
1347}
1348#[doc = r" Proxy"]
1349pub struct _DOZEW<'a> {
1350 w: &'a mut W,
1351}
1352impl<'a> _DOZEW<'a> {
1353 #[doc = r" Writes `variant` to the field"]
1354 #[inline]
1355 pub fn variant(self, variant: DOZEW) -> &'a mut W {
1356 {
1357 self.bit(variant._bits())
1358 }
1359 }
1360 #[doc = "Doze mode has no effect on the module."]
1361 #[inline]
1362 pub fn _0(self) -> &'a mut W {
1363 self.variant(DOZEW::_0)
1364 }
1365 #[doc = "Doze mode disables the module."]
1366 #[inline]
1367 pub fn _1(self) -> &'a mut W {
1368 self.variant(DOZEW::_1)
1369 }
1370 #[doc = r" Sets the field bit"]
1371 pub fn set_bit(self) -> &'a mut W {
1372 self.bit(true)
1373 }
1374 #[doc = r" Clears the field bit"]
1375 pub fn clear_bit(self) -> &'a mut W {
1376 self.bit(false)
1377 }
1378 #[doc = r" Writes raw bits to the field"]
1379 #[inline]
1380 pub fn bit(self, value: bool) -> &'a mut W {
1381 const MASK: bool = true;
1382 const OFFSET: u8 = 15;
1383 self.w.bits &= !((MASK as u32) << OFFSET);
1384 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1385 self.w
1386 }
1387}
1388#[doc = "Values that can be written to the field `PCSIS0`"]
1389pub enum PCSIS0W {
1390 #[doc = "The inactive state of PCSx is low."]
1391 _0,
1392 #[doc = "The inactive state of PCSx is high."]
1393 _1,
1394}
1395impl PCSIS0W {
1396 #[allow(missing_docs)]
1397 #[doc(hidden)]
1398 #[inline]
1399 pub fn _bits(&self) -> bool {
1400 match *self {
1401 PCSIS0W::_0 => false,
1402 PCSIS0W::_1 => true,
1403 }
1404 }
1405}
1406#[doc = r" Proxy"]
1407pub struct _PCSIS0W<'a> {
1408 w: &'a mut W,
1409}
1410impl<'a> _PCSIS0W<'a> {
1411 #[doc = r" Writes `variant` to the field"]
1412 #[inline]
1413 pub fn variant(self, variant: PCSIS0W) -> &'a mut W {
1414 {
1415 self.bit(variant._bits())
1416 }
1417 }
1418 #[doc = "The inactive state of PCSx is low."]
1419 #[inline]
1420 pub fn _0(self) -> &'a mut W {
1421 self.variant(PCSIS0W::_0)
1422 }
1423 #[doc = "The inactive state of PCSx is high."]
1424 #[inline]
1425 pub fn _1(self) -> &'a mut W {
1426 self.variant(PCSIS0W::_1)
1427 }
1428 #[doc = r" Sets the field bit"]
1429 pub fn set_bit(self) -> &'a mut W {
1430 self.bit(true)
1431 }
1432 #[doc = r" Clears the field bit"]
1433 pub fn clear_bit(self) -> &'a mut W {
1434 self.bit(false)
1435 }
1436 #[doc = r" Writes raw bits to the field"]
1437 #[inline]
1438 pub fn bit(self, value: bool) -> &'a mut W {
1439 const MASK: bool = true;
1440 const OFFSET: u8 = 16;
1441 self.w.bits &= !((MASK as u32) << OFFSET);
1442 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1443 self.w
1444 }
1445}
1446#[doc = "Values that can be written to the field `PCSIS1`"]
1447pub enum PCSIS1W {
1448 #[doc = "The inactive state of PCSx is low."]
1449 _0,
1450 #[doc = "The inactive state of PCSx is high."]
1451 _1,
1452}
1453impl PCSIS1W {
1454 #[allow(missing_docs)]
1455 #[doc(hidden)]
1456 #[inline]
1457 pub fn _bits(&self) -> bool {
1458 match *self {
1459 PCSIS1W::_0 => false,
1460 PCSIS1W::_1 => true,
1461 }
1462 }
1463}
1464#[doc = r" Proxy"]
1465pub struct _PCSIS1W<'a> {
1466 w: &'a mut W,
1467}
1468impl<'a> _PCSIS1W<'a> {
1469 #[doc = r" Writes `variant` to the field"]
1470 #[inline]
1471 pub fn variant(self, variant: PCSIS1W) -> &'a mut W {
1472 {
1473 self.bit(variant._bits())
1474 }
1475 }
1476 #[doc = "The inactive state of PCSx is low."]
1477 #[inline]
1478 pub fn _0(self) -> &'a mut W {
1479 self.variant(PCSIS1W::_0)
1480 }
1481 #[doc = "The inactive state of PCSx is high."]
1482 #[inline]
1483 pub fn _1(self) -> &'a mut W {
1484 self.variant(PCSIS1W::_1)
1485 }
1486 #[doc = r" Sets the field bit"]
1487 pub fn set_bit(self) -> &'a mut W {
1488 self.bit(true)
1489 }
1490 #[doc = r" Clears the field bit"]
1491 pub fn clear_bit(self) -> &'a mut W {
1492 self.bit(false)
1493 }
1494 #[doc = r" Writes raw bits to the field"]
1495 #[inline]
1496 pub fn bit(self, value: bool) -> &'a mut W {
1497 const MASK: bool = true;
1498 const OFFSET: u8 = 17;
1499 self.w.bits &= !((MASK as u32) << OFFSET);
1500 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1501 self.w
1502 }
1503}
1504#[doc = "Values that can be written to the field `PCSIS2`"]
1505pub enum PCSIS2W {
1506 #[doc = "The inactive state of PCSx is low."]
1507 _0,
1508 #[doc = "The inactive state of PCSx is high."]
1509 _1,
1510}
1511impl PCSIS2W {
1512 #[allow(missing_docs)]
1513 #[doc(hidden)]
1514 #[inline]
1515 pub fn _bits(&self) -> bool {
1516 match *self {
1517 PCSIS2W::_0 => false,
1518 PCSIS2W::_1 => true,
1519 }
1520 }
1521}
1522#[doc = r" Proxy"]
1523pub struct _PCSIS2W<'a> {
1524 w: &'a mut W,
1525}
1526impl<'a> _PCSIS2W<'a> {
1527 #[doc = r" Writes `variant` to the field"]
1528 #[inline]
1529 pub fn variant(self, variant: PCSIS2W) -> &'a mut W {
1530 {
1531 self.bit(variant._bits())
1532 }
1533 }
1534 #[doc = "The inactive state of PCSx is low."]
1535 #[inline]
1536 pub fn _0(self) -> &'a mut W {
1537 self.variant(PCSIS2W::_0)
1538 }
1539 #[doc = "The inactive state of PCSx is high."]
1540 #[inline]
1541 pub fn _1(self) -> &'a mut W {
1542 self.variant(PCSIS2W::_1)
1543 }
1544 #[doc = r" Sets the field bit"]
1545 pub fn set_bit(self) -> &'a mut W {
1546 self.bit(true)
1547 }
1548 #[doc = r" Clears the field bit"]
1549 pub fn clear_bit(self) -> &'a mut W {
1550 self.bit(false)
1551 }
1552 #[doc = r" Writes raw bits to the field"]
1553 #[inline]
1554 pub fn bit(self, value: bool) -> &'a mut W {
1555 const MASK: bool = true;
1556 const OFFSET: u8 = 18;
1557 self.w.bits &= !((MASK as u32) << OFFSET);
1558 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1559 self.w
1560 }
1561}
1562#[doc = "Values that can be written to the field `PCSIS3`"]
1563pub enum PCSIS3W {
1564 #[doc = "The inactive state of PCSx is low."]
1565 _0,
1566 #[doc = "The inactive state of PCSx is high."]
1567 _1,
1568}
1569impl PCSIS3W {
1570 #[allow(missing_docs)]
1571 #[doc(hidden)]
1572 #[inline]
1573 pub fn _bits(&self) -> bool {
1574 match *self {
1575 PCSIS3W::_0 => false,
1576 PCSIS3W::_1 => true,
1577 }
1578 }
1579}
1580#[doc = r" Proxy"]
1581pub struct _PCSIS3W<'a> {
1582 w: &'a mut W,
1583}
1584impl<'a> _PCSIS3W<'a> {
1585 #[doc = r" Writes `variant` to the field"]
1586 #[inline]
1587 pub fn variant(self, variant: PCSIS3W) -> &'a mut W {
1588 {
1589 self.bit(variant._bits())
1590 }
1591 }
1592 #[doc = "The inactive state of PCSx is low."]
1593 #[inline]
1594 pub fn _0(self) -> &'a mut W {
1595 self.variant(PCSIS3W::_0)
1596 }
1597 #[doc = "The inactive state of PCSx is high."]
1598 #[inline]
1599 pub fn _1(self) -> &'a mut W {
1600 self.variant(PCSIS3W::_1)
1601 }
1602 #[doc = r" Sets the field bit"]
1603 pub fn set_bit(self) -> &'a mut W {
1604 self.bit(true)
1605 }
1606 #[doc = r" Clears the field bit"]
1607 pub fn clear_bit(self) -> &'a mut W {
1608 self.bit(false)
1609 }
1610 #[doc = r" Writes raw bits to the field"]
1611 #[inline]
1612 pub fn bit(self, value: bool) -> &'a mut W {
1613 const MASK: bool = true;
1614 const OFFSET: u8 = 19;
1615 self.w.bits &= !((MASK as u32) << OFFSET);
1616 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1617 self.w
1618 }
1619}
1620#[doc = "Values that can be written to the field `PCSIS4`"]
1621pub enum PCSIS4W {
1622 #[doc = "The inactive state of PCSx is low."]
1623 _0,
1624 #[doc = "The inactive state of PCSx is high."]
1625 _1,
1626}
1627impl PCSIS4W {
1628 #[allow(missing_docs)]
1629 #[doc(hidden)]
1630 #[inline]
1631 pub fn _bits(&self) -> bool {
1632 match *self {
1633 PCSIS4W::_0 => false,
1634 PCSIS4W::_1 => true,
1635 }
1636 }
1637}
1638#[doc = r" Proxy"]
1639pub struct _PCSIS4W<'a> {
1640 w: &'a mut W,
1641}
1642impl<'a> _PCSIS4W<'a> {
1643 #[doc = r" Writes `variant` to the field"]
1644 #[inline]
1645 pub fn variant(self, variant: PCSIS4W) -> &'a mut W {
1646 {
1647 self.bit(variant._bits())
1648 }
1649 }
1650 #[doc = "The inactive state of PCSx is low."]
1651 #[inline]
1652 pub fn _0(self) -> &'a mut W {
1653 self.variant(PCSIS4W::_0)
1654 }
1655 #[doc = "The inactive state of PCSx is high."]
1656 #[inline]
1657 pub fn _1(self) -> &'a mut W {
1658 self.variant(PCSIS4W::_1)
1659 }
1660 #[doc = r" Sets the field bit"]
1661 pub fn set_bit(self) -> &'a mut W {
1662 self.bit(true)
1663 }
1664 #[doc = r" Clears the field bit"]
1665 pub fn clear_bit(self) -> &'a mut W {
1666 self.bit(false)
1667 }
1668 #[doc = r" Writes raw bits to the field"]
1669 #[inline]
1670 pub fn bit(self, value: bool) -> &'a mut W {
1671 const MASK: bool = true;
1672 const OFFSET: u8 = 20;
1673 self.w.bits &= !((MASK as u32) << OFFSET);
1674 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1675 self.w
1676 }
1677}
1678#[doc = "Values that can be written to the field `PCSIS5`"]
1679pub enum PCSIS5W {
1680 #[doc = "The inactive state of PCSx is low."]
1681 _0,
1682 #[doc = "The inactive state of PCSx is high."]
1683 _1,
1684}
1685impl PCSIS5W {
1686 #[allow(missing_docs)]
1687 #[doc(hidden)]
1688 #[inline]
1689 pub fn _bits(&self) -> bool {
1690 match *self {
1691 PCSIS5W::_0 => false,
1692 PCSIS5W::_1 => true,
1693 }
1694 }
1695}
1696#[doc = r" Proxy"]
1697pub struct _PCSIS5W<'a> {
1698 w: &'a mut W,
1699}
1700impl<'a> _PCSIS5W<'a> {
1701 #[doc = r" Writes `variant` to the field"]
1702 #[inline]
1703 pub fn variant(self, variant: PCSIS5W) -> &'a mut W {
1704 {
1705 self.bit(variant._bits())
1706 }
1707 }
1708 #[doc = "The inactive state of PCSx is low."]
1709 #[inline]
1710 pub fn _0(self) -> &'a mut W {
1711 self.variant(PCSIS5W::_0)
1712 }
1713 #[doc = "The inactive state of PCSx is high."]
1714 #[inline]
1715 pub fn _1(self) -> &'a mut W {
1716 self.variant(PCSIS5W::_1)
1717 }
1718 #[doc = r" Sets the field bit"]
1719 pub fn set_bit(self) -> &'a mut W {
1720 self.bit(true)
1721 }
1722 #[doc = r" Clears the field bit"]
1723 pub fn clear_bit(self) -> &'a mut W {
1724 self.bit(false)
1725 }
1726 #[doc = r" Writes raw bits to the field"]
1727 #[inline]
1728 pub fn bit(self, value: bool) -> &'a mut W {
1729 const MASK: bool = true;
1730 const OFFSET: u8 = 21;
1731 self.w.bits &= !((MASK as u32) << OFFSET);
1732 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1733 self.w
1734 }
1735}
1736#[doc = "Values that can be written to the field `ROOE`"]
1737pub enum ROOEW {
1738 #[doc = "Incoming data is ignored."]
1739 _0,
1740 #[doc = "Incoming data is shifted into the shift register."]
1741 _1,
1742}
1743impl ROOEW {
1744 #[allow(missing_docs)]
1745 #[doc(hidden)]
1746 #[inline]
1747 pub fn _bits(&self) -> bool {
1748 match *self {
1749 ROOEW::_0 => false,
1750 ROOEW::_1 => true,
1751 }
1752 }
1753}
1754#[doc = r" Proxy"]
1755pub struct _ROOEW<'a> {
1756 w: &'a mut W,
1757}
1758impl<'a> _ROOEW<'a> {
1759 #[doc = r" Writes `variant` to the field"]
1760 #[inline]
1761 pub fn variant(self, variant: ROOEW) -> &'a mut W {
1762 {
1763 self.bit(variant._bits())
1764 }
1765 }
1766 #[doc = "Incoming data is ignored."]
1767 #[inline]
1768 pub fn _0(self) -> &'a mut W {
1769 self.variant(ROOEW::_0)
1770 }
1771 #[doc = "Incoming data is shifted into the shift register."]
1772 #[inline]
1773 pub fn _1(self) -> &'a mut W {
1774 self.variant(ROOEW::_1)
1775 }
1776 #[doc = r" Sets the field bit"]
1777 pub fn set_bit(self) -> &'a mut W {
1778 self.bit(true)
1779 }
1780 #[doc = r" Clears the field bit"]
1781 pub fn clear_bit(self) -> &'a mut W {
1782 self.bit(false)
1783 }
1784 #[doc = r" Writes raw bits to the field"]
1785 #[inline]
1786 pub fn bit(self, value: bool) -> &'a mut W {
1787 const MASK: bool = true;
1788 const OFFSET: u8 = 24;
1789 self.w.bits &= !((MASK as u32) << OFFSET);
1790 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1791 self.w
1792 }
1793}
1794#[doc = "Values that can be written to the field `PCSSE`"]
1795pub enum PCSSEW {
1796 #[doc = "PCS5/ PCSS is used as the Peripheral Chip Select\\[5\\] signal."]
1797 _0,
1798 #[doc = "PCS5/ PCSS is used as an active-low PCS Strobe signal."]
1799 _1,
1800}
1801impl PCSSEW {
1802 #[allow(missing_docs)]
1803 #[doc(hidden)]
1804 #[inline]
1805 pub fn _bits(&self) -> bool {
1806 match *self {
1807 PCSSEW::_0 => false,
1808 PCSSEW::_1 => true,
1809 }
1810 }
1811}
1812#[doc = r" Proxy"]
1813pub struct _PCSSEW<'a> {
1814 w: &'a mut W,
1815}
1816impl<'a> _PCSSEW<'a> {
1817 #[doc = r" Writes `variant` to the field"]
1818 #[inline]
1819 pub fn variant(self, variant: PCSSEW) -> &'a mut W {
1820 {
1821 self.bit(variant._bits())
1822 }
1823 }
1824 #[doc = "PCS5/ PCSS is used as the Peripheral Chip Select\\[5\\] signal."]
1825 #[inline]
1826 pub fn _0(self) -> &'a mut W {
1827 self.variant(PCSSEW::_0)
1828 }
1829 #[doc = "PCS5/ PCSS is used as an active-low PCS Strobe signal."]
1830 #[inline]
1831 pub fn _1(self) -> &'a mut W {
1832 self.variant(PCSSEW::_1)
1833 }
1834 #[doc = r" Sets the field bit"]
1835 pub fn set_bit(self) -> &'a mut W {
1836 self.bit(true)
1837 }
1838 #[doc = r" Clears the field bit"]
1839 pub fn clear_bit(self) -> &'a mut W {
1840 self.bit(false)
1841 }
1842 #[doc = r" Writes raw bits to the field"]
1843 #[inline]
1844 pub fn bit(self, value: bool) -> &'a mut W {
1845 const MASK: bool = true;
1846 const OFFSET: u8 = 25;
1847 self.w.bits &= !((MASK as u32) << OFFSET);
1848 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1849 self.w
1850 }
1851}
1852#[doc = "Values that can be written to the field `MTFE`"]
1853pub enum MTFEW {
1854 #[doc = "Modified SPI transfer format disabled."]
1855 _0,
1856 #[doc = "Modified SPI transfer format enabled."]
1857 _1,
1858}
1859impl MTFEW {
1860 #[allow(missing_docs)]
1861 #[doc(hidden)]
1862 #[inline]
1863 pub fn _bits(&self) -> bool {
1864 match *self {
1865 MTFEW::_0 => false,
1866 MTFEW::_1 => true,
1867 }
1868 }
1869}
1870#[doc = r" Proxy"]
1871pub struct _MTFEW<'a> {
1872 w: &'a mut W,
1873}
1874impl<'a> _MTFEW<'a> {
1875 #[doc = r" Writes `variant` to the field"]
1876 #[inline]
1877 pub fn variant(self, variant: MTFEW) -> &'a mut W {
1878 {
1879 self.bit(variant._bits())
1880 }
1881 }
1882 #[doc = "Modified SPI transfer format disabled."]
1883 #[inline]
1884 pub fn _0(self) -> &'a mut W {
1885 self.variant(MTFEW::_0)
1886 }
1887 #[doc = "Modified SPI transfer format enabled."]
1888 #[inline]
1889 pub fn _1(self) -> &'a mut W {
1890 self.variant(MTFEW::_1)
1891 }
1892 #[doc = r" Sets the field bit"]
1893 pub fn set_bit(self) -> &'a mut W {
1894 self.bit(true)
1895 }
1896 #[doc = r" Clears the field bit"]
1897 pub fn clear_bit(self) -> &'a mut W {
1898 self.bit(false)
1899 }
1900 #[doc = r" Writes raw bits to the field"]
1901 #[inline]
1902 pub fn bit(self, value: bool) -> &'a mut W {
1903 const MASK: bool = true;
1904 const OFFSET: u8 = 26;
1905 self.w.bits &= !((MASK as u32) << OFFSET);
1906 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1907 self.w
1908 }
1909}
1910#[doc = "Values that can be written to the field `FRZ`"]
1911pub enum FRZW {
1912 #[doc = "Do not halt serial transfers in Debug mode."]
1913 _0,
1914 #[doc = "Halt serial transfers in Debug mode."]
1915 _1,
1916}
1917impl FRZW {
1918 #[allow(missing_docs)]
1919 #[doc(hidden)]
1920 #[inline]
1921 pub fn _bits(&self) -> bool {
1922 match *self {
1923 FRZW::_0 => false,
1924 FRZW::_1 => true,
1925 }
1926 }
1927}
1928#[doc = r" Proxy"]
1929pub struct _FRZW<'a> {
1930 w: &'a mut W,
1931}
1932impl<'a> _FRZW<'a> {
1933 #[doc = r" Writes `variant` to the field"]
1934 #[inline]
1935 pub fn variant(self, variant: FRZW) -> &'a mut W {
1936 {
1937 self.bit(variant._bits())
1938 }
1939 }
1940 #[doc = "Do not halt serial transfers in Debug mode."]
1941 #[inline]
1942 pub fn _0(self) -> &'a mut W {
1943 self.variant(FRZW::_0)
1944 }
1945 #[doc = "Halt serial transfers in Debug mode."]
1946 #[inline]
1947 pub fn _1(self) -> &'a mut W {
1948 self.variant(FRZW::_1)
1949 }
1950 #[doc = r" Sets the field bit"]
1951 pub fn set_bit(self) -> &'a mut W {
1952 self.bit(true)
1953 }
1954 #[doc = r" Clears the field bit"]
1955 pub fn clear_bit(self) -> &'a mut W {
1956 self.bit(false)
1957 }
1958 #[doc = r" Writes raw bits to the field"]
1959 #[inline]
1960 pub fn bit(self, value: bool) -> &'a mut W {
1961 const MASK: bool = true;
1962 const OFFSET: u8 = 27;
1963 self.w.bits &= !((MASK as u32) << OFFSET);
1964 self.w.bits |= ((value & MASK) as u32) << OFFSET;
1965 self.w
1966 }
1967}
1968#[doc = "Values that can be written to the field `CONT_SCKE`"]
1969pub enum CONT_SCKEW {
1970 #[doc = "Continuous SCK disabled."]
1971 _0,
1972 #[doc = "Continuous SCK enabled."]
1973 _1,
1974}
1975impl CONT_SCKEW {
1976 #[allow(missing_docs)]
1977 #[doc(hidden)]
1978 #[inline]
1979 pub fn _bits(&self) -> bool {
1980 match *self {
1981 CONT_SCKEW::_0 => false,
1982 CONT_SCKEW::_1 => true,
1983 }
1984 }
1985}
1986#[doc = r" Proxy"]
1987pub struct _CONT_SCKEW<'a> {
1988 w: &'a mut W,
1989}
1990impl<'a> _CONT_SCKEW<'a> {
1991 #[doc = r" Writes `variant` to the field"]
1992 #[inline]
1993 pub fn variant(self, variant: CONT_SCKEW) -> &'a mut W {
1994 {
1995 self.bit(variant._bits())
1996 }
1997 }
1998 #[doc = "Continuous SCK disabled."]
1999 #[inline]
2000 pub fn _0(self) -> &'a mut W {
2001 self.variant(CONT_SCKEW::_0)
2002 }
2003 #[doc = "Continuous SCK enabled."]
2004 #[inline]
2005 pub fn _1(self) -> &'a mut W {
2006 self.variant(CONT_SCKEW::_1)
2007 }
2008 #[doc = r" Sets the field bit"]
2009 pub fn set_bit(self) -> &'a mut W {
2010 self.bit(true)
2011 }
2012 #[doc = r" Clears the field bit"]
2013 pub fn clear_bit(self) -> &'a mut W {
2014 self.bit(false)
2015 }
2016 #[doc = r" Writes raw bits to the field"]
2017 #[inline]
2018 pub fn bit(self, value: bool) -> &'a mut W {
2019 const MASK: bool = true;
2020 const OFFSET: u8 = 30;
2021 self.w.bits &= !((MASK as u32) << OFFSET);
2022 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2023 self.w
2024 }
2025}
2026#[doc = "Values that can be written to the field `MSTR`"]
2027pub enum MSTRW {
2028 #[doc = "Enables Slave mode"]
2029 _0,
2030 #[doc = "Enables Master mode"]
2031 _1,
2032}
2033impl MSTRW {
2034 #[allow(missing_docs)]
2035 #[doc(hidden)]
2036 #[inline]
2037 pub fn _bits(&self) -> bool {
2038 match *self {
2039 MSTRW::_0 => false,
2040 MSTRW::_1 => true,
2041 }
2042 }
2043}
2044#[doc = r" Proxy"]
2045pub struct _MSTRW<'a> {
2046 w: &'a mut W,
2047}
2048impl<'a> _MSTRW<'a> {
2049 #[doc = r" Writes `variant` to the field"]
2050 #[inline]
2051 pub fn variant(self, variant: MSTRW) -> &'a mut W {
2052 {
2053 self.bit(variant._bits())
2054 }
2055 }
2056 #[doc = "Enables Slave mode"]
2057 #[inline]
2058 pub fn _0(self) -> &'a mut W {
2059 self.variant(MSTRW::_0)
2060 }
2061 #[doc = "Enables Master mode"]
2062 #[inline]
2063 pub fn _1(self) -> &'a mut W {
2064 self.variant(MSTRW::_1)
2065 }
2066 #[doc = r" Sets the field bit"]
2067 pub fn set_bit(self) -> &'a mut W {
2068 self.bit(true)
2069 }
2070 #[doc = r" Clears the field bit"]
2071 pub fn clear_bit(self) -> &'a mut W {
2072 self.bit(false)
2073 }
2074 #[doc = r" Writes raw bits to the field"]
2075 #[inline]
2076 pub fn bit(self, value: bool) -> &'a mut W {
2077 const MASK: bool = true;
2078 const OFFSET: u8 = 31;
2079 self.w.bits &= !((MASK as u32) << OFFSET);
2080 self.w.bits |= ((value & MASK) as u32) << OFFSET;
2081 self.w
2082 }
2083}
2084impl R {
2085 #[doc = r" Value of the register as raw bits"]
2086 #[inline]
2087 pub fn bits(&self) -> u32 {
2088 self.bits
2089 }
2090 #[doc = "Bit 0 - Halt"]
2091 #[inline]
2092 pub fn halt(&self) -> HALTR {
2093 HALTR::_from({
2094 const MASK: bool = true;
2095 const OFFSET: u8 = 0;
2096 ((self.bits >> OFFSET) & MASK as u32) != 0
2097 })
2098 }
2099 #[doc = "Bits 8:9 - Sample Point"]
2100 #[inline]
2101 pub fn smpl_pt(&self) -> SMPL_PTR {
2102 SMPL_PTR::_from({
2103 const MASK: u8 = 3;
2104 const OFFSET: u8 = 8;
2105 ((self.bits >> OFFSET) & MASK as u32) as u8
2106 })
2107 }
2108 #[doc = "Bit 12 - Disable Receive FIFO"]
2109 #[inline]
2110 pub fn dis_rxf(&self) -> DIS_RXFR {
2111 DIS_RXFR::_from({
2112 const MASK: bool = true;
2113 const OFFSET: u8 = 12;
2114 ((self.bits >> OFFSET) & MASK as u32) != 0
2115 })
2116 }
2117 #[doc = "Bit 13 - Disable Transmit FIFO"]
2118 #[inline]
2119 pub fn dis_txf(&self) -> DIS_TXFR {
2120 DIS_TXFR::_from({
2121 const MASK: bool = true;
2122 const OFFSET: u8 = 13;
2123 ((self.bits >> OFFSET) & MASK as u32) != 0
2124 })
2125 }
2126 #[doc = "Bit 14 - Module Disable"]
2127 #[inline]
2128 pub fn mdis(&self) -> MDISR {
2129 MDISR::_from({
2130 const MASK: bool = true;
2131 const OFFSET: u8 = 14;
2132 ((self.bits >> OFFSET) & MASK as u32) != 0
2133 })
2134 }
2135 #[doc = "Bit 15 - Doze Enable"]
2136 #[inline]
2137 pub fn doze(&self) -> DOZER {
2138 DOZER::_from({
2139 const MASK: bool = true;
2140 const OFFSET: u8 = 15;
2141 ((self.bits >> OFFSET) & MASK as u32) != 0
2142 })
2143 }
2144 #[doc = "Bit 16 - Peripheral Chip Select x Inactive State"]
2145 #[inline]
2146 pub fn pcsis0(&self) -> PCSIS0R {
2147 PCSIS0R::_from({
2148 const MASK: bool = true;
2149 const OFFSET: u8 = 16;
2150 ((self.bits >> OFFSET) & MASK as u32) != 0
2151 })
2152 }
2153 #[doc = "Bit 17 - Peripheral Chip Select x Inactive State"]
2154 #[inline]
2155 pub fn pcsis1(&self) -> PCSIS1R {
2156 PCSIS1R::_from({
2157 const MASK: bool = true;
2158 const OFFSET: u8 = 17;
2159 ((self.bits >> OFFSET) & MASK as u32) != 0
2160 })
2161 }
2162 #[doc = "Bit 18 - Peripheral Chip Select x Inactive State"]
2163 #[inline]
2164 pub fn pcsis2(&self) -> PCSIS2R {
2165 PCSIS2R::_from({
2166 const MASK: bool = true;
2167 const OFFSET: u8 = 18;
2168 ((self.bits >> OFFSET) & MASK as u32) != 0
2169 })
2170 }
2171 #[doc = "Bit 19 - Peripheral Chip Select x Inactive State"]
2172 #[inline]
2173 pub fn pcsis3(&self) -> PCSIS3R {
2174 PCSIS3R::_from({
2175 const MASK: bool = true;
2176 const OFFSET: u8 = 19;
2177 ((self.bits >> OFFSET) & MASK as u32) != 0
2178 })
2179 }
2180 #[doc = "Bit 20 - Peripheral Chip Select x Inactive State"]
2181 #[inline]
2182 pub fn pcsis4(&self) -> PCSIS4R {
2183 PCSIS4R::_from({
2184 const MASK: bool = true;
2185 const OFFSET: u8 = 20;
2186 ((self.bits >> OFFSET) & MASK as u32) != 0
2187 })
2188 }
2189 #[doc = "Bit 21 - Peripheral Chip Select x Inactive State"]
2190 #[inline]
2191 pub fn pcsis5(&self) -> PCSIS5R {
2192 PCSIS5R::_from({
2193 const MASK: bool = true;
2194 const OFFSET: u8 = 21;
2195 ((self.bits >> OFFSET) & MASK as u32) != 0
2196 })
2197 }
2198 #[doc = "Bit 24 - Receive FIFO Overflow Overwrite Enable"]
2199 #[inline]
2200 pub fn rooe(&self) -> ROOER {
2201 ROOER::_from({
2202 const MASK: bool = true;
2203 const OFFSET: u8 = 24;
2204 ((self.bits >> OFFSET) & MASK as u32) != 0
2205 })
2206 }
2207 #[doc = "Bit 25 - Peripheral Chip Select Strobe Enable"]
2208 #[inline]
2209 pub fn pcsse(&self) -> PCSSER {
2210 PCSSER::_from({
2211 const MASK: bool = true;
2212 const OFFSET: u8 = 25;
2213 ((self.bits >> OFFSET) & MASK as u32) != 0
2214 })
2215 }
2216 #[doc = "Bit 26 - Modified Timing Format Enable"]
2217 #[inline]
2218 pub fn mtfe(&self) -> MTFER {
2219 MTFER::_from({
2220 const MASK: bool = true;
2221 const OFFSET: u8 = 26;
2222 ((self.bits >> OFFSET) & MASK as u32) != 0
2223 })
2224 }
2225 #[doc = "Bit 27 - Freeze"]
2226 #[inline]
2227 pub fn frz(&self) -> FRZR {
2228 FRZR::_from({
2229 const MASK: bool = true;
2230 const OFFSET: u8 = 27;
2231 ((self.bits >> OFFSET) & MASK as u32) != 0
2232 })
2233 }
2234 #[doc = "Bits 28:29 - SPI Configuration."]
2235 #[inline]
2236 pub fn dconf(&self) -> DCONFR {
2237 DCONFR::_from({
2238 const MASK: u8 = 3;
2239 const OFFSET: u8 = 28;
2240 ((self.bits >> OFFSET) & MASK as u32) as u8
2241 })
2242 }
2243 #[doc = "Bit 30 - Continuous SCK Enable"]
2244 #[inline]
2245 pub fn cont_scke(&self) -> CONT_SCKER {
2246 CONT_SCKER::_from({
2247 const MASK: bool = true;
2248 const OFFSET: u8 = 30;
2249 ((self.bits >> OFFSET) & MASK as u32) != 0
2250 })
2251 }
2252 #[doc = "Bit 31 - Master/Slave Mode Select"]
2253 #[inline]
2254 pub fn mstr(&self) -> MSTRR {
2255 MSTRR::_from({
2256 const MASK: bool = true;
2257 const OFFSET: u8 = 31;
2258 ((self.bits >> OFFSET) & MASK as u32) != 0
2259 })
2260 }
2261}
2262impl W {
2263 #[doc = r" Reset value of the register"]
2264 #[inline]
2265 pub fn reset_value() -> W {
2266 W { bits: 16385 }
2267 }
2268 #[doc = r" Writes raw bits to the register"]
2269 #[inline]
2270 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2271 self.bits = bits;
2272 self
2273 }
2274 #[doc = "Bit 0 - Halt"]
2275 #[inline]
2276 pub fn halt(&mut self) -> _HALTW {
2277 _HALTW { w: self }
2278 }
2279 #[doc = "Bits 8:9 - Sample Point"]
2280 #[inline]
2281 pub fn smpl_pt(&mut self) -> _SMPL_PTW {
2282 _SMPL_PTW { w: self }
2283 }
2284 #[doc = "Bit 10 - Flushes the RX FIFO"]
2285 #[inline]
2286 pub fn clr_rxf(&mut self) -> _CLR_RXFW {
2287 _CLR_RXFW { w: self }
2288 }
2289 #[doc = "Bit 11 - Clear TX FIFO"]
2290 #[inline]
2291 pub fn clr_txf(&mut self) -> _CLR_TXFW {
2292 _CLR_TXFW { w: self }
2293 }
2294 #[doc = "Bit 12 - Disable Receive FIFO"]
2295 #[inline]
2296 pub fn dis_rxf(&mut self) -> _DIS_RXFW {
2297 _DIS_RXFW { w: self }
2298 }
2299 #[doc = "Bit 13 - Disable Transmit FIFO"]
2300 #[inline]
2301 pub fn dis_txf(&mut self) -> _DIS_TXFW {
2302 _DIS_TXFW { w: self }
2303 }
2304 #[doc = "Bit 14 - Module Disable"]
2305 #[inline]
2306 pub fn mdis(&mut self) -> _MDISW {
2307 _MDISW { w: self }
2308 }
2309 #[doc = "Bit 15 - Doze Enable"]
2310 #[inline]
2311 pub fn doze(&mut self) -> _DOZEW {
2312 _DOZEW { w: self }
2313 }
2314 #[doc = "Bit 16 - Peripheral Chip Select x Inactive State"]
2315 #[inline]
2316 pub fn pcsis0(&mut self) -> _PCSIS0W {
2317 _PCSIS0W { w: self }
2318 }
2319 #[doc = "Bit 17 - Peripheral Chip Select x Inactive State"]
2320 #[inline]
2321 pub fn pcsis1(&mut self) -> _PCSIS1W {
2322 _PCSIS1W { w: self }
2323 }
2324 #[doc = "Bit 18 - Peripheral Chip Select x Inactive State"]
2325 #[inline]
2326 pub fn pcsis2(&mut self) -> _PCSIS2W {
2327 _PCSIS2W { w: self }
2328 }
2329 #[doc = "Bit 19 - Peripheral Chip Select x Inactive State"]
2330 #[inline]
2331 pub fn pcsis3(&mut self) -> _PCSIS3W {
2332 _PCSIS3W { w: self }
2333 }
2334 #[doc = "Bit 20 - Peripheral Chip Select x Inactive State"]
2335 #[inline]
2336 pub fn pcsis4(&mut self) -> _PCSIS4W {
2337 _PCSIS4W { w: self }
2338 }
2339 #[doc = "Bit 21 - Peripheral Chip Select x Inactive State"]
2340 #[inline]
2341 pub fn pcsis5(&mut self) -> _PCSIS5W {
2342 _PCSIS5W { w: self }
2343 }
2344 #[doc = "Bit 24 - Receive FIFO Overflow Overwrite Enable"]
2345 #[inline]
2346 pub fn rooe(&mut self) -> _ROOEW {
2347 _ROOEW { w: self }
2348 }
2349 #[doc = "Bit 25 - Peripheral Chip Select Strobe Enable"]
2350 #[inline]
2351 pub fn pcsse(&mut self) -> _PCSSEW {
2352 _PCSSEW { w: self }
2353 }
2354 #[doc = "Bit 26 - Modified Timing Format Enable"]
2355 #[inline]
2356 pub fn mtfe(&mut self) -> _MTFEW {
2357 _MTFEW { w: self }
2358 }
2359 #[doc = "Bit 27 - Freeze"]
2360 #[inline]
2361 pub fn frz(&mut self) -> _FRZW {
2362 _FRZW { w: self }
2363 }
2364 #[doc = "Bit 30 - Continuous SCK Enable"]
2365 #[inline]
2366 pub fn cont_scke(&mut self) -> _CONT_SCKEW {
2367 _CONT_SCKEW { w: self }
2368 }
2369 #[doc = "Bit 31 - Master/Slave Mode Select"]
2370 #[inline]
2371 pub fn mstr(&mut self) -> _MSTRW {
2372 _MSTRW { w: self }
2373 }
2374}