k510_pac/uart/
uart_rfw.rs

1#[doc = "Register `UART_RFW` writer"]
2pub struct W(crate::W<UART_RFW_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<UART_RFW_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<UART_RFW_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<UART_RFW_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Receive FIFO Framing Error\n\nValue on reset: 0"]
23#[derive(Clone, Copy, Debug, PartialEq)]
24pub enum RFFE_AW {
25    #[doc = "0: Receive FIFO framing error disabled"]
26    DISABLED = 0,
27    #[doc = "1: Receive FIFO framing error enabled"]
28    ENABLED = 1,
29}
30impl From<RFFE_AW> for bool {
31    #[inline(always)]
32    fn from(variant: RFFE_AW) -> Self {
33        variant as u8 != 0
34    }
35}
36#[doc = "Field `RFFE` writer - Receive FIFO Framing Error"]
37pub type RFFE_W<'a> = crate::BitWriter<'a, u32, UART_RFW_SPEC, RFFE_AW, 9>;
38impl<'a> RFFE_W<'a> {
39    #[doc = "Receive FIFO framing error disabled"]
40    #[inline(always)]
41    pub fn disabled(self) -> &'a mut W {
42        self.variant(RFFE_AW::DISABLED)
43    }
44    #[doc = "Receive FIFO framing error enabled"]
45    #[inline(always)]
46    pub fn enabled(self) -> &'a mut W {
47        self.variant(RFFE_AW::ENABLED)
48    }
49}
50#[doc = "Receive FIFO Parity Error\n\nValue on reset: 0"]
51#[derive(Clone, Copy, Debug, PartialEq)]
52pub enum RFPE_AW {
53    #[doc = "0: Receive FIFO parity error disabled"]
54    DISABLED = 0,
55    #[doc = "1: Receive FIFO parity error enabled"]
56    ENABLED = 1,
57}
58impl From<RFPE_AW> for bool {
59    #[inline(always)]
60    fn from(variant: RFPE_AW) -> Self {
61        variant as u8 != 0
62    }
63}
64#[doc = "Field `RFPE` writer - Receive FIFO Parity Error"]
65pub type RFPE_W<'a> = crate::BitWriter<'a, u32, UART_RFW_SPEC, RFPE_AW, 8>;
66impl<'a> RFPE_W<'a> {
67    #[doc = "Receive FIFO parity error disabled"]
68    #[inline(always)]
69    pub fn disabled(self) -> &'a mut W {
70        self.variant(RFPE_AW::DISABLED)
71    }
72    #[doc = "Receive FIFO parity error enabled"]
73    #[inline(always)]
74    pub fn enabled(self) -> &'a mut W {
75        self.variant(RFPE_AW::ENABLED)
76    }
77}
78#[doc = "Field `RFWD` writer - Receive FIFO Write Data"]
79pub type RFWD_W<'a> = crate::FieldWriter<'a, u32, UART_RFW_SPEC, u8, u8, 8, 0>;
80impl W {
81    #[doc = "Bit 9 - Receive FIFO Framing Error"]
82    #[inline(always)]
83    pub fn rffe(&mut self) -> RFFE_W {
84        RFFE_W::new(self)
85    }
86    #[doc = "Bit 8 - Receive FIFO Parity Error"]
87    #[inline(always)]
88    pub fn rfpe(&mut self) -> RFPE_W {
89        RFPE_W::new(self)
90    }
91    #[doc = "Bits 0:7 - Receive FIFO Write Data"]
92    #[inline(always)]
93    pub fn rfwd(&mut self) -> RFWD_W {
94        RFWD_W::new(self)
95    }
96    #[doc = "Writes raw bits to the register."]
97    #[inline(always)]
98    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
99        self.0.bits(bits);
100        self
101    }
102}
103#[doc = "Receive FIFO control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_rfw](index.html) module"]
104pub struct UART_RFW_SPEC;
105impl crate::RegisterSpec for UART_RFW_SPEC {
106    type Ux = u32;
107}
108#[doc = "`write(|w| ..)` method takes [uart_rfw::W](W) writer structure"]
109impl crate::Writable for UART_RFW_SPEC {
110    type Writer = W;
111}
112#[doc = "`reset()` method sets UART_RFW to value 0"]
113impl crate::Resettable for UART_RFW_SPEC {
114    #[inline(always)]
115    fn reset_value() -> Self::Ux {
116        0
117    }
118}
k510_pac/uart/uart_rfw.rs

k510_pac/uart/
uart_rfw.rs
