k510_pac/sysctl/
peri_sys_bus_clk_en.rs1#[doc = "Register `PERI_SYS_BUS_CLK_EN` reader"]
2pub struct R(crate::R<PERI_SYS_BUS_CLK_EN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PERI_SYS_BUS_CLK_EN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PERI_SYS_BUS_CLK_EN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PERI_SYS_BUS_CLK_EN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PERI_SYS_BUS_CLK_EN` writer"]
17pub struct W(crate::W<PERI_SYS_BUS_CLK_EN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PERI_SYS_BUS_CLK_EN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PERI_SYS_BUS_CLK_EN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PERI_SYS_BUS_CLK_EN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `WE_audif_pclk_en` writer - Write enable for bit 10 (audif_pclk_en)"]
38pub type WE_AUDIF_PCLK_EN_W<'a> = crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, bool, 26>;
39#[doc = "Fields `WE_spi_(0-3)_hclk_en` writer - Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
40pub type WE_SPI__HCLK_EN_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, bool, O>;
42#[doc = "Field `WE_i2s_2_pclk_en` writer - Write enable for bit 5 (i2s_2_pclk_en)"]
43pub type WE_I2S_2_PCLK_EN_W<'a> = crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, bool, 21>;
44#[doc = "Fields `WE_uart_(0-3)_pclk_en` writer - Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
45pub type WE_UART__PCLK_EN_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, bool, O>;
47#[doc = "Audio data interface slave APB port clock enable control\n\nValue on reset: 1"]
48#[derive(Clone, Copy, Debug, PartialEq)]
49pub enum AUDIF_HCLK_EN_A {
50 #[doc = "0: Disable AUD_IF slave APB port clock"]
51 DISABLE = 0,
52 #[doc = "1: Enable AUD_IF slave APB port clock"]
53 ENABLE = 1,
54}
55impl From<AUDIF_HCLK_EN_A> for bool {
56 #[inline(always)]
57 fn from(variant: AUDIF_HCLK_EN_A) -> Self {
58 variant as u8 != 0
59 }
60}
61#[doc = "Field `audif_hclk_en` reader - Audio data interface slave APB port clock enable control"]
62pub type AUDIF_HCLK_EN_R = crate::BitReader<AUDIF_HCLK_EN_A>;
63impl AUDIF_HCLK_EN_R {
64 #[doc = "Get enumerated values variant"]
65 #[inline(always)]
66 pub fn variant(&self) -> AUDIF_HCLK_EN_A {
67 match self.bits {
68 false => AUDIF_HCLK_EN_A::DISABLE,
69 true => AUDIF_HCLK_EN_A::ENABLE,
70 }
71 }
72 #[doc = "Checks if the value of the field is `DISABLE`"]
73 #[inline(always)]
74 pub fn is_disable(&self) -> bool {
75 *self == AUDIF_HCLK_EN_A::DISABLE
76 }
77 #[doc = "Checks if the value of the field is `ENABLE`"]
78 #[inline(always)]
79 pub fn is_enable(&self) -> bool {
80 *self == AUDIF_HCLK_EN_A::ENABLE
81 }
82}
83#[doc = "Field `audif_hclk_en` writer - Audio data interface slave APB port clock enable control"]
84pub type AUDIF_HCLK_EN_W<'a> =
85 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, AUDIF_HCLK_EN_A, 10>;
86impl<'a> AUDIF_HCLK_EN_W<'a> {
87 #[doc = "Disable AUD_IF slave APB port clock"]
88 #[inline(always)]
89 pub fn disable(self) -> &'a mut W {
90 self.variant(AUDIF_HCLK_EN_A::DISABLE)
91 }
92 #[doc = "Enable AUD_IF slave APB port clock"]
93 #[inline(always)]
94 pub fn enable(self) -> &'a mut W {
95 self.variant(AUDIF_HCLK_EN_A::ENABLE)
96 }
97}
98#[doc = "SPI host \\[i\\]
99slave AHB interface clock enable control\n\nValue on reset: 1"]
100#[derive(Clone, Copy, Debug, PartialEq)]
101pub enum SPI__HCLK_EN_A {
102 #[doc = "0: Disable SPI \\[i\\]
103slave AHB interface clock"]
104 DISABLE = 0,
105 #[doc = "1: Enable SPI \\[i\\]
106slave AHB interface clock"]
107 ENABLE = 1,
108}
109impl From<SPI__HCLK_EN_A> for bool {
110 #[inline(always)]
111 fn from(variant: SPI__HCLK_EN_A) -> Self {
112 variant as u8 != 0
113 }
114}
115#[doc = "Fields `spi_(0-3)_hclk_en` reader - SPI host \\[i\\]
116slave AHB interface clock enable control"]
117pub type SPI__HCLK_EN_R = crate::BitReader<SPI__HCLK_EN_A>;
118impl SPI__HCLK_EN_R {
119 #[doc = "Get enumerated values variant"]
120 #[inline(always)]
121 pub fn variant(&self) -> SPI__HCLK_EN_A {
122 match self.bits {
123 false => SPI__HCLK_EN_A::DISABLE,
124 true => SPI__HCLK_EN_A::ENABLE,
125 }
126 }
127 #[doc = "Checks if the value of the field is `DISABLE`"]
128 #[inline(always)]
129 pub fn is_disable(&self) -> bool {
130 *self == SPI__HCLK_EN_A::DISABLE
131 }
132 #[doc = "Checks if the value of the field is `ENABLE`"]
133 #[inline(always)]
134 pub fn is_enable(&self) -> bool {
135 *self == SPI__HCLK_EN_A::ENABLE
136 }
137}
138#[doc = "Fields `spi_(0-3)_hclk_en` writer - SPI host \\[i\\]
139slave AHB interface clock enable control"]
140pub type SPI__HCLK_EN_W<'a, const O: u8> =
141 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, SPI__HCLK_EN_A, O>;
142impl<'a, const O: u8> SPI__HCLK_EN_W<'a, O> {
143 #[doc = "Disable SPI \\[i\\]
144slave AHB interface clock"]
145 #[inline(always)]
146 pub fn disable(self) -> &'a mut W {
147 self.variant(SPI__HCLK_EN_A::DISABLE)
148 }
149 #[doc = "Enable SPI \\[i\\]
150slave AHB interface clock"]
151 #[inline(always)]
152 pub fn enable(self) -> &'a mut W {
153 self.variant(SPI__HCLK_EN_A::ENABLE)
154 }
155}
156#[doc = "I2S 2 slave APB interface clock enable control\n\nValue on reset: 1"]
157#[derive(Clone, Copy, Debug, PartialEq)]
158pub enum I2S_2_PCLK_EN_A {
159 #[doc = "0: Disable I2S 2 slave APB port clock"]
160 DISABLE = 0,
161 #[doc = "1: Enable I2S 2 slave APB port clock"]
162 ENABLE = 1,
163}
164impl From<I2S_2_PCLK_EN_A> for bool {
165 #[inline(always)]
166 fn from(variant: I2S_2_PCLK_EN_A) -> Self {
167 variant as u8 != 0
168 }
169}
170#[doc = "Field `i2s_2_pclk_en` reader - I2S 2 slave APB interface clock enable control"]
171pub type I2S_2_PCLK_EN_R = crate::BitReader<I2S_2_PCLK_EN_A>;
172impl I2S_2_PCLK_EN_R {
173 #[doc = "Get enumerated values variant"]
174 #[inline(always)]
175 pub fn variant(&self) -> I2S_2_PCLK_EN_A {
176 match self.bits {
177 false => I2S_2_PCLK_EN_A::DISABLE,
178 true => I2S_2_PCLK_EN_A::ENABLE,
179 }
180 }
181 #[doc = "Checks if the value of the field is `DISABLE`"]
182 #[inline(always)]
183 pub fn is_disable(&self) -> bool {
184 *self == I2S_2_PCLK_EN_A::DISABLE
185 }
186 #[doc = "Checks if the value of the field is `ENABLE`"]
187 #[inline(always)]
188 pub fn is_enable(&self) -> bool {
189 *self == I2S_2_PCLK_EN_A::ENABLE
190 }
191}
192#[doc = "Field `i2s_2_pclk_en` writer - I2S 2 slave APB interface clock enable control"]
193pub type I2S_2_PCLK_EN_W<'a> =
194 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, I2S_2_PCLK_EN_A, 5>;
195impl<'a> I2S_2_PCLK_EN_W<'a> {
196 #[doc = "Disable I2S 2 slave APB port clock"]
197 #[inline(always)]
198 pub fn disable(self) -> &'a mut W {
199 self.variant(I2S_2_PCLK_EN_A::DISABLE)
200 }
201 #[doc = "Enable I2S 2 slave APB port clock"]
202 #[inline(always)]
203 pub fn enable(self) -> &'a mut W {
204 self.variant(I2S_2_PCLK_EN_A::ENABLE)
205 }
206}
207#[doc = "UART host \\[i\\]
208slave APB interface clock enable control\n\nValue on reset: 1"]
209#[derive(Clone, Copy, Debug, PartialEq)]
210pub enum UART__PCLK_EN_A {
211 #[doc = "0: Disable UART \\[i\\]
212slave APB port clock"]
213 DISABLE = 0,
214 #[doc = "1: Enable UART \\[i\\]
215slave APB port clock"]
216 ENABLE = 1,
217}
218impl From<UART__PCLK_EN_A> for bool {
219 #[inline(always)]
220 fn from(variant: UART__PCLK_EN_A) -> Self {
221 variant as u8 != 0
222 }
223}
224#[doc = "Fields `uart_(0-3)_pclk_en` reader - UART host \\[i\\]
225slave APB interface clock enable control"]
226pub type UART__PCLK_EN_R = crate::BitReader<UART__PCLK_EN_A>;
227impl UART__PCLK_EN_R {
228 #[doc = "Get enumerated values variant"]
229 #[inline(always)]
230 pub fn variant(&self) -> UART__PCLK_EN_A {
231 match self.bits {
232 false => UART__PCLK_EN_A::DISABLE,
233 true => UART__PCLK_EN_A::ENABLE,
234 }
235 }
236 #[doc = "Checks if the value of the field is `DISABLE`"]
237 #[inline(always)]
238 pub fn is_disable(&self) -> bool {
239 *self == UART__PCLK_EN_A::DISABLE
240 }
241 #[doc = "Checks if the value of the field is `ENABLE`"]
242 #[inline(always)]
243 pub fn is_enable(&self) -> bool {
244 *self == UART__PCLK_EN_A::ENABLE
245 }
246}
247#[doc = "Fields `uart_(0-3)_pclk_en` writer - UART host \\[i\\]
248slave APB interface clock enable control"]
249pub type UART__PCLK_EN_W<'a, const O: u8> =
250 crate::BitWriter<'a, u32, PERI_SYS_BUS_CLK_EN_SPEC, UART__PCLK_EN_A, O>;
251impl<'a, const O: u8> UART__PCLK_EN_W<'a, O> {
252 #[doc = "Disable UART \\[i\\]
253slave APB port clock"]
254 #[inline(always)]
255 pub fn disable(self) -> &'a mut W {
256 self.variant(UART__PCLK_EN_A::DISABLE)
257 }
258 #[doc = "Enable UART \\[i\\]
259slave APB port clock"]
260 #[inline(always)]
261 pub fn enable(self) -> &'a mut W {
262 self.variant(UART__PCLK_EN_A::ENABLE)
263 }
264}
265impl R {
266 #[doc = "Bit 10 - Audio data interface slave APB port clock enable control"]
267 #[inline(always)]
268 pub fn audif_hclk_en(&self) -> AUDIF_HCLK_EN_R {
269 AUDIF_HCLK_EN_R::new(((self.bits >> 10) & 1) != 0)
270 }
271 #[doc = "SPI host \\[i\\]
272slave AHB interface clock enable control"]
273 #[inline(always)]
274 pub unsafe fn spi__hclk_en(&self, n: u8) -> SPI__HCLK_EN_R {
275 SPI__HCLK_EN_R::new(((self.bits >> (n + 6)) & 1) != 0)
276 }
277 #[doc = "Bit 6 - SPI host \\[i\\]
278slave AHB interface clock enable control"]
279 #[inline(always)]
280 pub fn spi_0_hclk_en(&self) -> SPI__HCLK_EN_R {
281 SPI__HCLK_EN_R::new(((self.bits >> 6) & 1) != 0)
282 }
283 #[doc = "Bit 7 - SPI host \\[i\\]
284slave AHB interface clock enable control"]
285 #[inline(always)]
286 pub fn spi_1_hclk_en(&self) -> SPI__HCLK_EN_R {
287 SPI__HCLK_EN_R::new(((self.bits >> 7) & 1) != 0)
288 }
289 #[doc = "Bit 8 - SPI host \\[i\\]
290slave AHB interface clock enable control"]
291 #[inline(always)]
292 pub fn spi_2_hclk_en(&self) -> SPI__HCLK_EN_R {
293 SPI__HCLK_EN_R::new(((self.bits >> 8) & 1) != 0)
294 }
295 #[doc = "Bit 9 - SPI host \\[i\\]
296slave AHB interface clock enable control"]
297 #[inline(always)]
298 pub fn spi_3_hclk_en(&self) -> SPI__HCLK_EN_R {
299 SPI__HCLK_EN_R::new(((self.bits >> 9) & 1) != 0)
300 }
301 #[doc = "Bit 5 - I2S 2 slave APB interface clock enable control"]
302 #[inline(always)]
303 pub fn i2s_2_pclk_en(&self) -> I2S_2_PCLK_EN_R {
304 I2S_2_PCLK_EN_R::new(((self.bits >> 5) & 1) != 0)
305 }
306 #[doc = "UART host \\[i\\]
307slave APB interface clock enable control"]
308 #[inline(always)]
309 pub unsafe fn uart__pclk_en(&self, n: u8) -> UART__PCLK_EN_R {
310 UART__PCLK_EN_R::new(((self.bits >> n) & 1) != 0)
311 }
312 #[doc = "Bit 0 - UART host \\[i\\]
313slave APB interface clock enable control"]
314 #[inline(always)]
315 pub fn uart_0_pclk_en(&self) -> UART__PCLK_EN_R {
316 UART__PCLK_EN_R::new((self.bits & 1) != 0)
317 }
318 #[doc = "Bit 1 - UART host \\[i\\]
319slave APB interface clock enable control"]
320 #[inline(always)]
321 pub fn uart_1_pclk_en(&self) -> UART__PCLK_EN_R {
322 UART__PCLK_EN_R::new(((self.bits >> 1) & 1) != 0)
323 }
324 #[doc = "Bit 2 - UART host \\[i\\]
325slave APB interface clock enable control"]
326 #[inline(always)]
327 pub fn uart_2_pclk_en(&self) -> UART__PCLK_EN_R {
328 UART__PCLK_EN_R::new(((self.bits >> 2) & 1) != 0)
329 }
330 #[doc = "Bit 3 - UART host \\[i\\]
331slave APB interface clock enable control"]
332 #[inline(always)]
333 pub fn uart_3_pclk_en(&self) -> UART__PCLK_EN_R {
334 UART__PCLK_EN_R::new(((self.bits >> 3) & 1) != 0)
335 }
336}
337impl W {
338 #[doc = "Bit 26 - Write enable for bit 10 (audif_pclk_en)"]
339 #[inline(always)]
340 pub fn we_audif_pclk_en(&mut self) -> WE_AUDIF_PCLK_EN_W {
341 WE_AUDIF_PCLK_EN_W::new(self)
342 }
343 #[doc = "Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
344 #[inline(always)]
345 pub unsafe fn we_spi__hclk_en<const O: u8>(&mut self) -> WE_SPI__HCLK_EN_W<O> {
346 WE_SPI__HCLK_EN_W::new(self)
347 }
348 #[doc = "Bit 22 - Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
349 #[inline(always)]
350 pub fn we_spi_0_hclk_en(&mut self) -> WE_SPI__HCLK_EN_W<22> {
351 WE_SPI__HCLK_EN_W::new(self)
352 }
353 #[doc = "Bit 23 - Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
354 #[inline(always)]
355 pub fn we_spi_1_hclk_en(&mut self) -> WE_SPI__HCLK_EN_W<23> {
356 WE_SPI__HCLK_EN_W::new(self)
357 }
358 #[doc = "Bit 24 - Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
359 #[inline(always)]
360 pub fn we_spi_2_hclk_en(&mut self) -> WE_SPI__HCLK_EN_W<24> {
361 WE_SPI__HCLK_EN_W::new(self)
362 }
363 #[doc = "Bit 25 - Write enable for bit 6-9 (spi_\\[0-3\\]_hclk_en)"]
364 #[inline(always)]
365 pub fn we_spi_3_hclk_en(&mut self) -> WE_SPI__HCLK_EN_W<25> {
366 WE_SPI__HCLK_EN_W::new(self)
367 }
368 #[doc = "Bit 21 - Write enable for bit 5 (i2s_2_pclk_en)"]
369 #[inline(always)]
370 pub fn we_i2s_2_pclk_en(&mut self) -> WE_I2S_2_PCLK_EN_W {
371 WE_I2S_2_PCLK_EN_W::new(self)
372 }
373 #[doc = "Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
374 #[inline(always)]
375 pub unsafe fn we_uart__pclk_en<const O: u8>(&mut self) -> WE_UART__PCLK_EN_W<O> {
376 WE_UART__PCLK_EN_W::new(self)
377 }
378 #[doc = "Bit 16 - Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
379 #[inline(always)]
380 pub fn we_uart_0_pclk_en(&mut self) -> WE_UART__PCLK_EN_W<16> {
381 WE_UART__PCLK_EN_W::new(self)
382 }
383 #[doc = "Bit 17 - Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
384 #[inline(always)]
385 pub fn we_uart_1_pclk_en(&mut self) -> WE_UART__PCLK_EN_W<17> {
386 WE_UART__PCLK_EN_W::new(self)
387 }
388 #[doc = "Bit 18 - Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
389 #[inline(always)]
390 pub fn we_uart_2_pclk_en(&mut self) -> WE_UART__PCLK_EN_W<18> {
391 WE_UART__PCLK_EN_W::new(self)
392 }
393 #[doc = "Bit 19 - Write enable for bit 0-3 (uart_\\[0-3\\]_pclk_en)"]
394 #[inline(always)]
395 pub fn we_uart_3_pclk_en(&mut self) -> WE_UART__PCLK_EN_W<19> {
396 WE_UART__PCLK_EN_W::new(self)
397 }
398 #[doc = "Bit 10 - Audio data interface slave APB port clock enable control"]
399 #[inline(always)]
400 pub fn audif_hclk_en(&mut self) -> AUDIF_HCLK_EN_W {
401 AUDIF_HCLK_EN_W::new(self)
402 }
403 #[doc = "SPI host \\[i\\]
404slave AHB interface clock enable control"]
405 #[inline(always)]
406 pub unsafe fn spi__hclk_en<const O: u8>(&mut self) -> SPI__HCLK_EN_W<O> {
407 SPI__HCLK_EN_W::new(self)
408 }
409 #[doc = "Bit 6 - SPI host \\[i\\]
410slave AHB interface clock enable control"]
411 #[inline(always)]
412 pub fn spi_0_hclk_en(&mut self) -> SPI__HCLK_EN_W<6> {
413 SPI__HCLK_EN_W::new(self)
414 }
415 #[doc = "Bit 7 - SPI host \\[i\\]
416slave AHB interface clock enable control"]
417 #[inline(always)]
418 pub fn spi_1_hclk_en(&mut self) -> SPI__HCLK_EN_W<7> {
419 SPI__HCLK_EN_W::new(self)
420 }
421 #[doc = "Bit 8 - SPI host \\[i\\]
422slave AHB interface clock enable control"]
423 #[inline(always)]
424 pub fn spi_2_hclk_en(&mut self) -> SPI__HCLK_EN_W<8> {
425 SPI__HCLK_EN_W::new(self)
426 }
427 #[doc = "Bit 9 - SPI host \\[i\\]
428slave AHB interface clock enable control"]
429 #[inline(always)]
430 pub fn spi_3_hclk_en(&mut self) -> SPI__HCLK_EN_W<9> {
431 SPI__HCLK_EN_W::new(self)
432 }
433 #[doc = "Bit 5 - I2S 2 slave APB interface clock enable control"]
434 #[inline(always)]
435 pub fn i2s_2_pclk_en(&mut self) -> I2S_2_PCLK_EN_W {
436 I2S_2_PCLK_EN_W::new(self)
437 }
438 #[doc = "UART host \\[i\\]
439slave APB interface clock enable control"]
440 #[inline(always)]
441 pub unsafe fn uart__pclk_en<const O: u8>(&mut self) -> UART__PCLK_EN_W<O> {
442 UART__PCLK_EN_W::new(self)
443 }
444 #[doc = "Bit 0 - UART host \\[i\\]
445slave APB interface clock enable control"]
446 #[inline(always)]
447 pub fn uart_0_pclk_en(&mut self) -> UART__PCLK_EN_W<0> {
448 UART__PCLK_EN_W::new(self)
449 }
450 #[doc = "Bit 1 - UART host \\[i\\]
451slave APB interface clock enable control"]
452 #[inline(always)]
453 pub fn uart_1_pclk_en(&mut self) -> UART__PCLK_EN_W<1> {
454 UART__PCLK_EN_W::new(self)
455 }
456 #[doc = "Bit 2 - UART host \\[i\\]
457slave APB interface clock enable control"]
458 #[inline(always)]
459 pub fn uart_2_pclk_en(&mut self) -> UART__PCLK_EN_W<2> {
460 UART__PCLK_EN_W::new(self)
461 }
462 #[doc = "Bit 3 - UART host \\[i\\]
463slave APB interface clock enable control"]
464 #[inline(always)]
465 pub fn uart_3_pclk_en(&mut self) -> UART__PCLK_EN_W<3> {
466 UART__PCLK_EN_W::new(self)
467 }
468 #[doc = "Writes raw bits to the register."]
469 #[inline(always)]
470 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
471 self.0.bits(bits);
472 self
473 }
474}
475#[doc = "Peripheral subsystem modules bus IF clock enable register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [peri_sys_bus_clk_en](index.html) module"]
476pub struct PERI_SYS_BUS_CLK_EN_SPEC;
477impl crate::RegisterSpec for PERI_SYS_BUS_CLK_EN_SPEC {
478 type Ux = u32;
479}
480#[doc = "`read()` method returns [peri_sys_bus_clk_en::R](R) reader structure"]
481impl crate::Readable for PERI_SYS_BUS_CLK_EN_SPEC {
482 type Reader = R;
483}
484#[doc = "`write(|w| ..)` method takes [peri_sys_bus_clk_en::W](W) writer structure"]
485impl crate::Writable for PERI_SYS_BUS_CLK_EN_SPEC {
486 type Writer = W;
487}
488#[doc = "`reset()` method sets PERI_SYS_BUS_CLK_EN to value 0x07ef"]
489impl crate::Resettable for PERI_SYS_BUS_CLK_EN_SPEC {
490 #[inline(always)]
491 fn reset_value() -> Self::Ux {
492 0x07ef
493 }
494}