Struct k22f::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _PACRA>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRB>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRC>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRD>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRE>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRF>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRG>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRH>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRI>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRJ>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRK>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRL>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRM>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRN>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRO>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRP>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRA>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRB>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRC>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRD>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor Protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write Protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted Protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor Protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted Protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRE>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRF>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRG>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRH>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRI>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRJ>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRK>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRL>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRM>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRN>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRO>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PACRP>>

pub fn tp7(&mut self) -> TP7_W

Bit 0 - Trusted Protect

pub fn wp7(&mut self) -> WP7_W

Bit 1 - Write Protect

pub fn sp7(&mut self) -> SP7_W

Bit 2 - Supervisor Protect

pub fn tp6(&mut self) -> TP6_W

Bit 4 - Trusted Protect

pub fn wp6(&mut self) -> WP6_W

Bit 5 - Write Protect

pub fn sp6(&mut self) -> SP6_W

Bit 6 - Supervisor Protect

pub fn tp5(&mut self) -> TP5_W

Bit 8 - Trusted Protect

pub fn wp5(&mut self) -> WP5_W

Bit 9 - Write Protect

pub fn sp5(&mut self) -> SP5_W

Bit 10 - Supervisor Protect

pub fn tp4(&mut self) -> TP4_W

Bit 12 - Trusted protect

pub fn wp4(&mut self) -> WP4_W

Bit 13 - Write Protect

pub fn sp4(&mut self) -> SP4_W

Bit 14 - Supervisor protect

pub fn tp3(&mut self) -> TP3_W

Bit 16 - Trusted Protect

pub fn wp3(&mut self) -> WP3_W

Bit 17 - Write protect

pub fn sp3(&mut self) -> SP3_W

Bit 18 - Supervisor Protect

pub fn tp2(&mut self) -> TP2_W

Bit 20 - Trusted protect

pub fn wp2(&mut self) -> WP2_W

Bit 21 - Write Protect

pub fn sp2(&mut self) -> SP2_W

Bit 22 - Supervisor protect

pub fn tp1(&mut self) -> TP1_W

Bit 24 - Trusted Protect

pub fn wp1(&mut self) -> WP1_W

Bit 25 - Write Protect

pub fn sp1(&mut self) -> SP1_W

Bit 26 - Supervisor Protect

pub fn tp0(&mut self) -> TP0_W

Bit 28 - Trusted protect

pub fn wp0(&mut self) -> WP0_W

Bit 29 - Write Protect

pub fn sp0(&mut self) -> SP0_W

Bit 30 - Supervisor Protect

impl W<u32, Reg<u32, _PRS>>

pub fn m0(&mut self) -> M0_W

Bits 0:2 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.

pub fn m1(&mut self) -> M1_W

Bits 4:6 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.

pub fn m2(&mut self) -> M2_W

Bits 8:10 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.

pub fn m4(&mut self) -> M4_W

Bits 16:18 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.

impl W<u32, Reg<u32, _CRS>>

pub fn park(&mut self) -> PARK_W

Bits 0:2 - Park

pub fn pctl(&mut self) -> PCTL_W

Bits 4:5 - Parking Control

pub fn arb(&mut self) -> ARB_W

Bits 8:9 - Arbitration Mode

pub fn hlp(&mut self) -> HLP_W

Bit 30 - Halt Low Priority

pub fn ro(&mut self) -> RO_W

Bit 31 - Read Only

impl W<u32, Reg<u32, _MGPCR0>>

pub fn aulb(&mut self) -> AULB_W

Bits 0:2 - Arbitrates On Undefined Length Bursts

impl W<u32, Reg<u32, _MGPCR1>>

pub fn aulb(&mut self) -> AULB_W

Bits 0:2 - Arbitrates On Undefined Length Bursts

impl W<u32, Reg<u32, _MGPCR2>>

pub fn aulb(&mut self) -> AULB_W

Bits 0:2 - Arbitrates On Undefined Length Bursts

impl W<u32, Reg<u32, _MGPCR4>>

pub fn aulb(&mut self) -> AULB_W

Bits 0:2 - Arbitrates On Undefined Length Bursts

impl W<u32, Reg<u32, _CR>>

pub fn edbg(&mut self) -> EDBG_W

Bit 1 - Enable Debug

pub fn erca(&mut self) -> ERCA_W

Bit 2 - Enable Round Robin Channel Arbitration

pub fn hoe(&mut self) -> HOE_W

Bit 4 - Halt On Error

pub fn halt(&mut self) -> HALT_W

Bit 5 - Halt DMA Operations

pub fn clm(&mut self) -> CLM_W

Bit 6 - Continuous Link Mode

pub fn emlm(&mut self) -> EMLM_W

Bit 7 - Enable Minor Loop Mapping

pub fn ecx(&mut self) -> ECX_W

Bit 16 - Error Cancel Transfer

pub fn cx(&mut self) -> CX_W

Bit 17 - Cancel Transfer

impl W<u32, Reg<u32, _ERQ>>

pub fn erq0(&mut self) -> ERQ0_W

Bit 0 - Enable DMA Request 0

pub fn erq1(&mut self) -> ERQ1_W

Bit 1 - Enable DMA Request 1

pub fn erq2(&mut self) -> ERQ2_W

Bit 2 - Enable DMA Request 2

pub fn erq3(&mut self) -> ERQ3_W

Bit 3 - Enable DMA Request 3

pub fn erq4(&mut self) -> ERQ4_W

Bit 4 - Enable DMA Request 4

pub fn erq5(&mut self) -> ERQ5_W

Bit 5 - Enable DMA Request 5

pub fn erq6(&mut self) -> ERQ6_W

Bit 6 - Enable DMA Request 6

pub fn erq7(&mut self) -> ERQ7_W

Bit 7 - Enable DMA Request 7

pub fn erq8(&mut self) -> ERQ8_W

Bit 8 - Enable DMA Request 8

pub fn erq9(&mut self) -> ERQ9_W

Bit 9 - Enable DMA Request 9

pub fn erq10(&mut self) -> ERQ10_W

Bit 10 - Enable DMA Request 10

pub fn erq11(&mut self) -> ERQ11_W

Bit 11 - Enable DMA Request 11

pub fn erq12(&mut self) -> ERQ12_W

Bit 12 - Enable DMA Request 12

pub fn erq13(&mut self) -> ERQ13_W

Bit 13 - Enable DMA Request 13

pub fn erq14(&mut self) -> ERQ14_W

Bit 14 - Enable DMA Request 14

pub fn erq15(&mut self) -> ERQ15_W

Bit 15 - Enable DMA Request 15

impl W<u32, Reg<u32, _EEI>>

pub fn eei0(&mut self) -> EEI0_W

Bit 0 - Enable Error Interrupt 0

pub fn eei1(&mut self) -> EEI1_W

Bit 1 - Enable Error Interrupt 1

pub fn eei2(&mut self) -> EEI2_W

Bit 2 - Enable Error Interrupt 2

pub fn eei3(&mut self) -> EEI3_W

Bit 3 - Enable Error Interrupt 3

pub fn eei4(&mut self) -> EEI4_W

Bit 4 - Enable Error Interrupt 4

pub fn eei5(&mut self) -> EEI5_W

Bit 5 - Enable Error Interrupt 5

pub fn eei6(&mut self) -> EEI6_W

Bit 6 - Enable Error Interrupt 6

pub fn eei7(&mut self) -> EEI7_W

Bit 7 - Enable Error Interrupt 7

pub fn eei8(&mut self) -> EEI8_W

Bit 8 - Enable Error Interrupt 8

pub fn eei9(&mut self) -> EEI9_W

Bit 9 - Enable Error Interrupt 9

pub fn eei10(&mut self) -> EEI10_W

Bit 10 - Enable Error Interrupt 10

pub fn eei11(&mut self) -> EEI11_W

Bit 11 - Enable Error Interrupt 11

pub fn eei12(&mut self) -> EEI12_W

Bit 12 - Enable Error Interrupt 12

pub fn eei13(&mut self) -> EEI13_W

Bit 13 - Enable Error Interrupt 13

pub fn eei14(&mut self) -> EEI14_W

Bit 14 - Enable Error Interrupt 14

pub fn eei15(&mut self) -> EEI15_W

Bit 15 - Enable Error Interrupt 15

impl W<u8, Reg<u8, _CEEI>>

pub fn ceei(&mut self) -> CEEI_W

Bits 0:3 - Clear Enable Error Interrupt

pub fn caee(&mut self) -> CAEE_W

Bit 6 - Clear All Enable Error Interrupts

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SEEI>>

pub fn seei(&mut self) -> SEEI_W

Bits 0:3 - Set Enable Error Interrupt

pub fn saee(&mut self) -> SAEE_W

Bit 6 - Sets All Enable Error Interrupts

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CERQ>>

pub fn cerq(&mut self) -> CERQ_W

Bits 0:3 - Clear Enable Request

pub fn caer(&mut self) -> CAER_W

Bit 6 - Clear All Enable Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SERQ>>

pub fn serq(&mut self) -> SERQ_W

Bits 0:3 - Set enable request

pub fn saer(&mut self) -> SAER_W

Bit 6 - Set All Enable Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CDNE>>

pub fn cdne(&mut self) -> CDNE_W

Bits 0:3 - Clear DONE Bit

pub fn cadn(&mut self) -> CADN_W

Bit 6 - Clears All DONE Bits

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _SSRT>>

pub fn ssrt(&mut self) -> SSRT_W

Bits 0:3 - Set START Bit

pub fn sast(&mut self) -> SAST_W

Bit 6 - Set All START Bits (activates all channels)

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CERR>>

pub fn cerr(&mut self) -> CERR_W

Bits 0:3 - Clear Error Indicator

pub fn caei(&mut self) -> CAEI_W

Bit 6 - Clear All Error Indicators

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u8, Reg<u8, _CINT>>

pub fn cint(&mut self) -> CINT_W

Bits 0:3 - Clear Interrupt Request

pub fn cair(&mut self) -> CAIR_W

Bit 6 - Clear All Interrupt Requests

pub fn nop(&mut self) -> NOP_W

Bit 7 - No Op enable

impl W<u32, Reg<u32, _INT>>

pub fn int0(&mut self) -> INT0_W

Bit 0 - Interrupt Request 0

pub fn int1(&mut self) -> INT1_W

Bit 1 - Interrupt Request 1

pub fn int2(&mut self) -> INT2_W

Bit 2 - Interrupt Request 2

pub fn int3(&mut self) -> INT3_W

Bit 3 - Interrupt Request 3

pub fn int4(&mut self) -> INT4_W

Bit 4 - Interrupt Request 4

pub fn int5(&mut self) -> INT5_W

Bit 5 - Interrupt Request 5

pub fn int6(&mut self) -> INT6_W

Bit 6 - Interrupt Request 6

pub fn int7(&mut self) -> INT7_W

Bit 7 - Interrupt Request 7

pub fn int8(&mut self) -> INT8_W

Bit 8 - Interrupt Request 8

pub fn int9(&mut self) -> INT9_W

Bit 9 - Interrupt Request 9

pub fn int10(&mut self) -> INT10_W

Bit 10 - Interrupt Request 10

pub fn int11(&mut self) -> INT11_W

Bit 11 - Interrupt Request 11

pub fn int12(&mut self) -> INT12_W

Bit 12 - Interrupt Request 12

pub fn int13(&mut self) -> INT13_W

Bit 13 - Interrupt Request 13

pub fn int14(&mut self) -> INT14_W

Bit 14 - Interrupt Request 14

pub fn int15(&mut self) -> INT15_W

Bit 15 - Interrupt Request 15

impl W<u32, Reg<u32, _ERR>>

pub fn err0(&mut self) -> ERR0_W

Bit 0 - Error In Channel 0

pub fn err1(&mut self) -> ERR1_W

Bit 1 - Error In Channel 1

pub fn err2(&mut self) -> ERR2_W

Bit 2 - Error In Channel 2

pub fn err3(&mut self) -> ERR3_W

Bit 3 - Error In Channel 3

pub fn err4(&mut self) -> ERR4_W

Bit 4 - Error In Channel 4

pub fn err5(&mut self) -> ERR5_W

Bit 5 - Error In Channel 5

pub fn err6(&mut self) -> ERR6_W

Bit 6 - Error In Channel 6

pub fn err7(&mut self) -> ERR7_W

Bit 7 - Error In Channel 7

pub fn err8(&mut self) -> ERR8_W

Bit 8 - Error In Channel 8

pub fn err9(&mut self) -> ERR9_W

Bit 9 - Error In Channel 9

pub fn err10(&mut self) -> ERR10_W

Bit 10 - Error In Channel 10

pub fn err11(&mut self) -> ERR11_W

Bit 11 - Error In Channel 11

pub fn err12(&mut self) -> ERR12_W

Bit 12 - Error In Channel 12

pub fn err13(&mut self) -> ERR13_W

Bit 13 - Error In Channel 13

pub fn err14(&mut self) -> ERR14_W

Bit 14 - Error In Channel 14

pub fn err15(&mut self) -> ERR15_W

Bit 15 - Error In Channel 15

impl W<u32, Reg<u32, _HRS>>

pub fn hrs0(&mut self) -> HRS0_W

Bit 0 - Hardware Request Status Channel 0

pub fn hrs1(&mut self) -> HRS1_W

Bit 1 - Hardware Request Status Channel 1

pub fn hrs2(&mut self) -> HRS2_W

Bit 2 - Hardware Request Status Channel 2

pub fn hrs3(&mut self) -> HRS3_W

Bit 3 - Hardware Request Status Channel 3

pub fn hrs4(&mut self) -> HRS4_W

Bit 4 - Hardware Request Status Channel 4

pub fn hrs5(&mut self) -> HRS5_W

Bit 5 - Hardware Request Status Channel 5

pub fn hrs6(&mut self) -> HRS6_W

Bit 6 - Hardware Request Status Channel 6

pub fn hrs7(&mut self) -> HRS7_W

Bit 7 - Hardware Request Status Channel 7

pub fn hrs8(&mut self) -> HRS8_W

Bit 8 - Hardware Request Status Channel 8

pub fn hrs9(&mut self) -> HRS9_W

Bit 9 - Hardware Request Status Channel 9

pub fn hrs10(&mut self) -> HRS10_W

Bit 10 - Hardware Request Status Channel 10

pub fn hrs11(&mut self) -> HRS11_W

Bit 11 - Hardware Request Status Channel 11

pub fn hrs12(&mut self) -> HRS12_W

Bit 12 - Hardware Request Status Channel 12

pub fn hrs13(&mut self) -> HRS13_W

Bit 13 - Hardware Request Status Channel 13

pub fn hrs14(&mut self) -> HRS14_W

Bit 14 - Hardware Request Status Channel 14

pub fn hrs15(&mut self) -> HRS15_W

Bit 15 - Hardware Request Status Channel 15

impl W<u32, Reg<u32, _EARS>>

pub fn edreq_0(&mut self) -> EDREQ_0_W

Bit 0 - Enable asynchronous DMA request in stop for channel 0.

pub fn edreq_1(&mut self) -> EDREQ_1_W

Bit 1 - Enable asynchronous DMA request in stop for channel 1.

pub fn edreq_2(&mut self) -> EDREQ_2_W

Bit 2 - Enable asynchronous DMA request in stop for channel 2.

pub fn edreq_3(&mut self) -> EDREQ_3_W

Bit 3 - Enable asynchronous DMA request in stop for channel 3.

impl W<u8, Reg<u8, _DCHPRI>>

pub fn chpri(&mut self) -> CHPRI_W

Bits 0:3 - Channel n Arbitration Priority

pub fn dpa(&mut self) -> DPA_W

Bit 6 - Disable Preempt Ability

pub fn ecp(&mut self) -> ECP_W

Bit 7 - Enable Channel Preemption

impl W<u32, Reg<u32, _TCD_SADDR>>

pub fn saddr(&mut self) -> SADDR_W

Bits 0:31 - Source Address

impl W<u16, Reg<u16, _TCD_SOFF>>

pub fn soff(&mut self) -> SOFF_W

Bits 0:15 - Source address signed offset

impl W<u16, Reg<u16, _TCD_ATTR>>

pub fn dsize(&mut self) -> DSIZE_W

Bits 0:2 - Destination Data Transfer Size

pub fn dmod(&mut self) -> DMOD_W

Bits 3:7 - Destination Address Modulo

pub fn ssize(&mut self) -> SSIZE_W

Bits 8:10 - Source data transfer size

pub fn smod(&mut self) -> SMOD_W

Bits 11:15 - Source Address Modulo.

impl W<u32, Reg<u32, _TCD_NBYTES_MLNO>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:31 - Minor Byte Transfer Count

impl W<u32, Reg<u32, _TCD_NBYTES_MLOFFNO>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:29 - Minor Byte Transfer Count

pub fn dmloe(&mut self) -> DMLOE_W

Bit 30 - Destination Minor Loop Offset enable

pub fn smloe(&mut self) -> SMLOE_W

Bit 31 - Source Minor Loop Offset Enable

impl W<u32, Reg<u32, _TCD_NBYTES_MLOFFYES>>

pub fn nbytes(&mut self) -> NBYTES_W

Bits 0:9 - Minor Byte Transfer Count

pub fn mloff(&mut self) -> MLOFF_W

Bits 10:29 - If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.

pub fn dmloe(&mut self) -> DMLOE_W

Bit 30 - Destination Minor Loop Offset enable

pub fn smloe(&mut self) -> SMLOE_W

Bit 31 - Source Minor Loop Offset Enable

impl W<u32, Reg<u32, _TCD_SLAST>>

pub fn slast(&mut self) -> SLAST_W

Bits 0:31 - Last source Address Adjustment

impl W<u32, Reg<u32, _TCD_DADDR>>

pub fn daddr(&mut self) -> DADDR_W

Bits 0:31 - Destination Address

impl W<u16, Reg<u16, _TCD_DOFF>>

pub fn doff(&mut self) -> DOFF_W

Bits 0:15 - Destination Address Signed offset

impl W<u16, Reg<u16, _TCD_CITER_ELINKNO>>

pub fn citer(&mut self) -> CITER_W

Bits 0:14 - Current Major Iteration Count

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enable channel-to-channel linking on minor-loop complete

impl W<u16, Reg<u16, _TCD_CITER_ELINKYES>>

pub fn citer(&mut self) -> CITER_W

Bits 0:8 - Current Major Iteration Count

pub fn linkch(&mut self) -> LINKCH_W

Bits 9:12 - Link Channel Number

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enable channel-to-channel linking on minor-loop complete

impl W<u32, Reg<u32, _TCD_DLASTSGA>>

pub fn dlastsga(&mut self) -> DLASTSGA_W

Bits 0:31 - Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)

impl W<u16, Reg<u16, _TCD_CSR>>

pub fn start(&mut self) -> START_W

Bit 0 - Channel Start

pub fn intmajor(&mut self) -> INTMAJOR_W

Bit 1 - Enable an interrupt when major iteration count completes

pub fn inthalf(&mut self) -> INTHALF_W

Bit 2 - Enable an interrupt when major counter is half complete.

pub fn dreq(&mut self) -> DREQ_W

Bit 3 - Disable Request

pub fn esg(&mut self) -> ESG_W

Bit 4 - Enable Scatter/Gather Processing

pub fn majorelink(&mut self) -> MAJORELINK_W

Bit 5 - Enable channel-to-channel linking on major loop complete

pub fn active(&mut self) -> ACTIVE_W

Bit 6 - Channel Active

pub fn done(&mut self) -> DONE_W

Bit 7 - Channel Done

pub fn majorlinkch(&mut self) -> MAJORLINKCH_W

Bits 8:11 - Link Channel Number

pub fn bwc(&mut self) -> BWC_W

Bits 14:15 - Bandwidth Control

impl W<u16, Reg<u16, _TCD_BITER_ELINKNO>>

pub fn biter(&mut self) -> BITER_W

Bits 0:14 - Starting Major Iteration Count

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enables channel-to-channel linking on minor loop complete

impl W<u16, Reg<u16, _TCD_BITER_ELINKYES>>

pub fn biter(&mut self) -> BITER_W

Bits 0:8 - Starting Major Iteration Count

pub fn linkch(&mut self) -> LINKCH_W

Bits 9:12 - Link Channel Number

pub fn elink(&mut self) -> ELINK_W

Bit 15 - Enables channel-to-channel linking on minor loop complete

impl W<u32, Reg<u32, _CSAR>>

pub fn ba(&mut self) -> BA_W

Bits 16:31 - Base Address

impl W<u32, Reg<u32, _CSMR>>

pub fn v(&mut self) -> V_W

Bit 0 - Valid

pub fn wp(&mut self) -> WP_W

Bit 8 - Write Protect

pub fn bam(&mut self) -> BAM_W

Bits 16:31 - Base Address Mask

impl W<u32, Reg<u32, _CSCR>>

pub fn bstw(&mut self) -> BSTW_W

Bit 3 - Burst-Write Enable

pub fn bstr(&mut self) -> BSTR_W

Bit 4 - Burst-Read Enable

pub fn bem(&mut self) -> BEM_W

Bit 5 - Byte-Enable Mode

pub fn ps(&mut self) -> PS_W

Bits 6:7 - Port Size

pub fn aa(&mut self) -> AA_W

Bit 8 - Auto-Acknowledge Enable

pub fn bls(&mut self) -> BLS_W

Bit 9 - Byte-Lane Shift

pub fn ws(&mut self) -> WS_W

Bits 10:15 - Wait States

pub fn wrah(&mut self) -> WRAH_W

Bits 16:17 - Write Address Hold or Deselect

pub fn rdah(&mut self) -> RDAH_W

Bits 18:19 - Read Address Hold or Deselect

pub fn aset(&mut self) -> ASET_W

Bits 20:21 - Address Setup

pub fn exts(&mut self) -> EXTS_W

Bit 22 - Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS /FB_ALE is asserted.

pub fn swsen(&mut self) -> SWSEN_W

Bit 23 - Secondary Wait State Enable

pub fn sws(&mut self) -> SWS_W

Bits 26:31 - Secondary Wait States

impl W<u32, Reg<u32, _CSPMCR>>

pub fn group5(&mut self) -> GROUP5_W

Bits 12:15 - FlexBus Signal Group 5 Multiplex control

pub fn group4(&mut self) -> GROUP4_W

Bits 16:19 - FlexBus Signal Group 4 Multiplex control

pub fn group3(&mut self) -> GROUP3_W

Bits 20:23 - FlexBus Signal Group 3 Multiplex control

pub fn group2(&mut self) -> GROUP2_W

Bits 24:27 - FlexBus Signal Group 2 Multiplex control

pub fn group1(&mut self) -> GROUP1_W

Bits 28:31 - FlexBus Signal Group 1 Multiplex control

impl W<u32, Reg<u32, _CESR>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn sperr(&mut self) -> SPERR_W

Bits 27:31 - Slave Port n Error

impl W<u32, Reg<u32, _RGD_WORD0>>

pub fn srtaddr(&mut self) -> SRTADDR_W

Bits 5:31 - Start Address

impl W<u32, Reg<u32, _RGD_WORD1>>

pub fn endaddr(&mut self) -> ENDADDR_W

Bits 5:31 - End Address

impl W<u32, Reg<u32, _RGD_WORD2>>

pub fn m0um(&mut self) -> M0UM_W

Bits 0:2 - Bus Master 0 User Mode Access Control

pub fn m0sm(&mut self) -> M0SM_W

Bits 3:4 - Bus Master 0 Supervisor Mode Access Control

pub fn m0pe(&mut self) -> M0PE_W

Bit 5 - Bus Master 0 Process Identifier enable

pub fn m1um(&mut self) -> M1UM_W

Bits 6:8 - Bus Master 1 User Mode Access Control

pub fn m1sm(&mut self) -> M1SM_W

Bits 9:10 - Bus Master 1 Supervisor Mode Access Control

pub fn m1pe(&mut self) -> M1PE_W

Bit 11 - Bus Master 1 Process Identifier enable

pub fn m2um(&mut self) -> M2UM_W

Bits 12:14 - Bus Master 2 User Mode Access control

pub fn m2sm(&mut self) -> M2SM_W

Bits 15:16 - Bus Master 2 Supervisor Mode Access Control

pub fn m2pe(&mut self) -> M2PE_W

Bit 17 - Bus Master 2 Process Identifier Enable

pub fn m3um(&mut self) -> M3UM_W

Bits 18:20 - Bus Master 3 User Mode Access Control

pub fn m3sm(&mut self) -> M3SM_W

Bits 21:22 - Bus Master 3 Supervisor Mode Access Control

pub fn m3pe(&mut self) -> M3PE_W

Bit 23 - Bus Master 3 Process Identifier Enable

pub fn m4we(&mut self) -> M4WE_W

Bit 24 - Bus Master 4 Write Enable

pub fn m4re(&mut self) -> M4RE_W

Bit 25 - Bus Master 4 Read Enable

pub fn m5we(&mut self) -> M5WE_W

Bit 26 - Bus Master 5 Write Enable

pub fn m5re(&mut self) -> M5RE_W

Bit 27 - Bus Master 5 Read Enable

pub fn m6we(&mut self) -> M6WE_W

Bit 28 - Bus Master 6 Write Enable

pub fn m6re(&mut self) -> M6RE_W

Bit 29 - Bus Master 6 Read Enable

pub fn m7we(&mut self) -> M7WE_W

Bit 30 - Bus Master 7 Write Enable

pub fn m7re(&mut self) -> M7RE_W

Bit 31 - Bus Master 7 Read Enable

impl W<u32, Reg<u32, _RGD_WORD3>>

pub fn vld(&mut self) -> VLD_W

Bit 0 - Valid

pub fn pidmask(&mut self) -> PIDMASK_W

Bits 16:23 - Process Identifier Mask

pub fn pid(&mut self) -> PID_W

Bits 24:31 - Process Identifier

impl W<u32, Reg<u32, _RGDAAC>>

pub fn m0um(&mut self) -> M0UM_W

Bits 0:2 - Bus Master 0 User Mode Access Control

pub fn m0sm(&mut self) -> M0SM_W

Bits 3:4 - Bus Master 0 Supervisor Mode Access Control

pub fn m0pe(&mut self) -> M0PE_W

Bit 5 - Bus Master 0 Process Identifier Enable

pub fn m1um(&mut self) -> M1UM_W

Bits 6:8 - Bus Master 1 User Mode Access Control

pub fn m1sm(&mut self) -> M1SM_W

Bits 9:10 - Bus Master 1 Supervisor Mode Access Control

pub fn m1pe(&mut self) -> M1PE_W

Bit 11 - Bus Master 1 Process Identifier Enable

pub fn m2um(&mut self) -> M2UM_W

Bits 12:14 - Bus Master 2 User Mode Access Control

pub fn m2sm(&mut self) -> M2SM_W

Bits 15:16 - Bus Master 2 Supervisor Mode Access Control

pub fn m2pe(&mut self) -> M2PE_W

Bit 17 - Bus Master 2 Process Identifier Enable

pub fn m3um(&mut self) -> M3UM_W

Bits 18:20 - Bus Master 3 User Mode Access Control

pub fn m3sm(&mut self) -> M3SM_W

Bits 21:22 - Bus Master 3 Supervisor Mode Access Control

pub fn m3pe(&mut self) -> M3PE_W

Bit 23 - Bus Master 3 Process Identifier Enable

pub fn m4we(&mut self) -> M4WE_W

Bit 24 - Bus Master 4 Write Enable

pub fn m4re(&mut self) -> M4RE_W

Bit 25 - Bus Master 4 Read Enable

pub fn m5we(&mut self) -> M5WE_W

Bit 26 - Bus Master 5 Write Enable

pub fn m5re(&mut self) -> M5RE_W

Bit 27 - Bus Master 5 Read Enable

pub fn m6we(&mut self) -> M6WE_W

Bit 28 - Bus Master 6 Write Enable

pub fn m6re(&mut self) -> M6RE_W

Bit 29 - Bus Master 6 Read Enable

pub fn m7we(&mut self) -> M7WE_W

Bit 30 - Bus Master 7 Write Enable

pub fn m7re(&mut self) -> M7RE_W

Bit 31 - Bus Master 7 Read Enable

impl W<u32, Reg<u32, _PFAPR>>

pub fn m0ap(&mut self) -> M0AP_W

Bits 0:1 - Master 0 Access Protection

pub fn m1ap(&mut self) -> M1AP_W

Bits 2:3 - Master 1 Access Protection

pub fn m2ap(&mut self) -> M2AP_W

Bits 4:5 - Master 2 Access Protection

pub fn m3ap(&mut self) -> M3AP_W

Bits 6:7 - Master 3 Access Protection

pub fn m4ap(&mut self) -> M4AP_W

Bits 8:9 - Master 4 Access Protection

pub fn m5ap(&mut self) -> M5AP_W

Bits 10:11 - Master 5 Access Protection

pub fn m6ap(&mut self) -> M6AP_W

Bits 12:13 - Master 6 Access Protection

pub fn m7ap(&mut self) -> M7AP_W

Bits 14:15 - Master 7 Access Protection

pub fn m0pfd(&mut self) -> M0PFD_W

Bit 16 - Master 0 Prefetch Disable

pub fn m1pfd(&mut self) -> M1PFD_W

Bit 17 - Master 1 Prefetch Disable

pub fn m2pfd(&mut self) -> M2PFD_W

Bit 18 - Master 2 Prefetch Disable

pub fn m3pfd(&mut self) -> M3PFD_W

Bit 19 - Master 3 Prefetch Disable

pub fn m4pfd(&mut self) -> M4PFD_W

Bit 20 - Master 4 Prefetch Disable

pub fn m5pfd(&mut self) -> M5PFD_W

Bit 21 - Master 5 Prefetch Disable

pub fn m6pfd(&mut self) -> M6PFD_W

Bit 22 - Master 6 Prefetch Disable

pub fn m7pfd(&mut self) -> M7PFD_W

Bit 23 - Master 7 Prefetch Disable

impl W<u32, Reg<u32, _PFB0CR>>

pub fn b0sebe(&mut self) -> B0SEBE_W

Bit 0 - Bank 0 Single Entry Buffer Enable

pub fn b0ipe(&mut self) -> B0IPE_W

Bit 1 - Bank 0 Instruction Prefetch Enable

pub fn b0dpe(&mut self) -> B0DPE_W

Bit 2 - Bank 0 Data Prefetch Enable

pub fn b0ice(&mut self) -> B0ICE_W

Bit 3 - Bank 0 Instruction Cache Enable

pub fn b0dce(&mut self) -> B0DCE_W

Bit 4 - Bank 0 Data Cache Enable

pub fn crc(&mut self) -> CRC_W

Bits 5:7 - Cache Replacement Control

pub fn s_b_inv(&mut self) -> S_B_INV_W

Bit 19 - Invalidate Prefetch Speculation Buffer

pub fn cinv_way(&mut self) -> CINV_WAY_W

Bits 20:23 - Cache Invalidate Way x

pub fn clck_way(&mut self) -> CLCK_WAY_W

Bits 24:27 - Cache Lock Way x

impl W<u32, Reg<u32, _PFB1CR>>

pub fn b1sebe(&mut self) -> B1SEBE_W

Bit 0 - Bank 1 Single Entry Buffer Enable

pub fn b1ipe(&mut self) -> B1IPE_W

Bit 1 - Bank 1 Instruction Prefetch Enable

pub fn b1dpe(&mut self) -> B1DPE_W

Bit 2 - Bank 1 Data Prefetch Enable

pub fn b1ice(&mut self) -> B1ICE_W

Bit 3 - Bank 1 Instruction Cache Enable

pub fn b1dce(&mut self) -> B1DCE_W

Bit 4 - Bank 1 Data Cache Enable

impl W<u32, Reg<u32, _TAGVDW0S>>

pub fn valid(&mut self) -> VALID_W

Bit 0 - 1-bit valid for cache entry

pub fn tag(&mut self) -> TAG_W

Bits 6:19 - 14-bit tag for cache entry

impl W<u32, Reg<u32, _TAGVDW1S>>

pub fn valid(&mut self) -> VALID_W

Bit 0 - 1-bit valid for cache entry

pub fn tag(&mut self) -> TAG_W

Bits 6:19 - 14-bit tag for cache entry

impl W<u32, Reg<u32, _TAGVDW2S>>

pub fn valid(&mut self) -> VALID_W

Bit 0 - 1-bit valid for cache entry

pub fn tag(&mut self) -> TAG_W

Bits 6:19 - 14-bit tag for cache entry

impl W<u32, Reg<u32, _TAGVDW3S>>

pub fn valid(&mut self) -> VALID_W

Bit 0 - 1-bit valid for cache entry

pub fn tag(&mut self) -> TAG_W

Bits 6:19 - 14-bit tag for cache entry

impl W<u32, Reg<u32, _DATAW0SUM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [127:96] of data entry

impl W<u32, Reg<u32, _DATAW0SMU>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [95:64] of data entry

impl W<u32, Reg<u32, _DATAW0SML>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [63:32] of data entry

impl W<u32, Reg<u32, _DATAW0SLM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [31:0] of data entry

impl W<u32, Reg<u32, _DATAW1SUM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [127:96] of data entry

impl W<u32, Reg<u32, _DATAW1SMU>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [95:64] of data entry

impl W<u32, Reg<u32, _DATAW1SML>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [63:32] of data entry

impl W<u32, Reg<u32, _DATAW1SLM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [31:0] of data entry

impl W<u32, Reg<u32, _DATAW2SUM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [127:96] of data entry

impl W<u32, Reg<u32, _DATAW2SMU>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [95:64] of data entry

impl W<u32, Reg<u32, _DATAW2SML>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [63:32] of data entry

impl W<u32, Reg<u32, _DATAW2SLM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [31:0] of data entry

impl W<u32, Reg<u32, _DATAW3SUM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [127:96] of data entry

impl W<u32, Reg<u32, _DATAW3SMU>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [95:64] of data entry

impl W<u32, Reg<u32, _DATAW3SML>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [63:32] of data entry

impl W<u32, Reg<u32, _DATAW3SLM>>

pub fn data(&mut self) -> DATA_W

Bits 0:31 - Bits [31:0] of data entry

impl W<u8, Reg<u8, _FSTAT>>

pub fn fpviol(&mut self) -> FPVIOL_W

Bit 4 - Flash Protection Violation Flag

pub fn accerr(&mut self) -> ACCERR_W

Bit 5 - Flash Access Error Flag

pub fn rdcolerr(&mut self) -> RDCOLERR_W

Bit 6 - FTFE Read Collision Error Flag

pub fn ccif(&mut self) -> CCIF_W

Bit 7 - Command Complete Interrupt Flag

impl W<u8, Reg<u8, _FCNFG>>

pub fn erssusp(&mut self) -> ERSSUSP_W

Bit 4 - Erase Suspend

pub fn rdcollie(&mut self) -> RDCOLLIE_W

Bit 6 - Read Collision Error Interrupt Enable

pub fn ccie(&mut self) -> CCIE_W

Bit 7 - Command Complete Interrupt Enable

impl W<u8, Reg<u8, _FCCOB>>

pub fn ccobn(&mut self) -> CCOBN_W

Bits 0:7 - The FCCOB register provides a command code and relevant parameters to the memory controller

impl W<u8, Reg<u8, _FPROT>>

pub fn prot(&mut self) -> PROT_W

Bits 0:7 - Program Flash Region Protect

impl W<u8, Reg<u8, _FEPROT>>

pub fn eprot(&mut self) -> EPROT_W

Bits 0:7 - EEPROM Region Protect

impl W<u8, Reg<u8, _FDPROT>>

pub fn dprot(&mut self) -> DPROT_W

Bits 0:7 - Data Flash Region Protect

impl W<u8, Reg<u8, _CHCFG>>

pub fn source(&mut self) -> SOURCE_W

Bits 0:5 - DMA Channel Source (Slot)

pub fn trig(&mut self) -> TRIG_W

Bit 6 - DMA Channel Trigger Enable

pub fn enbl(&mut self) -> ENBL_W

Bit 7 - DMA Channel Enable

impl W<u32, Reg<u32, _MCR>>

pub fn maxmb(&mut self) -> MAXMB_W

Bits 0:6 - Number Of The Last Message Buffer

pub fn idam(&mut self) -> IDAM_W

Bits 8:9 - ID Acceptance Mode

pub fn aen(&mut self) -> AEN_W

Bit 12 - Abort Enable

pub fn lprioen(&mut self) -> LPRIOEN_W

Bit 13 - Local Priority Enable

pub fn irmq(&mut self) -> IRMQ_W

Bit 16 - Individual Rx Masking And Queue Enable

pub fn srxdis(&mut self) -> SRXDIS_W

Bit 17 - Self Reception Disable

pub fn waksrc(&mut self) -> WAKSRC_W

Bit 19 - Wake Up Source

pub fn wrnen(&mut self) -> WRNEN_W

Bit 21 - Warning Interrupt Enable

pub fn slfwak(&mut self) -> SLFWAK_W

Bit 22 - Self Wake Up

pub fn supv(&mut self) -> SUPV_W

Bit 23 - Supervisor Mode

pub fn softrst(&mut self) -> SOFTRST_W

Bit 25 - Soft Reset

pub fn wakmsk(&mut self) -> WAKMSK_W

Bit 26 - Wake Up Interrupt Mask

pub fn halt(&mut self) -> HALT_W

Bit 28 - Halt FlexCAN

pub fn rfen(&mut self) -> RFEN_W

Bit 29 - Rx FIFO Enable

pub fn frz(&mut self) -> FRZ_W

Bit 30 - Freeze Enable

pub fn mdis(&mut self) -> MDIS_W

Bit 31 - Module Disable

impl W<u32, Reg<u32, _CTRL1>>

pub fn propseg(&mut self) -> PROPSEG_W

Bits 0:2 - Propagation Segment

pub fn lom(&mut self) -> LOM_W

Bit 3 - Listen-Only Mode

pub fn lbuf(&mut self) -> LBUF_W

Bit 4 - Lowest Buffer Transmitted First

pub fn tsyn(&mut self) -> TSYN_W

Bit 5 - Timer Sync

pub fn boffrec(&mut self) -> BOFFREC_W

Bit 6 - Bus Off Recovery

pub fn smp(&mut self) -> SMP_W

Bit 7 - CAN Bit Sampling

pub fn rwrnmsk(&mut self) -> RWRNMSK_W

Bit 10 - Rx Warning Interrupt Mask

pub fn twrnmsk(&mut self) -> TWRNMSK_W

Bit 11 - Tx Warning Interrupt Mask

pub fn lpb(&mut self) -> LPB_W

Bit 12 - Loop Back Mode

pub fn clksrc(&mut self) -> CLKSRC_W

Bit 13 - CAN Engine Clock Source

pub fn errmsk(&mut self) -> ERRMSK_W

Bit 14 - Error Mask

pub fn boffmsk(&mut self) -> BOFFMSK_W

Bit 15 - Bus Off Mask

pub fn pseg2(&mut self) -> PSEG2_W

Bits 16:18 - Phase Segment 2

pub fn pseg1(&mut self) -> PSEG1_W

Bits 19:21 - Phase Segment 1

pub fn rjw(&mut self) -> RJW_W

Bits 22:23 - Resync Jump Width

pub fn presdiv(&mut self) -> PRESDIV_W

Bits 24:31 - Prescaler Division Factor

impl W<u32, Reg<u32, _TIMER>>

pub fn timer(&mut self) -> TIMER_W

Bits 0:15 - Timer Value

impl W<u32, Reg<u32, _RXMGMASK>>

pub fn mg(&mut self) -> MG_W

Bits 0:31 - Rx Mailboxes Global Mask Bits

impl W<u32, Reg<u32, _RX14MASK>>

pub fn rx14m(&mut self) -> RX14M_W

Bits 0:31 - Rx Buffer 14 Mask Bits

impl W<u32, Reg<u32, _RX15MASK>>

pub fn rx15m(&mut self) -> RX15M_W

Bits 0:31 - Rx Buffer 15 Mask Bits

impl W<u32, Reg<u32, _ECR>>

pub fn txerrcnt(&mut self) -> TXERRCNT_W

Bits 0:7 - Transmit Error Counter

pub fn rxerrcnt(&mut self) -> RXERRCNT_W

Bits 8:15 - Receive Error Counter

impl W<u32, Reg<u32, _ESR1>>

pub fn wakint(&mut self) -> WAKINT_W

Bit 0 - Wake-Up Interrupt

pub fn errint(&mut self) -> ERRINT_W

Bit 1 - Error Interrupt

pub fn boffint(&mut self) -> BOFFINT_W

Bit 2 - Bus Off Interrupt

pub fn rwrnint(&mut self) -> RWRNINT_W

Bit 16 - Rx Warning Interrupt Flag

pub fn twrnint(&mut self) -> TWRNINT_W

Bit 17 - Tx Warning Interrupt Flag

impl W<u32, Reg<u32, _IMASK1>>

pub fn buflm(&mut self) -> BUFLM_W

Bits 0:31 - Buffer MB i Mask

impl W<u32, Reg<u32, _IFLAG1>>

pub fn buf0i(&mut self) -> BUF0I_W

Bit 0 - Buffer MB0 Interrupt Or "reserved"

pub fn buf4to1i(&mut self) -> BUF4TO1I_W

Bits 1:4 - Buffer MB i Interrupt Or "reserved"

pub fn buf5i(&mut self) -> BUF5I_W

Bit 5 - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"

pub fn buf6i(&mut self) -> BUF6I_W

Bit 6 - Buffer MB6 Interrupt Or "Rx FIFO Warning"

pub fn buf7i(&mut self) -> BUF7I_W

Bit 7 - Buffer MB7 Interrupt Or "Rx FIFO Overflow"

pub fn buf31to8i(&mut self) -> BUF31TO8I_W

Bits 8:31 - Buffer MBi Interrupt

impl W<u32, Reg<u32, _CTRL2>>

pub fn eacen(&mut self) -> EACEN_W

Bit 16 - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes

pub fn rrs(&mut self) -> RRS_W

Bit 17 - Remote Request Storing

pub fn mrp(&mut self) -> MRP_W

Bit 18 - Mailboxes Reception Priority

pub fn tasd(&mut self) -> TASD_W

Bits 19:23 - Tx Arbitration Start Delay

pub fn rffn(&mut self) -> RFFN_W

Bits 24:27 - Number Of Rx FIFO Filters

pub fn wrmfrz(&mut self) -> WRMFRZ_W

Bit 28 - Write-Access To Memory In Freeze Mode

impl W<u32, Reg<u32, _RXFGMASK>>

pub fn fgm(&mut self) -> FGM_W

Bits 0:31 - Rx FIFO Global Mask Bits

impl W<u32, Reg<u32, _CS0>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID0>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD00>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD10>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS1>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID1>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD01>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD11>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS2>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID2>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD02>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD12>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS3>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID3>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD03>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD13>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS4>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID4>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD04>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD14>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS5>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID5>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD05>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD15>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS6>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID6>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD06>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD16>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS7>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID7>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD07>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD17>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS8>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID8>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD08>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD18>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS9>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID9>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD09>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD19>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS10>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID10>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD010>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD110>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS11>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID11>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD011>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD111>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS12>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID12>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD012>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD112>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS13>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID13>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD013>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD113>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS14>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID14>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD014>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD114>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _CS15>>

pub fn time_stamp(&mut self) -> TIME_STAMP_W

Bits 0:15 - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus.

pub fn dlc(&mut self) -> DLC_W

Bits 16:19 - Length of the data to be stored/transmitted.

pub fn rtr(&mut self) -> RTR_W

Bit 20 - Remote Transmission Request. One/zero for remote/data frame.

pub fn ide(&mut self) -> IDE_W

Bit 21 - ID Extended. One/zero for extended/standard format frame.

pub fn srr(&mut self) -> SRR_W

Bit 22 - Substitute Remote Request. Contains a fixed recessive bit.

pub fn code(&mut self) -> CODE_W

Bits 24:27 - Reserved

impl W<u32, Reg<u32, _ID15>>

pub fn ext(&mut self) -> EXT_W

Bits 0:17 - Contains extended (LOW word) identifier of message buffer.

pub fn std(&mut self) -> STD_W

Bits 18:28 - Contains standard/extended (HIGH word) identifier of message buffer.

pub fn prio(&mut self) -> PRIO_W

Bits 29:31 - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority.

impl W<u32, Reg<u32, _WORD015>>

pub fn data_byte_3(&mut self) -> DATA_BYTE_3_W

Bits 0:7 - Data byte 3 of Rx/Tx frame.

pub fn data_byte_2(&mut self) -> DATA_BYTE_2_W

Bits 8:15 - Data byte 2 of Rx/Tx frame.

pub fn data_byte_1(&mut self) -> DATA_BYTE_1_W

Bits 16:23 - Data byte 1 of Rx/Tx frame.

pub fn data_byte_0(&mut self) -> DATA_BYTE_0_W

Bits 24:31 - Data byte 0 of Rx/Tx frame.

impl W<u32, Reg<u32, _WORD115>>

pub fn data_byte_7(&mut self) -> DATA_BYTE_7_W

Bits 0:7 - Data byte 7 of Rx/Tx frame.

pub fn data_byte_6(&mut self) -> DATA_BYTE_6_W

Bits 8:15 - Data byte 6 of Rx/Tx frame.

pub fn data_byte_5(&mut self) -> DATA_BYTE_5_W

Bits 16:23 - Data byte 5 of Rx/Tx frame.

pub fn data_byte_4(&mut self) -> DATA_BYTE_4_W

Bits 24:31 - Data byte 4 of Rx/Tx frame.

impl W<u32, Reg<u32, _RXIMR>>

pub fn mi(&mut self) -> MI_W

Bits 0:31 - Individual Mask Bits

impl W<u32, Reg<u32, _MCR>>

pub fn halt(&mut self) -> HALT_W

Bit 0 - Halt

pub fn smpl_pt(&mut self) -> SMPL_PT_W

Bits 8:9 - Sample Point

pub fn clr_rxf(&mut self) -> CLR_RXF_W

Bit 10 - Flushes the RX FIFO

pub fn clr_txf(&mut self) -> CLR_TXF_W

Bit 11 - Clear TX FIFO

pub fn dis_rxf(&mut self) -> DIS_RXF_W

Bit 12 - Disable Receive FIFO

pub fn dis_txf(&mut self) -> DIS_TXF_W

Bit 13 - Disable Transmit FIFO

pub fn mdis(&mut self) -> MDIS_W

Bit 14 - Module Disable

pub fn doze(&mut self) -> DOZE_W

Bit 15 - Doze Enable

pub fn pcsis(&mut self) -> PCSIS_W

Bits 16:21 - Peripheral Chip Select x Inactive State

pub fn rooe(&mut self) -> ROOE_W

Bit 24 - Receive FIFO Overflow Overwrite Enable

pub fn pcsse(&mut self) -> PCSSE_W

Bit 25 - Peripheral Chip Select Strobe Enable

pub fn mtfe(&mut self) -> MTFE_W

Bit 26 - Modified Timing Format Enable

pub fn frz(&mut self) -> FRZ_W

Bit 27 - Freeze

pub fn cont_scke(&mut self) -> CONT_SCKE_W

Bit 30 - Continuous SCK Enable

pub fn mstr(&mut self) -> MSTR_W

Bit 31 - Master/Slave Mode Select

impl W<u32, Reg<u32, _TCR>>

pub fn spi_tcnt(&mut self) -> SPI_TCNT_W

Bits 16:31 - SPI Transfer Counter

impl W<u32, Reg<u32, _CTAR>>

pub fn br(&mut self) -> BR_W

Bits 0:3 - Baud Rate Scaler

pub fn dt(&mut self) -> DT_W

Bits 4:7 - Delay After Transfer Scaler

pub fn asc(&mut self) -> ASC_W

Bits 8:11 - After SCK Delay Scaler

pub fn cssck(&mut self) -> CSSCK_W

Bits 12:15 - PCS to SCK Delay Scaler

pub fn pbr(&mut self) -> PBR_W

Bits 16:17 - Baud Rate Prescaler

pub fn pdt(&mut self) -> PDT_W

Bits 18:19 - Delay after Transfer Prescaler

pub fn pasc(&mut self) -> PASC_W

Bits 20:21 - After SCK Delay Prescaler

pub fn pcssck(&mut self) -> PCSSCK_W

Bits 22:23 - PCS to SCK Delay Prescaler

pub fn lsbfe(&mut self) -> LSBFE_W

Bit 24 - LSB First

pub fn cpha(&mut self) -> CPHA_W

Bit 25 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W

Bit 26 - Clock Polarity

pub fn fmsz(&mut self) -> FMSZ_W

Bits 27:30 - Frame Size

pub fn dbr(&mut self) -> DBR_W

Bit 31 - Double Baud Rate

impl W<u32, Reg<u32, _CTAR_SLAVE>>

pub fn cpha(&mut self) -> CPHA_W

Bit 25 - Clock Phase

pub fn cpol(&mut self) -> CPOL_W

Bit 26 - Clock Polarity

pub fn fmsz(&mut self) -> FMSZ_W

Bits 27:31 - Frame Size

impl W<u32, Reg<u32, _SR>>

pub fn rfdf(&mut self) -> RFDF_W

Bit 17 - Receive FIFO Drain Flag

pub fn rfof(&mut self) -> RFOF_W

Bit 19 - Receive FIFO Overflow Flag

pub fn tfff(&mut self) -> TFFF_W

Bit 25 - Transmit FIFO Fill Flag

pub fn tfuf(&mut self) -> TFUF_W

Bit 27 - Transmit FIFO Underflow Flag

pub fn eoqf(&mut self) -> EOQF_W

Bit 28 - End of Queue Flag

pub fn txrxs(&mut self) -> TXRXS_W

Bit 30 - TX and RX Status

pub fn tcf(&mut self) -> TCF_W

Bit 31 - Transfer Complete Flag

impl W<u32, Reg<u32, _RSER>>

pub fn rfdf_dirs(&mut self) -> RFDF_DIRS_W

Bit 16 - Receive FIFO Drain DMA or Interrupt Request Select

pub fn rfdf_re(&mut self) -> RFDF_RE_W

Bit 17 - Receive FIFO Drain Request Enable

pub fn rfof_re(&mut self) -> RFOF_RE_W

Bit 19 - Receive FIFO Overflow Request Enable

pub fn tfff_dirs(&mut self) -> TFFF_DIRS_W

Bit 24 - Transmit FIFO Fill DMA or Interrupt Request Select

pub fn tfff_re(&mut self) -> TFFF_RE_W

Bit 25 - Transmit FIFO Fill Request Enable

pub fn tfuf_re(&mut self) -> TFUF_RE_W

Bit 27 - Transmit FIFO Underflow Request Enable

pub fn eoqf_re(&mut self) -> EOQF_RE_W

Bit 28 - Finished Request Enable

pub fn tcf_re(&mut self) -> TCF_RE_W

Bit 31 - Transmission Complete Request Enable

impl W<u32, Reg<u32, _PUSHR>>

pub fn txdata(&mut self) -> TXDATA_W

Bits 0:15 - Transmit Data

pub fn pcs(&mut self) -> PCS_W

Bits 16:21 - Select which PCS signals are to be asserted for the transfer

pub fn ctcnt(&mut self) -> CTCNT_W

Bit 26 - Clear Transfer Counter

pub fn eoq(&mut self) -> EOQ_W

Bit 27 - End Of Queue

pub fn ctas(&mut self) -> CTAS_W

Bits 28:30 - Clock and Transfer Attributes Select

pub fn cont(&mut self) -> CONT_W

Bit 31 - Continuous Peripheral Chip Select Enable

impl W<u32, Reg<u32, _PUSHR_SLAVE>>

pub fn txdata(&mut self) -> TXDATA_W

Bits 0:31 - Transmit Data

impl W<u32, Reg<u32, _TCSR>>

pub fn frde(&mut self) -> FRDE_W

Bit 0 - FIFO Request DMA Enable

pub fn fwde(&mut self) -> FWDE_W

Bit 1 - FIFO Warning DMA Enable

pub fn frie(&mut self) -> FRIE_W

Bit 8 - FIFO Request Interrupt Enable

pub fn fwie(&mut self) -> FWIE_W

Bit 9 - FIFO Warning Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 10 - FIFO Error Interrupt Enable

pub fn seie(&mut self) -> SEIE_W

Bit 11 - Sync Error Interrupt Enable

pub fn wsie(&mut self) -> WSIE_W

Bit 12 - Word Start Interrupt Enable

pub fn fef(&mut self) -> FEF_W

Bit 18 - FIFO Error Flag

pub fn sef(&mut self) -> SEF_W

Bit 19 - Sync Error Flag

pub fn wsf(&mut self) -> WSF_W

Bit 20 - Word Start Flag

pub fn sr(&mut self) -> SR_W

Bit 24 - Software Reset

pub fn fr(&mut self) -> FR_W

Bit 25 - FIFO Reset

pub fn bce(&mut self) -> BCE_W

Bit 28 - Bit Clock Enable

pub fn dbge(&mut self) -> DBGE_W

Bit 29 - Debug Enable

pub fn stope(&mut self) -> STOPE_W

Bit 30 - Stop Enable

pub fn te(&mut self) -> TE_W

Bit 31 - Transmitter Enable

impl W<u32, Reg<u32, _TCR1>>

pub fn tfw(&mut self) -> TFW_W

Bits 0:2 - Transmit FIFO Watermark

impl W<u32, Reg<u32, _TCR2>>

pub fn div(&mut self) -> DIV_W

Bits 0:7 - Bit Clock Divide

pub fn bcd(&mut self) -> BCD_W

Bit 24 - Bit Clock Direction

pub fn bcp(&mut self) -> BCP_W

Bit 25 - Bit Clock Polarity

pub fn msel(&mut self) -> MSEL_W

Bits 26:27 - MCLK Select

pub fn bci(&mut self) -> BCI_W

Bit 28 - Bit Clock Input

pub fn bcs(&mut self) -> BCS_W

Bit 29 - Bit Clock Swap

pub fn sync(&mut self) -> SYNC_W

Bits 30:31 - Synchronous Mode

impl W<u32, Reg<u32, _TCR3>>

pub fn wdfl(&mut self) -> WDFL_W

Bits 0:4 - Word Flag Configuration

pub fn tce(&mut self) -> TCE_W

Bits 16:17 - Transmit Channel Enable

impl W<u32, Reg<u32, _TCR4>>

pub fn fsd(&mut self) -> FSD_W

Bit 0 - Frame Sync Direction

pub fn fsp(&mut self) -> FSP_W

Bit 1 - Frame Sync Polarity

pub fn fse(&mut self) -> FSE_W

Bit 3 - Frame Sync Early

pub fn mf(&mut self) -> MF_W

Bit 4 - MSB First

pub fn sywd(&mut self) -> SYWD_W

Bits 8:12 - Sync Width

pub fn frsz(&mut self) -> FRSZ_W

Bits 16:20 - Frame size

impl W<u32, Reg<u32, _TCR5>>

pub fn fbt(&mut self) -> FBT_W

Bits 8:12 - First Bit Shifted

pub fn w0w(&mut self) -> W0W_W

Bits 16:20 - Word 0 Width

pub fn wnw(&mut self) -> WNW_W

Bits 24:28 - Word N Width

impl W<u32, Reg<u32, _TDR>>

pub fn tdr(&mut self) -> TDR_W

Bits 0:31 - Transmit Data Register

impl W<u32, Reg<u32, _TMR>>

pub fn twm(&mut self) -> TWM_W

Bits 0:31 - Transmit Word Mask

impl W<u32, Reg<u32, _RCSR>>

pub fn frde(&mut self) -> FRDE_W

Bit 0 - FIFO Request DMA Enable

pub fn fwde(&mut self) -> FWDE_W

Bit 1 - FIFO Warning DMA Enable

pub fn frie(&mut self) -> FRIE_W

Bit 8 - FIFO Request Interrupt Enable

pub fn fwie(&mut self) -> FWIE_W

Bit 9 - FIFO Warning Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 10 - FIFO Error Interrupt Enable

pub fn seie(&mut self) -> SEIE_W

Bit 11 - Sync Error Interrupt Enable

pub fn wsie(&mut self) -> WSIE_W

Bit 12 - Word Start Interrupt Enable

pub fn fef(&mut self) -> FEF_W

Bit 18 - FIFO Error Flag

pub fn sef(&mut self) -> SEF_W

Bit 19 - Sync Error Flag

pub fn wsf(&mut self) -> WSF_W

Bit 20 - Word Start Flag

pub fn sr(&mut self) -> SR_W

Bit 24 - Software Reset

pub fn fr(&mut self) -> FR_W

Bit 25 - FIFO Reset

pub fn bce(&mut self) -> BCE_W

Bit 28 - Bit Clock Enable

pub fn dbge(&mut self) -> DBGE_W

Bit 29 - Debug Enable

pub fn stope(&mut self) -> STOPE_W

Bit 30 - Stop Enable

pub fn re(&mut self) -> RE_W

Bit 31 - Receiver Enable

impl W<u32, Reg<u32, _RCR1>>

pub fn rfw(&mut self) -> RFW_W

Bits 0:2 - Receive FIFO Watermark

impl W<u32, Reg<u32, _RCR2>>

pub fn div(&mut self) -> DIV_W

Bits 0:7 - Bit Clock Divide

pub fn bcd(&mut self) -> BCD_W

Bit 24 - Bit Clock Direction

pub fn bcp(&mut self) -> BCP_W

Bit 25 - Bit Clock Polarity

pub fn msel(&mut self) -> MSEL_W

Bits 26:27 - MCLK Select

pub fn bci(&mut self) -> BCI_W

Bit 28 - Bit Clock Input

pub fn bcs(&mut self) -> BCS_W

Bit 29 - Bit Clock Swap

pub fn sync(&mut self) -> SYNC_W

Bits 30:31 - Synchronous Mode

impl W<u32, Reg<u32, _RCR3>>

pub fn wdfl(&mut self) -> WDFL_W

Bits 0:4 - Word Flag Configuration

pub fn rce(&mut self) -> RCE_W

Bits 16:17 - Receive Channel Enable

impl W<u32, Reg<u32, _RCR4>>

pub fn fsd(&mut self) -> FSD_W

Bit 0 - Frame Sync Direction

pub fn fsp(&mut self) -> FSP_W

Bit 1 - Frame Sync Polarity

pub fn fse(&mut self) -> FSE_W

Bit 3 - Frame Sync Early

pub fn mf(&mut self) -> MF_W

Bit 4 - MSB First

pub fn sywd(&mut self) -> SYWD_W

Bits 8:12 - Sync Width

pub fn frsz(&mut self) -> FRSZ_W

Bits 16:20 - Frame Size

impl W<u32, Reg<u32, _RCR5>>

pub fn fbt(&mut self) -> FBT_W

Bits 8:12 - First Bit Shifted

pub fn w0w(&mut self) -> W0W_W

Bits 16:20 - Word 0 Width

pub fn wnw(&mut self) -> WNW_W

Bits 24:28 - Word N Width

impl W<u32, Reg<u32, _RMR>>

pub fn rwm(&mut self) -> RWM_W

Bits 0:31 - Receive Word Mask

impl W<u32, Reg<u32, _MCR>>

pub fn mics(&mut self) -> MICS_W

Bits 24:25 - MCLK Input Clock Select

pub fn moe(&mut self) -> MOE_W

Bit 30 - MCLK Output Enable

impl W<u32, Reg<u32, _MDR>>

pub fn divide(&mut self) -> DIVIDE_W

Bits 0:11 - MCLK Divide

pub fn fract(&mut self) -> FRACT_W

Bits 12:19 - MCLK Fraction

impl W<u32, Reg<u32, _DATA>>

pub fn ll(&mut self) -> LL_W

Bits 0:7 - CRC Low Lower Byte

pub fn lu(&mut self) -> LU_W

Bits 8:15 - CRC Low Upper Byte

pub fn hl(&mut self) -> HL_W

Bits 16:23 - CRC High Lower Byte

pub fn hu(&mut self) -> HU_W

Bits 24:31 - CRC High Upper Byte

impl W<u16, Reg<u16, _DATAL>>

pub fn datal(&mut self) -> DATAL_W

Bits 0:15 - DATAL stores the lower 16 bits of the 16/32 bit CRC

impl W<u8, Reg<u8, _DATALL>>

pub fn datall(&mut self) -> DATALL_W

Bits 0:7 - CRCLL stores the first 8 bits of the 32 bit DATA

impl W<u8, Reg<u8, _DATALU>>

pub fn datalu(&mut self) -> DATALU_W

Bits 0:7 - DATALL stores the second 8 bits of the 32 bit CRC

impl W<u16, Reg<u16, _DATAH>>

pub fn datah(&mut self) -> DATAH_W

Bits 0:15 - DATAH stores the high 16 bits of the 16/32 bit CRC

impl W<u8, Reg<u8, _DATAHL>>

pub fn datahl(&mut self) -> DATAHL_W

Bits 0:7 - DATAHL stores the third 8 bits of the 32 bit CRC

impl W<u8, Reg<u8, _DATAHU>>

pub fn datahu(&mut self) -> DATAHU_W

Bits 0:7 - DATAHU stores the fourth 8 bits of the 32 bit CRC

impl W<u32, Reg<u32, _GPOLY>>

pub fn low(&mut self) -> LOW_W

Bits 0:15 - Low Polynominal Half-word

pub fn high(&mut self) -> HIGH_W

Bits 16:31 - High Polynominal Half-word

impl W<u16, Reg<u16, _GPOLYL>>

pub fn gpolyl(&mut self) -> GPOLYL_W

Bits 0:15 - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value

impl W<u8, Reg<u8, _GPOLYLL>>

pub fn gpolyll(&mut self) -> GPOLYLL_W

Bits 0:7 - POLYLL stores the first 8 bits of the 32 bit CRC

impl W<u8, Reg<u8, _GPOLYLU>>

pub fn gpolylu(&mut self) -> GPOLYLU_W

Bits 0:7 - POLYLL stores the second 8 bits of the 32 bit CRC

impl W<u16, Reg<u16, _GPOLYH>>

pub fn gpolyh(&mut self) -> GPOLYH_W

Bits 0:15 - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value

impl W<u8, Reg<u8, _GPOLYHL>>

pub fn gpolyhl(&mut self) -> GPOLYHL_W

Bits 0:7 - POLYHL stores the third 8 bits of the 32 bit CRC

impl W<u8, Reg<u8, _GPOLYHU>>

pub fn gpolyhu(&mut self) -> GPOLYHU_W

Bits 0:7 - POLYHU stores the fourth 8 bits of the 32 bit CRC

impl W<u32, Reg<u32, _CTRL>>

pub fn tcrc(&mut self) -> TCRC_W

Bit 24 - Width of CRC protocol.

pub fn was(&mut self) -> WAS_W

Bit 25 - Write CRC Data Register As Seed

pub fn fxor(&mut self) -> FXOR_W

Bit 26 - Complement Read Of CRC Data Register

pub fn totr(&mut self) -> TOTR_W

Bits 28:29 - Type Of Transpose For Read

pub fn tot(&mut self) -> TOT_W

Bits 30:31 - Type Of Transpose For Writes

impl W<u8, Reg<u8, _CTRLHU>>

pub fn tcrc(&mut self) -> TCRC_W

Bit 0 - no description available

pub fn was(&mut self) -> WAS_W

Bit 1 - no description available

pub fn fxor(&mut self) -> FXOR_W

Bit 2 - no description available

pub fn totr(&mut self) -> TOTR_W

Bits 4:5 - no description available

pub fn tot(&mut self) -> TOT_W

Bits 6:7 - no description available

impl W<u32, Reg<u32, _CONTROL>>

pub fn iack(&mut self) -> IACK_W

Bit 0 - Interrupt Acknowledge

pub fn ie(&mut self) -> IE_W

Bit 16 - Interrupt Enable

pub fn bc12(&mut self) -> BC12_W

Bit 17 - BC1.2 compatibility. This bit cannot be changed after start detection.

pub fn start(&mut self) -> START_W

Bit 24 - Start Change Detection Sequence

pub fn sr(&mut self) -> SR_W

Bit 25 - Software Reset

impl W<u32, Reg<u32, _CLOCK>>

pub fn clock_unit(&mut self) -> CLOCK_UNIT_W

Bit 0 - Unit of Measurement Encoding for Clock Speed

pub fn clock_speed(&mut self) -> CLOCK_SPEED_W

Bits 2:11 - Numerical Value of Clock Speed in Binary

impl W<u32, Reg<u32, _TIMER0>>

pub fn tseq_init(&mut self) -> TSEQ_INIT_W

Bits 16:25 - Sequence Initiation Time

impl W<u32, Reg<u32, _TIMER1>>

pub fn tvdpsrc_on(&mut self) -> TVDPSRC_ON_W

Bits 0:9 - Time Period Comparator Enabled

pub fn tdcd_dbnc(&mut self) -> TDCD_DBNC_W

Bits 16:25 - Time Period to Debounce D+ Signal

impl W<u32, Reg<u32, _TIMER2_BC11>>

pub fn check_dm(&mut self) -> CHECK_DM_W

Bits 0:3 - Time Before Check of D- Line

pub fn tvdpsrc_con(&mut self) -> TVDPSRC_CON_W

Bits 16:25 - Time Period Before Enabling D+ Pullup

impl W<u32, Reg<u32, _TIMER2_BC12>>

pub fn tvdmsrc_on(&mut self) -> TVDMSRC_ON_W

Bits 0:9 - Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid values are 0-40ms.

pub fn twait_after_prd(&mut self) -> TWAIT_AFTER_PRD_W

Bits 16:25 - Sets the amount of time (in ms) that the module waits after primary detection before start to secondary detection

impl W<u32, Reg<u32, _SC>>

pub fn ldok(&mut self) -> LDOK_W

Bit 0 - Load OK

pub fn cont(&mut self) -> CONT_W

Bit 1 - Continuous Mode Enable

pub fn mult(&mut self) -> MULT_W

Bits 2:3 - Multiplication Factor Select for Prescaler

pub fn pdbie(&mut self) -> PDBIE_W

Bit 5 - PDB Interrupt Enable

pub fn pdbif(&mut self) -> PDBIF_W

Bit 6 - PDB Interrupt Flag

pub fn pdben(&mut self) -> PDBEN_W

Bit 7 - PDB Enable

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 8:11 - Trigger Input Source Select

pub fn prescaler(&mut self) -> PRESCALER_W

Bits 12:14 - Prescaler Divider Select

pub fn dmaen(&mut self) -> DMAEN_W

Bit 15 - DMA Enable

pub fn swtrig(&mut self) -> SWTRIG_W

Bit 16 - Software Trigger

pub fn pdbeie(&mut self) -> PDBEIE_W

Bit 17 - PDB Sequence Error Interrupt Enable

pub fn ldmod(&mut self) -> LDMOD_W

Bits 18:19 - Load Mode Select

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - PDB Modulus

impl W<u32, Reg<u32, _IDLY>>

pub fn idly(&mut self) -> IDLY_W

Bits 0:15 - PDB Interrupt Delay

impl W<u32, Reg<u32, _CHC1>>

pub fn en(&mut self) -> EN_W

Bits 0:7 - PDB Channel Pre-Trigger Enable

pub fn tos(&mut self) -> TOS_W

Bits 8:15 - PDB Channel Pre-Trigger Output Select

pub fn bb(&mut self) -> BB_W

Bits 16:23 - PDB Channel Pre-Trigger Back-to-Back Operation Enable

impl W<u32, Reg<u32, _CHS>>

pub fn err(&mut self) -> ERR_W

Bits 0:7 - PDB Channel Sequence Error Flags

pub fn cf(&mut self) -> CF_W

Bits 16:23 - PDB Channel Flags

impl W<u32, Reg<u32, _CHDLY0>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _CHDLY1>>

pub fn dly(&mut self) -> DLY_W

Bits 0:15 - PDB Channel Delay

impl W<u32, Reg<u32, _DACINTC>>

pub fn toe(&mut self) -> TOE_W

Bit 0 - DAC Interval Trigger Enable

pub fn ext(&mut self) -> EXT_W

Bit 1 - DAC External Trigger Input Enable

impl W<u32, Reg<u32, _DACINT>>

pub fn int(&mut self) -> INT_W

Bits 0:15 - DAC Interval

impl W<u32, Reg<u32, _POEN>>

pub fn poen(&mut self) -> POEN_W

Bits 0:7 - PDB Pulse-Out Enable

impl W<u32, Reg<u32, _PODLY>>

pub fn dly2(&mut self) -> DLY2_W

Bits 0:15 - PDB Pulse-Out Delay 2

pub fn dly1(&mut self) -> DLY1_W

Bits 16:31 - PDB Pulse-Out Delay 1

impl W<u32, Reg<u32, _MCR>>

pub fn frz(&mut self) -> FRZ_W

Bit 0 - Freeze

pub fn mdis(&mut self) -> MDIS_W

Bit 1 - Module Disable - (PIT section)

impl W<u32, Reg<u32, _LDVAL>>

pub fn tsv(&mut self) -> TSV_W

Bits 0:31 - Timer Start Value

impl W<u32, Reg<u32, _TCTRL>>

pub fn ten(&mut self) -> TEN_W

Bit 0 - Timer Enable

pub fn tie(&mut self) -> TIE_W

Bit 1 - Timer Interrupt Enable

pub fn chn(&mut self) -> CHN_W

Bit 2 - Chain Mode

impl W<u32, Reg<u32, _TFLG>>

pub fn tif(&mut self) -> TIF_W

Bit 0 - Timer Interrupt Flag

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn toie(&mut self) -> TOIE_W

Bit 6 - Timer Overflow Interrupt Enable

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - Modulo Value

impl W<u32, Reg<u32, _CSC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel Interrupt Enable

impl W<u32, Reg<u32, _CV>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - Initial Value Of The FTM Counter

impl W<u32, Reg<u32, _STATUS>>

pub fn ch0f(&mut self) -> CH0F_W

Bit 0 - Channel 0 Flag

pub fn ch1f(&mut self) -> CH1F_W

Bit 1 - Channel 1 Flag

pub fn ch2f(&mut self) -> CH2F_W

Bit 2 - Channel 2 Flag

pub fn ch3f(&mut self) -> CH3F_W

Bit 3 - Channel 3 Flag

pub fn ch4f(&mut self) -> CH4F_W

Bit 4 - Channel 4 Flag

pub fn ch5f(&mut self) -> CH5F_W

Bit 5 - Channel 5 Flag

pub fn ch6f(&mut self) -> CH6F_W

Bit 6 - Channel 6 Flag

pub fn ch7f(&mut self) -> CH7F_W

Bit 7 - Channel 7 Flag

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn numtof(&mut self) -> NUMTOF_W

Bits 0:4 - TOF Frequency

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - BDM Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger.

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn toie(&mut self) -> TOIE_W

Bit 6 - Timer Overflow Interrupt Enable

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - Modulo Value

impl W<u32, Reg<u32, _CSC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel Interrupt Enable

impl W<u32, Reg<u32, _CV>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - Initial Value Of The FTM Counter

impl W<u32, Reg<u32, _STATUS>>

pub fn ch0f(&mut self) -> CH0F_W

Bit 0 - Channel 0 Flag

pub fn ch1f(&mut self) -> CH1F_W

Bit 1 - Channel 1 Flag

pub fn ch2f(&mut self) -> CH2F_W

Bit 2 - Channel 2 Flag

pub fn ch3f(&mut self) -> CH3F_W

Bit 3 - Channel 3 Flag

pub fn ch4f(&mut self) -> CH4F_W

Bit 4 - Channel 4 Flag

pub fn ch5f(&mut self) -> CH5F_W

Bit 5 - Channel 5 Flag

pub fn ch6f(&mut self) -> CH6F_W

Bit 6 - Channel 6 Flag

pub fn ch7f(&mut self) -> CH7F_W

Bit 7 - Channel 7 Flag

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn numtof(&mut self) -> NUMTOF_W

Bits 0:4 - TOF Frequency

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - BDM Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger.

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn toie(&mut self) -> TOIE_W

Bit 6 - Timer Overflow Interrupt Enable

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - Modulo Value

impl W<u32, Reg<u32, _CSC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel Interrupt Enable

impl W<u32, Reg<u32, _CV>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - Initial Value Of The FTM Counter

impl W<u32, Reg<u32, _STATUS>>

pub fn ch0f(&mut self) -> CH0F_W

Bit 0 - Channel 0 Flag

pub fn ch1f(&mut self) -> CH1F_W

Bit 1 - Channel 1 Flag

pub fn ch2f(&mut self) -> CH2F_W

Bit 2 - Channel 2 Flag

pub fn ch3f(&mut self) -> CH3F_W

Bit 3 - Channel 3 Flag

pub fn ch4f(&mut self) -> CH4F_W

Bit 4 - Channel 4 Flag

pub fn ch5f(&mut self) -> CH5F_W

Bit 5 - Channel 5 Flag

pub fn ch6f(&mut self) -> CH6F_W

Bit 6 - Channel 6 Flag

pub fn ch7f(&mut self) -> CH7F_W

Bit 7 - Channel 7 Flag

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn numtof(&mut self) -> NUMTOF_W

Bits 0:4 - TOF Frequency

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - BDM Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger.

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

impl W<u32, Reg<u32, _SC>>

pub fn ps(&mut self) -> PS_W

Bits 0:2 - Prescale Factor Selection

pub fn clks(&mut self) -> CLKS_W

Bits 3:4 - Clock Source Selection

pub fn cpwms(&mut self) -> CPWMS_W

Bit 5 - Center-Aligned PWM Select

pub fn toie(&mut self) -> TOIE_W

Bit 6 - Timer Overflow Interrupt Enable

impl W<u32, Reg<u32, _CNT>>

pub fn count(&mut self) -> COUNT_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _MOD>>

pub fn mod_(&mut self) -> MOD_W

Bits 0:15 - Modulo Value

impl W<u32, Reg<u32, _CSC>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

pub fn elsa(&mut self) -> ELSA_W

Bit 2 - Edge or Level Select

pub fn elsb(&mut self) -> ELSB_W

Bit 3 - Edge or Level Select

pub fn msa(&mut self) -> MSA_W

Bit 4 - Channel Mode Select

pub fn msb(&mut self) -> MSB_W

Bit 5 - Channel Mode Select

pub fn chie(&mut self) -> CHIE_W

Bit 6 - Channel Interrupt Enable

impl W<u32, Reg<u32, _CV>>

pub fn val(&mut self) -> VAL_W

Bits 0:15 - Channel Value

impl W<u32, Reg<u32, _CNTIN>>

pub fn init(&mut self) -> INIT_W

Bits 0:15 - Initial Value Of The FTM Counter

impl W<u32, Reg<u32, _STATUS>>

pub fn ch0f(&mut self) -> CH0F_W

Bit 0 - Channel 0 Flag

pub fn ch1f(&mut self) -> CH1F_W

Bit 1 - Channel 1 Flag

pub fn ch2f(&mut self) -> CH2F_W

Bit 2 - Channel 2 Flag

pub fn ch3f(&mut self) -> CH3F_W

Bit 3 - Channel 3 Flag

pub fn ch4f(&mut self) -> CH4F_W

Bit 4 - Channel 4 Flag

pub fn ch5f(&mut self) -> CH5F_W

Bit 5 - Channel 5 Flag

pub fn ch6f(&mut self) -> CH6F_W

Bit 6 - Channel 6 Flag

pub fn ch7f(&mut self) -> CH7F_W

Bit 7 - Channel 7 Flag

impl W<u32, Reg<u32, _MODE>>

pub fn ftmen(&mut self) -> FTMEN_W

Bit 0 - FTM Enable

pub fn init(&mut self) -> INIT_W

Bit 1 - Initialize The Channels Output

pub fn wpdis(&mut self) -> WPDIS_W

Bit 2 - Write Protection Disable

pub fn pwmsync(&mut self) -> PWMSYNC_W

Bit 3 - PWM Synchronization Mode

pub fn captest(&mut self) -> CAPTEST_W

Bit 4 - Capture Test Mode Enable

pub fn faultm(&mut self) -> FAULTM_W

Bits 5:6 - Fault Control Mode

pub fn faultie(&mut self) -> FAULTIE_W

Bit 7 - Fault Interrupt Enable

impl W<u32, Reg<u32, _SYNC>>

pub fn cntmin(&mut self) -> CNTMIN_W

Bit 0 - Minimum Loading Point Enable

pub fn cntmax(&mut self) -> CNTMAX_W

Bit 1 - Maximum Loading Point Enable

pub fn reinit(&mut self) -> REINIT_W

Bit 2 - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)

pub fn synchom(&mut self) -> SYNCHOM_W

Bit 3 - Output Mask Synchronization

pub fn trig0(&mut self) -> TRIG0_W

Bit 4 - PWM Synchronization Hardware Trigger 0

pub fn trig1(&mut self) -> TRIG1_W

Bit 5 - PWM Synchronization Hardware Trigger 1

pub fn trig2(&mut self) -> TRIG2_W

Bit 6 - PWM Synchronization Hardware Trigger 2

pub fn swsync(&mut self) -> SWSYNC_W

Bit 7 - PWM Synchronization Software Trigger

impl W<u32, Reg<u32, _OUTINIT>>

pub fn ch0oi(&mut self) -> CH0OI_W

Bit 0 - Channel 0 Output Initialization Value

pub fn ch1oi(&mut self) -> CH1OI_W

Bit 1 - Channel 1 Output Initialization Value

pub fn ch2oi(&mut self) -> CH2OI_W

Bit 2 - Channel 2 Output Initialization Value

pub fn ch3oi(&mut self) -> CH3OI_W

Bit 3 - Channel 3 Output Initialization Value

pub fn ch4oi(&mut self) -> CH4OI_W

Bit 4 - Channel 4 Output Initialization Value

pub fn ch5oi(&mut self) -> CH5OI_W

Bit 5 - Channel 5 Output Initialization Value

pub fn ch6oi(&mut self) -> CH6OI_W

Bit 6 - Channel 6 Output Initialization Value

pub fn ch7oi(&mut self) -> CH7OI_W

Bit 7 - Channel 7 Output Initialization Value

impl W<u32, Reg<u32, _OUTMASK>>

pub fn ch0om(&mut self) -> CH0OM_W

Bit 0 - Channel 0 Output Mask

pub fn ch1om(&mut self) -> CH1OM_W

Bit 1 - Channel 1 Output Mask

pub fn ch2om(&mut self) -> CH2OM_W

Bit 2 - Channel 2 Output Mask

pub fn ch3om(&mut self) -> CH3OM_W

Bit 3 - Channel 3 Output Mask

pub fn ch4om(&mut self) -> CH4OM_W

Bit 4 - Channel 4 Output Mask

pub fn ch5om(&mut self) -> CH5OM_W

Bit 5 - Channel 5 Output Mask

pub fn ch6om(&mut self) -> CH6OM_W

Bit 6 - Channel 6 Output Mask

pub fn ch7om(&mut self) -> CH7OM_W

Bit 7 - Channel 7 Output Mask

impl W<u32, Reg<u32, _COMBINE>>

pub fn combine0(&mut self) -> COMBINE0_W

Bit 0 - Combine Channels For n = 0

pub fn comp0(&mut self) -> COMP0_W

Bit 1 - Complement Of Channel (n) For n = 0

pub fn decapen0(&mut self) -> DECAPEN0_W

Bit 2 - Dual Edge Capture Mode Enable For n = 0

pub fn decap0(&mut self) -> DECAP0_W

Bit 3 - Dual Edge Capture Mode Captures For n = 0

pub fn dten0(&mut self) -> DTEN0_W

Bit 4 - Deadtime Enable For n = 0

pub fn syncen0(&mut self) -> SYNCEN0_W

Bit 5 - Synchronization Enable For n = 0

pub fn faulten0(&mut self) -> FAULTEN0_W

Bit 6 - Fault Control Enable For n = 0

pub fn combine1(&mut self) -> COMBINE1_W

Bit 8 - Combine Channels For n = 2

pub fn comp1(&mut self) -> COMP1_W

Bit 9 - Complement Of Channel (n) For n = 2

pub fn decapen1(&mut self) -> DECAPEN1_W

Bit 10 - Dual Edge Capture Mode Enable For n = 2

pub fn decap1(&mut self) -> DECAP1_W

Bit 11 - Dual Edge Capture Mode Captures For n = 2

pub fn dten1(&mut self) -> DTEN1_W

Bit 12 - Deadtime Enable For n = 2

pub fn syncen1(&mut self) -> SYNCEN1_W

Bit 13 - Synchronization Enable For n = 2

pub fn faulten1(&mut self) -> FAULTEN1_W

Bit 14 - Fault Control Enable For n = 2

pub fn combine2(&mut self) -> COMBINE2_W

Bit 16 - Combine Channels For n = 4

pub fn comp2(&mut self) -> COMP2_W

Bit 17 - Complement Of Channel (n) For n = 4

pub fn decapen2(&mut self) -> DECAPEN2_W

Bit 18 - Dual Edge Capture Mode Enable For n = 4

pub fn decap2(&mut self) -> DECAP2_W

Bit 19 - Dual Edge Capture Mode Captures For n = 4

pub fn dten2(&mut self) -> DTEN2_W

Bit 20 - Deadtime Enable For n = 4

pub fn syncen2(&mut self) -> SYNCEN2_W

Bit 21 - Synchronization Enable For n = 4

pub fn faulten2(&mut self) -> FAULTEN2_W

Bit 22 - Fault Control Enable For n = 4

pub fn combine3(&mut self) -> COMBINE3_W

Bit 24 - Combine Channels For n = 6

pub fn comp3(&mut self) -> COMP3_W

Bit 25 - Complement Of Channel (n) for n = 6

pub fn decapen3(&mut self) -> DECAPEN3_W

Bit 26 - Dual Edge Capture Mode Enable For n = 6

pub fn decap3(&mut self) -> DECAP3_W

Bit 27 - Dual Edge Capture Mode Captures For n = 6

pub fn dten3(&mut self) -> DTEN3_W

Bit 28 - Deadtime Enable For n = 6

pub fn syncen3(&mut self) -> SYNCEN3_W

Bit 29 - Synchronization Enable For n = 6

pub fn faulten3(&mut self) -> FAULTEN3_W

Bit 30 - Fault Control Enable For n = 6

impl W<u32, Reg<u32, _DEADTIME>>

pub fn dtval(&mut self) -> DTVAL_W

Bits 0:5 - Deadtime Value

pub fn dtps(&mut self) -> DTPS_W

Bits 6:7 - Deadtime Prescaler Value

impl W<u32, Reg<u32, _EXTTRIG>>

pub fn ch2trig(&mut self) -> CH2TRIG_W

Bit 0 - Channel 2 Trigger Enable

pub fn ch3trig(&mut self) -> CH3TRIG_W

Bit 1 - Channel 3 Trigger Enable

pub fn ch4trig(&mut self) -> CH4TRIG_W

Bit 2 - Channel 4 Trigger Enable

pub fn ch5trig(&mut self) -> CH5TRIG_W

Bit 3 - Channel 5 Trigger Enable

pub fn ch0trig(&mut self) -> CH0TRIG_W

Bit 4 - Channel 0 Trigger Enable

pub fn ch1trig(&mut self) -> CH1TRIG_W

Bit 5 - Channel 1 Trigger Enable

pub fn inittrigen(&mut self) -> INITTRIGEN_W

Bit 6 - Initialization Trigger Enable

impl W<u32, Reg<u32, _POL>>

pub fn pol0(&mut self) -> POL0_W

Bit 0 - Channel 0 Polarity

pub fn pol1(&mut self) -> POL1_W

Bit 1 - Channel 1 Polarity

pub fn pol2(&mut self) -> POL2_W

Bit 2 - Channel 2 Polarity

pub fn pol3(&mut self) -> POL3_W

Bit 3 - Channel 3 Polarity

pub fn pol4(&mut self) -> POL4_W

Bit 4 - Channel 4 Polarity

pub fn pol5(&mut self) -> POL5_W

Bit 5 - Channel 5 Polarity

pub fn pol6(&mut self) -> POL6_W

Bit 6 - Channel 6 Polarity

pub fn pol7(&mut self) -> POL7_W

Bit 7 - Channel 7 Polarity

impl W<u32, Reg<u32, _FMS>>

pub fn wpen(&mut self) -> WPEN_W

Bit 6 - Write Protection Enable

impl W<u32, Reg<u32, _FILTER>>

pub fn ch0fval(&mut self) -> CH0FVAL_W

Bits 0:3 - Channel 0 Input Filter

pub fn ch1fval(&mut self) -> CH1FVAL_W

Bits 4:7 - Channel 1 Input Filter

pub fn ch2fval(&mut self) -> CH2FVAL_W

Bits 8:11 - Channel 2 Input Filter

pub fn ch3fval(&mut self) -> CH3FVAL_W

Bits 12:15 - Channel 3 Input Filter

impl W<u32, Reg<u32, _FLTCTRL>>

pub fn fault0en(&mut self) -> FAULT0EN_W

Bit 0 - Fault Input 0 Enable

pub fn fault1en(&mut self) -> FAULT1EN_W

Bit 1 - Fault Input 1 Enable

pub fn fault2en(&mut self) -> FAULT2EN_W

Bit 2 - Fault Input 2 Enable

pub fn fault3en(&mut self) -> FAULT3EN_W

Bit 3 - Fault Input 3 Enable

pub fn ffltr0en(&mut self) -> FFLTR0EN_W

Bit 4 - Fault Input 0 Filter Enable

pub fn ffltr1en(&mut self) -> FFLTR1EN_W

Bit 5 - Fault Input 1 Filter Enable

pub fn ffltr2en(&mut self) -> FFLTR2EN_W

Bit 6 - Fault Input 2 Filter Enable

pub fn ffltr3en(&mut self) -> FFLTR3EN_W

Bit 7 - Fault Input 3 Filter Enable

pub fn ffval(&mut self) -> FFVAL_W

Bits 8:11 - Fault Input Filter

impl W<u32, Reg<u32, _QDCTRL>>

pub fn quaden(&mut self) -> QUADEN_W

Bit 0 - Quadrature Decoder Mode Enable

pub fn quadmode(&mut self) -> QUADMODE_W

Bit 3 - Quadrature Decoder Mode

pub fn phbpol(&mut self) -> PHBPOL_W

Bit 4 - Phase B Input Polarity

pub fn phapol(&mut self) -> PHAPOL_W

Bit 5 - Phase A Input Polarity

pub fn phbfltren(&mut self) -> PHBFLTREN_W

Bit 6 - Phase B Input Filter Enable

pub fn phafltren(&mut self) -> PHAFLTREN_W

Bit 7 - Phase A Input Filter Enable

impl W<u32, Reg<u32, _CONF>>

pub fn numtof(&mut self) -> NUMTOF_W

Bits 0:4 - TOF Frequency

pub fn bdmmode(&mut self) -> BDMMODE_W

Bits 6:7 - BDM Mode

pub fn gtbeen(&mut self) -> GTBEEN_W

Bit 9 - Global Time Base Enable

pub fn gtbeout(&mut self) -> GTBEOUT_W

Bit 10 - Global Time Base Output

impl W<u32, Reg<u32, _FLTPOL>>

pub fn flt0pol(&mut self) -> FLT0POL_W

Bit 0 - Fault Input 0 Polarity

pub fn flt1pol(&mut self) -> FLT1POL_W

Bit 1 - Fault Input 1 Polarity

pub fn flt2pol(&mut self) -> FLT2POL_W

Bit 2 - Fault Input 2 Polarity

pub fn flt3pol(&mut self) -> FLT3POL_W

Bit 3 - Fault Input 3 Polarity

impl W<u32, Reg<u32, _SYNCONF>>

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&mut self) -> SWWRBUF_W

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&mut self) -> SWOM_W

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&mut self) -> SWINVC_W

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&mut self) -> SWSOC_W

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&mut self) -> HWWRBUF_W

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&mut self) -> HWOM_W

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&mut self) -> HWINVC_W

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&mut self) -> HWSOC_W

Bit 20 - Software output control synchronization is activated by a hardware trigger.

impl W<u32, Reg<u32, _INVCTRL>>

pub fn inv0en(&mut self) -> INV0EN_W

Bit 0 - Pair Channels 0 Inverting Enable

pub fn inv1en(&mut self) -> INV1EN_W

Bit 1 - Pair Channels 1 Inverting Enable

pub fn inv2en(&mut self) -> INV2EN_W

Bit 2 - Pair Channels 2 Inverting Enable

pub fn inv3en(&mut self) -> INV3EN_W

Bit 3 - Pair Channels 3 Inverting Enable

impl W<u32, Reg<u32, _SWOCTRL>>

pub fn ch0oc(&mut self) -> CH0OC_W

Bit 0 - Channel 0 Software Output Control Enable

pub fn ch1oc(&mut self) -> CH1OC_W

Bit 1 - Channel 1 Software Output Control Enable

pub fn ch2oc(&mut self) -> CH2OC_W

Bit 2 - Channel 2 Software Output Control Enable

pub fn ch3oc(&mut self) -> CH3OC_W

Bit 3 - Channel 3 Software Output Control Enable

pub fn ch4oc(&mut self) -> CH4OC_W

Bit 4 - Channel 4 Software Output Control Enable

pub fn ch5oc(&mut self) -> CH5OC_W

Bit 5 - Channel 5 Software Output Control Enable

pub fn ch6oc(&mut self) -> CH6OC_W

Bit 6 - Channel 6 Software Output Control Enable

pub fn ch7oc(&mut self) -> CH7OC_W

Bit 7 - Channel 7 Software Output Control Enable

pub fn ch0ocv(&mut self) -> CH0OCV_W

Bit 8 - Channel 0 Software Output Control Value

pub fn ch1ocv(&mut self) -> CH1OCV_W

Bit 9 - Channel 1 Software Output Control Value

pub fn ch2ocv(&mut self) -> CH2OCV_W

Bit 10 - Channel 2 Software Output Control Value

pub fn ch3ocv(&mut self) -> CH3OCV_W

Bit 11 - Channel 3 Software Output Control Value

pub fn ch4ocv(&mut self) -> CH4OCV_W

Bit 12 - Channel 4 Software Output Control Value

pub fn ch5ocv(&mut self) -> CH5OCV_W

Bit 13 - Channel 5 Software Output Control Value

pub fn ch6ocv(&mut self) -> CH6OCV_W

Bit 14 - Channel 6 Software Output Control Value

pub fn ch7ocv(&mut self) -> CH7OCV_W

Bit 15 - Channel 7 Software Output Control Value

impl W<u32, Reg<u32, _PWMLOAD>>

pub fn ch0sel(&mut self) -> CH0SEL_W

Bit 0 - Channel 0 Select

pub fn ch1sel(&mut self) -> CH1SEL_W

Bit 1 - Channel 1 Select

pub fn ch2sel(&mut self) -> CH2SEL_W

Bit 2 - Channel 2 Select

pub fn ch3sel(&mut self) -> CH3SEL_W

Bit 3 - Channel 3 Select

pub fn ch4sel(&mut self) -> CH4SEL_W

Bit 4 - Channel 4 Select

pub fn ch5sel(&mut self) -> CH5SEL_W

Bit 5 - Channel 5 Select

pub fn ch6sel(&mut self) -> CH6SEL_W

Bit 6 - Channel 6 Select

pub fn ch7sel(&mut self) -> CH7SEL_W

Bit 7 - Channel 7 Select

pub fn ldok(&mut self) -> LDOK_W

Bit 9 - Load Enable

impl W<u32, Reg<u32, _SC1>>

pub fn adch(&mut self) -> ADCH_W

Bits 0:4 - Input channel select

pub fn diff(&mut self) -> DIFF_W

Bit 5 - Differential Mode Enable

pub fn aien(&mut self) -> AIEN_W

Bit 6 - Interrupt Enable

impl W<u32, Reg<u32, _CFG1>>

pub fn adiclk(&mut self) -> ADICLK_W

Bits 0:1 - Input Clock Select

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Conversion mode selection

pub fn adlsmp(&mut self) -> ADLSMP_W

Bit 4 - Sample time configuration

pub fn adiv(&mut self) -> ADIV_W

Bits 5:6 - Clock Divide Select

pub fn adlpc(&mut self) -> ADLPC_W

Bit 7 - Low-Power Configuration

impl W<u32, Reg<u32, _CFG2>>

pub fn adlsts(&mut self) -> ADLSTS_W

Bits 0:1 - Long Sample Time Select

pub fn adhsc(&mut self) -> ADHSC_W

Bit 2 - High-Speed Configuration

pub fn adacken(&mut self) -> ADACKEN_W

Bit 3 - Asynchronous Clock Output Enable

pub fn muxsel(&mut self) -> MUXSEL_W

Bit 4 - ADC Mux Select

impl W<u32, Reg<u32, _CV>>

pub fn cv(&mut self) -> CV_W

Bits 0:15 - Compare Value.

impl W<u32, Reg<u32, _SC2>>

pub fn refsel(&mut self) -> REFSEL_W

Bits 0:1 - Voltage Reference Selection

pub fn dmaen(&mut self) -> DMAEN_W

Bit 2 - DMA Enable

pub fn acren(&mut self) -> ACREN_W

Bit 3 - Compare Function Range Enable

pub fn acfgt(&mut self) -> ACFGT_W

Bit 4 - Compare Function Greater Than Enable

pub fn acfe(&mut self) -> ACFE_W

Bit 5 - Compare Function Enable

pub fn adtrg(&mut self) -> ADTRG_W

Bit 6 - Conversion Trigger Select

impl W<u32, Reg<u32, _SC3>>

pub fn avgs(&mut self) -> AVGS_W

Bits 0:1 - Hardware Average Select

pub fn avge(&mut self) -> AVGE_W

Bit 2 - Hardware Average Enable

pub fn adco(&mut self) -> ADCO_W

Bit 3 - Continuous Conversion Enable

pub fn calf(&mut self) -> CALF_W

Bit 6 - Calibration Failed Flag

pub fn cal(&mut self) -> CAL_W

Bit 7 - Calibration

impl W<u32, Reg<u32, _OFS>>

pub fn ofs(&mut self) -> OFS_W

Bits 0:15 - Offset Error Correction Value

impl W<u32, Reg<u32, _PG>>

pub fn pg(&mut self) -> PG_W

Bits 0:15 - Plus-Side Gain

impl W<u32, Reg<u32, _MG>>

pub fn mg(&mut self) -> MG_W

Bits 0:15 - Minus-Side Gain

impl W<u32, Reg<u32, _CLPD>>

pub fn clpd(&mut self) -> CLPD_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLPS>>

pub fn clps(&mut self) -> CLPS_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLP4>>

pub fn clp4(&mut self) -> CLP4_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP3>>

pub fn clp3(&mut self) -> CLP3_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLP2>>

pub fn clp2(&mut self) -> CLP2_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLP1>>

pub fn clp1(&mut self) -> CLP1_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP0>>

pub fn clp0(&mut self) -> CLP0_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLMD>>

pub fn clmd(&mut self) -> CLMD_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLMS>>

pub fn clms(&mut self) -> CLMS_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLM4>>

pub fn clm4(&mut self) -> CLM4_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLM3>>

pub fn clm3(&mut self) -> CLM3_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLM2>>

pub fn clm2(&mut self) -> CLM2_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLM1>>

pub fn clm1(&mut self) -> CLM1_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLM0>>

pub fn clm0(&mut self) -> CLM0_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _SC1>>

pub fn adch(&mut self) -> ADCH_W

Bits 0:4 - Input channel select

pub fn diff(&mut self) -> DIFF_W

Bit 5 - Differential Mode Enable

pub fn aien(&mut self) -> AIEN_W

Bit 6 - Interrupt Enable

impl W<u32, Reg<u32, _CFG1>>

pub fn adiclk(&mut self) -> ADICLK_W

Bits 0:1 - Input Clock Select

pub fn mode(&mut self) -> MODE_W

Bits 2:3 - Conversion mode selection

pub fn adlsmp(&mut self) -> ADLSMP_W

Bit 4 - Sample time configuration

pub fn adiv(&mut self) -> ADIV_W

Bits 5:6 - Clock Divide Select

pub fn adlpc(&mut self) -> ADLPC_W

Bit 7 - Low-Power Configuration

impl W<u32, Reg<u32, _CFG2>>

pub fn adlsts(&mut self) -> ADLSTS_W

Bits 0:1 - Long Sample Time Select

pub fn adhsc(&mut self) -> ADHSC_W

Bit 2 - High-Speed Configuration

pub fn adacken(&mut self) -> ADACKEN_W

Bit 3 - Asynchronous Clock Output Enable

pub fn muxsel(&mut self) -> MUXSEL_W

Bit 4 - ADC Mux Select

impl W<u32, Reg<u32, _CV>>

pub fn cv(&mut self) -> CV_W

Bits 0:15 - Compare Value.

impl W<u32, Reg<u32, _SC2>>

pub fn refsel(&mut self) -> REFSEL_W

Bits 0:1 - Voltage Reference Selection

pub fn dmaen(&mut self) -> DMAEN_W

Bit 2 - DMA Enable

pub fn acren(&mut self) -> ACREN_W

Bit 3 - Compare Function Range Enable

pub fn acfgt(&mut self) -> ACFGT_W

Bit 4 - Compare Function Greater Than Enable

pub fn acfe(&mut self) -> ACFE_W

Bit 5 - Compare Function Enable

pub fn adtrg(&mut self) -> ADTRG_W

Bit 6 - Conversion Trigger Select

impl W<u32, Reg<u32, _SC3>>

pub fn avgs(&mut self) -> AVGS_W

Bits 0:1 - Hardware Average Select

pub fn avge(&mut self) -> AVGE_W

Bit 2 - Hardware Average Enable

pub fn adco(&mut self) -> ADCO_W

Bit 3 - Continuous Conversion Enable

pub fn calf(&mut self) -> CALF_W

Bit 6 - Calibration Failed Flag

pub fn cal(&mut self) -> CAL_W

Bit 7 - Calibration

impl W<u32, Reg<u32, _OFS>>

pub fn ofs(&mut self) -> OFS_W

Bits 0:15 - Offset Error Correction Value

impl W<u32, Reg<u32, _PG>>

pub fn pg(&mut self) -> PG_W

Bits 0:15 - Plus-Side Gain

impl W<u32, Reg<u32, _MG>>

pub fn mg(&mut self) -> MG_W

Bits 0:15 - Minus-Side Gain

impl W<u32, Reg<u32, _CLPD>>

pub fn clpd(&mut self) -> CLPD_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLPS>>

pub fn clps(&mut self) -> CLPS_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLP4>>

pub fn clp4(&mut self) -> CLP4_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLP3>>

pub fn clp3(&mut self) -> CLP3_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLP2>>

pub fn clp2(&mut self) -> CLP2_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLP1>>

pub fn clp1(&mut self) -> CLP1_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLP0>>

pub fn clp0(&mut self) -> CLP0_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLMD>>

pub fn clmd(&mut self) -> CLMD_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLMS>>

pub fn clms(&mut self) -> CLMS_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _CLM4>>

pub fn clm4(&mut self) -> CLM4_W

Bits 0:9 - Calibration Value

impl W<u32, Reg<u32, _CLM3>>

pub fn clm3(&mut self) -> CLM3_W

Bits 0:8 - Calibration Value

impl W<u32, Reg<u32, _CLM2>>

pub fn clm2(&mut self) -> CLM2_W

Bits 0:7 - Calibration Value

impl W<u32, Reg<u32, _CLM1>>

pub fn clm1(&mut self) -> CLM1_W

Bits 0:6 - Calibration Value

impl W<u32, Reg<u32, _CLM0>>

pub fn clm0(&mut self) -> CLM0_W

Bits 0:5 - Calibration Value

impl W<u32, Reg<u32, _TSR>>

pub fn tsr(&mut self) -> TSR_W

Bits 0:31 - Time Seconds Register

impl W<u32, Reg<u32, _TPR>>

pub fn tpr(&mut self) -> TPR_W

Bits 0:15 - Time Prescaler Register

impl W<u32, Reg<u32, _TAR>>

pub fn tar(&mut self) -> TAR_W

Bits 0:31 - Time Alarm Register

impl W<u32, Reg<u32, _TCR>>

pub fn tcr(&mut self) -> TCR_W

Bits 0:7 - Time Compensation Register

pub fn cir(&mut self) -> CIR_W

Bits 8:15 - Compensation Interval Register

impl W<u32, Reg<u32, _CR>>

pub fn swr(&mut self) -> SWR_W

Bit 0 - Software Reset

pub fn wpe(&mut self) -> WPE_W

Bit 1 - Wakeup Pin Enable

pub fn sup(&mut self) -> SUP_W

Bit 2 - Supervisor Access

pub fn um(&mut self) -> UM_W

Bit 3 - Update Mode

pub fn wps(&mut self) -> WPS_W

Bit 4 - Wakeup Pin Select

pub fn osce(&mut self) -> OSCE_W

Bit 8 - Oscillator Enable

pub fn clko(&mut self) -> CLKO_W

Bit 9 - Clock Output

pub fn sc16p(&mut self) -> SC16P_W

Bit 10 - Oscillator 16pF Load Configure

pub fn sc8p(&mut self) -> SC8P_W

Bit 11 - Oscillator 8pF Load Configure

pub fn sc4p(&mut self) -> SC4P_W

Bit 12 - Oscillator 4pF Load Configure

pub fn sc2p(&mut self) -> SC2P_W

Bit 13 - Oscillator 2pF Load Configure

impl W<u32, Reg<u32, _SR>>

pub fn tce(&mut self) -> TCE_W

Bit 4 - Time Counter Enable

impl W<u32, Reg<u32, _LR>>

pub fn tcl(&mut self) -> TCL_W

Bit 3 - Time Compensation Lock

pub fn crl(&mut self) -> CRL_W

Bit 4 - Control Register Lock

pub fn srl(&mut self) -> SRL_W

Bit 5 - Status Register Lock

pub fn lrl(&mut self) -> LRL_W

Bit 6 - Lock Register Lock

pub fn ttsl(&mut self) -> TTSL_W

Bit 8 - Tamper Time Seconds Lock

pub fn mel(&mut self) -> MEL_W

Bit 9 - Monotonic Enable Lock

pub fn mcll(&mut self) -> MCLL_W

Bit 10 - Monotonic Counter Low Lock

pub fn mchl(&mut self) -> MCHL_W

Bit 11 - Monotonic Counter High Lock

impl W<u32, Reg<u32, _IER>>

pub fn tiie(&mut self) -> TIIE_W

Bit 0 - Time Invalid Interrupt Enable

pub fn toie(&mut self) -> TOIE_W

Bit 1 - Time Overflow Interrupt Enable

pub fn taie(&mut self) -> TAIE_W

Bit 2 - Time Alarm Interrupt Enable

pub fn moie(&mut self) -> MOIE_W

Bit 3 - Monotonic Overflow Interrupt Enable

pub fn tsie(&mut self) -> TSIE_W

Bit 4 - Time Seconds Interrupt Enable

pub fn wpon(&mut self) -> WPON_W

Bit 7 - Wakeup Pin On

impl W<u32, Reg<u32, _MER>>

pub fn mce(&mut self) -> MCE_W

Bit 4 - Monotonic Counter Enable

impl W<u32, Reg<u32, _MCLR>>

pub fn mcl(&mut self) -> MCL_W

Bits 0:31 - Monotonic Counter Low

impl W<u32, Reg<u32, _MCHR>>

pub fn mch(&mut self) -> MCH_W

Bits 0:31 - Monotonic Counter High

impl W<u32, Reg<u32, _WAR>>

pub fn tsrw(&mut self) -> TSRW_W

Bit 0 - Time Seconds Register Write

pub fn tprw(&mut self) -> TPRW_W

Bit 1 - Time Prescaler Register Write

pub fn tarw(&mut self) -> TARW_W

Bit 2 - Time Alarm Register Write

pub fn tcrw(&mut self) -> TCRW_W

Bit 3 - Time Compensation Register Write

pub fn crw(&mut self) -> CRW_W

Bit 4 - Control Register Write

pub fn srw(&mut self) -> SRW_W

Bit 5 - Status Register Write

pub fn lrw(&mut self) -> LRW_W

Bit 6 - Lock Register Write

pub fn ierw(&mut self) -> IERW_W

Bit 7 - Interrupt Enable Register Write

pub fn ttsw(&mut self) -> TTSW_W

Bit 8 - Tamper Time Seconds Write

pub fn merw(&mut self) -> MERW_W

Bit 9 - Monotonic Enable Register Write

pub fn mclw(&mut self) -> MCLW_W

Bit 10 - Monotonic Counter Low Write

pub fn mchw(&mut self) -> MCHW_W

Bit 11 - Monotonic Counter High Write

impl W<u32, Reg<u32, _RAR>>

pub fn tsrr(&mut self) -> TSRR_W

Bit 0 - Time Seconds Register Read

pub fn tprr(&mut self) -> TPRR_W

Bit 1 - Time Prescaler Register Read

pub fn tarr(&mut self) -> TARR_W

Bit 2 - Time Alarm Register Read

pub fn tcrr(&mut self) -> TCRR_W

Bit 3 - Time Compensation Register Read

pub fn crr(&mut self) -> CRR_W

Bit 4 - Control Register Read

pub fn srr(&mut self) -> SRR_W

Bit 5 - Status Register Read

pub fn lrr(&mut self) -> LRR_W

Bit 6 - Lock Register Read

pub fn ierr(&mut self) -> IERR_W

Bit 7 - Interrupt Enable Register Read

pub fn ttsr(&mut self) -> TTSR_W

Bit 8 - Tamper Time Seconds Read

pub fn merr(&mut self) -> MERR_W

Bit 9 - Monotonic Enable Register Read

pub fn mclr(&mut self) -> MCLR_W

Bit 10 - Monotonic Counter Low Read

pub fn mchr(&mut self) -> MCHR_W

Bit 11 - Monotonic Counter High Read

impl W<u32, Reg<u32, _REG>>

pub fn ll(&mut self) -> LL_W

Bits 0:7 - Low lower byte

pub fn lh(&mut self) -> LH_W

Bits 8:15 - Low higher byte

pub fn hl(&mut self) -> HL_W

Bits 16:23 - High lower byte

pub fn hh(&mut self) -> HH_W

Bits 24:31 - High higher byte

impl W<u32, Reg<u32, _CSR>>

pub fn ten(&mut self) -> TEN_W

Bit 0 - Timer Enable

pub fn tms(&mut self) -> TMS_W

Bit 1 - Timer Mode Select

pub fn tfc(&mut self) -> TFC_W

Bit 2 - Timer Free-Running Counter

pub fn tpp(&mut self) -> TPP_W

Bit 3 - Timer Pin Polarity

pub fn tps(&mut self) -> TPS_W

Bits 4:5 - Timer Pin Select

pub fn tie(&mut self) -> TIE_W

Bit 6 - Timer Interrupt Enable

pub fn tcf(&mut self) -> TCF_W

Bit 7 - Timer Compare Flag

impl W<u32, Reg<u32, _PSR>>

pub fn pcs(&mut self) -> PCS_W

Bits 0:1 - Prescaler Clock Select

pub fn pbyp(&mut self) -> PBYP_W

Bit 2 - Prescaler Bypass

pub fn prescale(&mut self) -> PRESCALE_W

Bits 3:6 - Prescale Value

impl W<u32, Reg<u32, _CMR>>

pub fn compare(&mut self) -> COMPARE_W

Bits 0:15 - Compare Value

impl W<u32, Reg<u32, _CNR>>

pub fn counter(&mut self) -> COUNTER_W

Bits 0:15 - Counter Value

impl W<u32, Reg<u32, _REG>>

pub fn ll(&mut self) -> LL_W

Bits 0:7 - Low lower byte

pub fn lh(&mut self) -> LH_W

Bits 8:15 - Low higher byte

pub fn hl(&mut self) -> HL_W

Bits 16:23 - High lower byte

pub fn hh(&mut self) -> HH_W

Bits 24:31 - High higher byte

impl W<u32, Reg<u32, _SOPT1>>

pub fn osc32ksel(&mut self) -> OSC32KSEL_W

Bits 18:19 - 32K oscillator clock select

pub fn usbvstby(&mut self) -> USBVSTBY_W

Bit 29 - USB voltage regulator in standby mode during VLPR and VLPW modes

pub fn usbsstby(&mut self) -> USBSSTBY_W

Bit 30 - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.

pub fn usbregen(&mut self) -> USBREGEN_W

Bit 31 - USB voltage regulator enable

impl W<u32, Reg<u32, _SOPT1CFG>>

pub fn urwe(&mut self) -> URWE_W

Bit 24 - USB voltage regulator enable write enable

pub fn uvswe(&mut self) -> UVSWE_W

Bit 25 - USB voltage regulator VLP standby write enable

pub fn usswe(&mut self) -> USSWE_W

Bit 26 - USB voltage regulator stop standby write enable

impl W<u32, Reg<u32, _SOPT2>>

pub fn rtcclkoutsel(&mut self) -> RTCCLKOUTSEL_W

Bit 4 - RTC clock out select

pub fn clkoutsel(&mut self) -> CLKOUTSEL_W

Bits 5:7 - CLKOUT select

pub fn fbsl(&mut self) -> FBSL_W

Bits 8:9 - FlexBus security level

pub fn ptd7pad(&mut self) -> PTD7PAD_W

Bit 11 - PTD7 pad drive strength

pub fn traceclksel(&mut self) -> TRACECLKSEL_W

Bit 12 - Debug trace clock select

pub fn pllfllsel(&mut self) -> PLLFLLSEL_W

Bit 16 - PLL/FLL clock select

pub fn usbsrc(&mut self) -> USBSRC_W

Bit 18 - USB clock source select

impl W<u32, Reg<u32, _SOPT4>>

pub fn ftm0flt0(&mut self) -> FTM0FLT0_W

Bit 0 - FTM0 Fault 0 Select

pub fn ftm0flt1(&mut self) -> FTM0FLT1_W

Bit 1 - FTM0 Fault 1 Select

pub fn ftm0flt2(&mut self) -> FTM0FLT2_W

Bit 2 - FTM0 Fault 2 Select

pub fn ftm1flt0(&mut self) -> FTM1FLT0_W

Bit 4 - FTM1 Fault 0 Select

pub fn ftm2flt0(&mut self) -> FTM2FLT0_W

Bit 8 - FTM2 Fault 0 Select

pub fn ftm3flt0(&mut self) -> FTM3FLT0_W

Bit 12 - FTM3 Fault 0 Select

pub fn ftm1ch0src(&mut self) -> FTM1CH0SRC_W

Bits 18:19 - FTM1 channel 0 input capture source select

pub fn ftm2ch0src(&mut self) -> FTM2CH0SRC_W

Bits 20:21 - FTM2 channel 0 input capture source select

pub fn ftm0clksel(&mut self) -> FTM0CLKSEL_W

Bit 24 - FlexTimer 0 External Clock Pin Select

pub fn ftm1clksel(&mut self) -> FTM1CLKSEL_W

Bit 25 - FTM1 External Clock Pin Select

pub fn ftm2clksel(&mut self) -> FTM2CLKSEL_W

Bit 26 - FlexTimer 2 External Clock Pin Select

pub fn ftm3clksel(&mut self) -> FTM3CLKSEL_W

Bit 27 - FlexTimer 3 External Clock Pin Select

pub fn ftm0trg0src(&mut self) -> FTM0TRG0SRC_W

Bit 28 - FlexTimer 0 Hardware Trigger 0 Source Select

pub fn ftm0trg1src(&mut self) -> FTM0TRG1SRC_W

Bit 29 - FlexTimer 0 Hardware Trigger 1 Source Select

pub fn ftm3trg0src(&mut self) -> FTM3TRG0SRC_W

Bit 30 - FlexTimer 3 Hardware Trigger 0 Source Select

pub fn ftm3trg1src(&mut self) -> FTM3TRG1SRC_W

Bit 31 - FlexTimer 3 Hardware Trigger 1 Source Select

impl W<u32, Reg<u32, _SOPT5>>

pub fn uart0txsrc(&mut self) -> UART0TXSRC_W

Bits 0:1 - UART 0 transmit data source select

pub fn uart0rxsrc(&mut self) -> UART0RXSRC_W

Bits 2:3 - UART 0 receive data source select

pub fn uart1txsrc(&mut self) -> UART1TXSRC_W

Bits 4:5 - UART 1 transmit data source select

pub fn uart1rxsrc(&mut self) -> UART1RXSRC_W

Bits 6:7 - UART 1 receive data source select

impl W<u32, Reg<u32, _SOPT7>>

pub fn adc0trgsel(&mut self) -> ADC0TRGSEL_W

Bits 0:3 - ADC0 trigger select

pub fn adc0pretrgsel(&mut self) -> ADC0PRETRGSEL_W

Bit 4 - ADC0 pretrigger select

pub fn adc0alttrgen(&mut self) -> ADC0ALTTRGEN_W

Bit 7 - ADC0 alternate trigger enable

pub fn adc1trgsel(&mut self) -> ADC1TRGSEL_W

Bits 8:11 - ADC1 trigger select

pub fn adc1pretrgsel(&mut self) -> ADC1PRETRGSEL_W

Bit 12 - ADC1 pre-trigger select

pub fn adc1alttrgen(&mut self) -> ADC1ALTTRGEN_W

Bit 15 - ADC1 alternate trigger enable

impl W<u32, Reg<u32, _SCGC1>>

pub fn i2c2(&mut self) -> I2C2_W

Bit 6 - I2C2 Clock Gate Control

impl W<u32, Reg<u32, _SCGC2>>

pub fn dac0(&mut self) -> DAC0_W

Bit 12 - DAC0 Clock Gate Control

impl W<u32, Reg<u32, _SCGC3>>

pub fn ftm2(&mut self) -> FTM2_W

Bit 24 - FTM2 Clock Gate Control

pub fn ftm3(&mut self) -> FTM3_W

Bit 25 - FTM3 Clock Gate Control

pub fn adc1(&mut self) -> ADC1_W

Bit 27 - ADC1 Clock Gate Control

impl W<u32, Reg<u32, _SCGC4>>

pub fn ewm(&mut self) -> EWM_W

Bit 1 - EWM Clock Gate Control

pub fn cmt(&mut self) -> CMT_W

Bit 2 - CMT Clock Gate Control

pub fn i2c0(&mut self) -> I2C0_W

Bit 6 - I2C0 Clock Gate Control

pub fn i2c1(&mut self) -> I2C1_W

Bit 7 - I2C1 Clock Gate Control

pub fn uart0(&mut self) -> UART0_W

Bit 10 - UART0 Clock Gate Control

pub fn uart1(&mut self) -> UART1_W

Bit 11 - UART1 Clock Gate Control

pub fn uart2(&mut self) -> UART2_W

Bit 12 - UART2 Clock Gate Control

pub fn usbotg(&mut self) -> USBOTG_W

Bit 18 - USB Clock Gate Control

pub fn cmp(&mut self) -> CMP_W

Bit 19 - Comparator Clock Gate Control

pub fn vref(&mut self) -> VREF_W

Bit 20 - VREF Clock Gate Control

impl W<u32, Reg<u32, _SCGC5>>

pub fn lptmr(&mut self) -> LPTMR_W

Bit 0 - Low Power Timer Access Control

pub fn porta(&mut self) -> PORTA_W

Bit 9 - Port A Clock Gate Control

pub fn portb(&mut self) -> PORTB_W

Bit 10 - Port B Clock Gate Control

pub fn portc(&mut self) -> PORTC_W

Bit 11 - Port C Clock Gate Control

pub fn portd(&mut self) -> PORTD_W

Bit 12 - Port D Clock Gate Control

pub fn porte(&mut self) -> PORTE_W

Bit 13 - Port E Clock Gate Control

impl W<u32, Reg<u32, _SCGC6>>

pub fn ftf(&mut self) -> FTF_W

Bit 0 - Flash Memory Clock Gate Control

pub fn dmamux(&mut self) -> DMAMUX_W

Bit 1 - DMA Mux Clock Gate Control

pub fn flexcan0(&mut self) -> FLEXCAN0_W

Bit 4 - FlexCAN0 Clock Gate Control

pub fn spi0(&mut self) -> SPI0_W

Bit 12 - SPI0 Clock Gate Control

pub fn i2s(&mut self) -> I2S_W

Bit 15 - I2S Clock Gate Control

pub fn crc(&mut self) -> CRC_W

Bit 18 - CRC Clock Gate Control

pub fn usbdcd(&mut self) -> USBDCD_W

Bit 21 - USB DCD Clock Gate Control

pub fn pdb(&mut self) -> PDB_W

Bit 22 - PDB Clock Gate Control

pub fn pit(&mut self) -> PIT_W

Bit 23 - PIT Clock Gate Control

pub fn ftm0(&mut self) -> FTM0_W

Bit 24 - FTM0 Clock Gate Control

pub fn ftm1(&mut self) -> FTM1_W

Bit 25 - FTM1 Clock Gate Control

pub fn ftm2(&mut self) -> FTM2_W

Bit 26 - FTM2 Clock Gate Control

pub fn adc0(&mut self) -> ADC0_W

Bit 27 - ADC0 Clock Gate Control

pub fn rtc(&mut self) -> RTC_W

Bit 29 - RTC Access Control

pub fn dac0(&mut self) -> DAC0_W

Bit 31 - DAC0 Clock Gate Control

impl W<u32, Reg<u32, _SCGC7>>

pub fn flexbus(&mut self) -> FLEXBUS_W

Bit 0 - FlexBus Clock Gate Control

pub fn dma(&mut self) -> DMA_W

Bit 1 - DMA Clock Gate Control

pub fn mpu(&mut self) -> MPU_W

Bit 2 - MPU Clock Gate Control

impl W<u32, Reg<u32, _CLKDIV1>>

pub fn outdiv4(&mut self) -> OUTDIV4_W

Bits 16:19 - Clock 4 output divider value

pub fn outdiv3(&mut self) -> OUTDIV3_W

Bits 20:23 - Clock 3 output divider value

pub fn outdiv2(&mut self) -> OUTDIV2_W

Bits 24:27 - Clock 2 output divider value

pub fn outdiv1(&mut self) -> OUTDIV1_W

Bits 28:31 - Clock 1 output divider value

impl W<u32, Reg<u32, _CLKDIV2>>

pub fn usbfrac(&mut self) -> USBFRAC_W

Bit 0 - USB clock divider fraction

pub fn usbdiv(&mut self) -> USBDIV_W

Bits 1:3 - USB clock divider divisor

impl W<u32, Reg<u32, _FCFG1>>

pub fn flashdis(&mut self) -> FLASHDIS_W

Bit 0 - Flash Disable

pub fn flashdoze(&mut self) -> FLASHDOZE_W

Bit 1 - Flash Doze

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u32, Reg<u32, _DFER>>

pub fn dfe(&mut self) -> DFE_W

Bits 0:31 - Digital Filter Enable

impl W<u32, Reg<u32, _DFCR>>

pub fn cs(&mut self) -> CS_W

Bit 0 - Clock Source

impl W<u32, Reg<u32, _DFWR>>

pub fn filt(&mut self) -> FILT_W

Bits 0:4 - Filter Length

impl W<u32, Reg<u32, _PCR0>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR1>>

pub fn ps(&mut self) -> PS_W

Bit 0 - Pull Select

pub fn pe(&mut self) -> PE_W

Bit 1 - Pull Enable

pub fn sre(&mut self) -> SRE_W

Bit 2 - Slew Rate Enable

pub fn pfe(&mut self) -> PFE_W

Bit 4 - Passive Filter Enable

pub fn ode(&mut self) -> ODE_W

Bit 5 - Open Drain Enable

pub fn dse(&mut self) -> DSE_W

Bit 6 - Drive Strength Enable

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR2>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR3>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR4>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR5>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR6>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR7>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR8>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR9>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR10>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR11>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR12>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR13>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR14>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR15>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR16>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR17>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR18>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR19>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR20>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR21>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR22>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR23>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR24>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR25>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR26>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR27>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR28>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR29>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR30>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _PCR31>>

pub fn mux(&mut self) -> MUX_W

Bits 8:10 - Pin Mux Control

pub fn lk(&mut self) -> LK_W

Bit 15 - Lock Register

pub fn irqc(&mut self) -> IRQC_W

Bits 16:19 - Interrupt Configuration

pub fn isf(&mut self) -> ISF_W

Bit 24 - Interrupt Status Flag

impl W<u32, Reg<u32, _GPCLR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _GPCHR>>

pub fn gpwd(&mut self) -> GPWD_W

Bits 0:15 - Global Pin Write Data

pub fn gpwe(&mut self) -> GPWE_W

Bits 16:31 - Global Pin Write Enable

impl W<u32, Reg<u32, _ISFR>>

pub fn isf(&mut self) -> ISF_W

Bits 0:31 - Interrupt Status Flag

impl W<u16, Reg<u16, _STCTRLH>>

pub fn wdogen(&mut self) -> WDOGEN_W

Bit 0 - Enables or disables the WDOG's operation

pub fn clksrc(&mut self) -> CLKSRC_W

Bit 1 - Selects clock source for the WDOG timer and other internal timing operations.

pub fn irqrsten(&mut self) -> IRQRSTEN_W

Bit 2 - Used to enable the debug breadcrumbs feature

pub fn winen(&mut self) -> WINEN_W

Bit 3 - Enables Windowing mode.

pub fn allowupdate(&mut self) -> ALLOWUPDATE_W

Bit 4 - Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window (WCT) closes, through unlock sequence

pub fn dbgen(&mut self) -> DBGEN_W

Bit 5 - Enables or disables WDOG in Debug mode.

pub fn stopen(&mut self) -> STOPEN_W

Bit 6 - Enables or disables WDOG in Stop mode.

pub fn waiten(&mut self) -> WAITEN_W

Bit 7 - Enables or disables WDOG in Wait mode.

pub fn testwdog(&mut self) -> TESTWDOG_W

Bit 10 - Puts the watchdog in the functional test mode

pub fn testsel(&mut self) -> TESTSEL_W

Bit 11 - Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer.

pub fn bytesel(&mut self) -> BYTESEL_W

Bits 12:13 - This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode.

pub fn distestwdog(&mut self) -> DISTESTWDOG_W

Bit 14 - Allows the WDOG's functional test mode to be disabled permanently

impl W<u16, Reg<u16, _STCTRLL>>

pub fn intflg(&mut self) -> INTFLG_W

Bit 15 - Interrupt flag

impl W<u16, Reg<u16, _TOVALH>>

pub fn tovalhigh(&mut self) -> TOVALHIGH_W

Bits 0:15 - Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer

impl W<u16, Reg<u16, _TOVALL>>

pub fn tovallow(&mut self) -> TOVALLOW_W

Bits 0:15 - Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer

impl W<u16, Reg<u16, _WINH>>

pub fn winhigh(&mut self) -> WINHIGH_W

Bits 0:15 - Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog

impl W<u16, Reg<u16, _WINL>>

pub fn winlow(&mut self) -> WINLOW_W

Bits 0:15 - Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog

impl W<u16, Reg<u16, _REFRESH>>

pub fn wdogrefresh(&mut self) -> WDOGREFRESH_W

Bits 0:15 - Watchdog refresh register

impl W<u16, Reg<u16, _UNLOCK>>

pub fn wdogunlock(&mut self) -> WDOGUNLOCK_W

Bits 0:15 - Writing the unlock sequence values to this register to makes the watchdog write-once registers writable again

impl W<u16, Reg<u16, _TMROUTH>>

pub fn timerouthigh(&mut self) -> TIMEROUTHIGH_W

Bits 0:15 - Shows the value of the upper 16 bits of the watchdog timer.

impl W<u16, Reg<u16, _TMROUTL>>

pub fn timeroutlow(&mut self) -> TIMEROUTLOW_W

Bits 0:15 - Shows the value of the lower 16 bits of the watchdog timer.

impl W<u16, Reg<u16, _RSTCNT>>

pub fn rstcnt(&mut self) -> RSTCNT_W

Bits 0:15 - Counts the number of times the watchdog resets the system

impl W<u16, Reg<u16, _PRESC>>

pub fn prescval(&mut self) -> PRESCVAL_W

Bits 8:10 - 3-bit prescaler for the watchdog clock source

impl W<u8, Reg<u8, _CTRL>>

pub fn ewmen(&mut self) -> EWMEN_W

Bit 0 - EWM enable.

pub fn assin(&mut self) -> ASSIN_W

Bit 1 - EWM_in's Assertion State Select.

pub fn inen(&mut self) -> INEN_W

Bit 2 - Input Enable.

pub fn inten(&mut self) -> INTEN_W

Bit 3 - Interrupt Enable.

impl W<u8, Reg<u8, _SERV>>

pub fn service(&mut self) -> SERVICE_W

Bits 0:7 - The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C

impl W<u8, Reg<u8, _CMPL>>

pub fn comparel(&mut self) -> COMPAREL_W

Bits 0:7 - To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required

impl W<u8, Reg<u8, _CMPH>>

pub fn compareh(&mut self) -> COMPAREH_W

Bits 0:7 - To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required

impl W<u8, Reg<u8, _CGH1>>

pub fn ph(&mut self) -> PH_W

Bits 0:7 - Primary Carrier High Time Data Value

impl W<u8, Reg<u8, _CGL1>>

pub fn pl(&mut self) -> PL_W

Bits 0:7 - Primary Carrier Low Time Data Value

impl W<u8, Reg<u8, _CGH2>>

pub fn sh(&mut self) -> SH_W

Bits 0:7 - Secondary Carrier High Time Data Value

impl W<u8, Reg<u8, _CGL2>>

pub fn sl(&mut self) -> SL_W

Bits 0:7 - Secondary Carrier Low Time Data Value

impl W<u8, Reg<u8, _OC>>

pub fn iropen(&mut self) -> IROPEN_W

Bit 5 - IRO Pin Enable

pub fn cmtpol(&mut self) -> CMTPOL_W

Bit 6 - CMT Output Polarity

pub fn irol(&mut self) -> IROL_W

Bit 7 - IRO Latch Control

impl W<u8, Reg<u8, _MSC>>

pub fn mcgen(&mut self) -> MCGEN_W

Bit 0 - Modulator and Carrier Generator Enable

pub fn eocie(&mut self) -> EOCIE_W

Bit 1 - End of Cycle Interrupt Enable

pub fn fsk(&mut self) -> FSK_W

Bit 2 - FSK Mode Select

pub fn base(&mut self) -> BASE_W

Bit 3 - Baseband Enable

pub fn exspc(&mut self) -> EXSPC_W

Bit 4 - Extended Space Enable

pub fn cmtdiv(&mut self) -> CMTDIV_W

Bits 5:6 - CMT Clock Divide Prescaler

impl W<u8, Reg<u8, _CMD1>>

pub fn mb(&mut self) -> MB_W

Bits 0:7 - Controls the upper mark periods of the modulator for all modes.

impl W<u8, Reg<u8, _CMD2>>

pub fn mb(&mut self) -> MB_W

Bits 0:7 - Controls the lower mark periods of the modulator for all modes.

impl W<u8, Reg<u8, _CMD3>>

pub fn sb(&mut self) -> SB_W

Bits 0:7 - Controls the upper space periods of the modulator for all modes.

impl W<u8, Reg<u8, _CMD4>>

pub fn sb(&mut self) -> SB_W

Bits 0:7 - Controls the lower space periods of the modulator for all modes.

impl W<u8, Reg<u8, _PPS>>

pub fn ppsdiv(&mut self) -> PPSDIV_W

Bits 0:3 - Primary Prescaler Divider

impl W<u8, Reg<u8, _DMA>>

pub fn dma(&mut self) -> DMA_W

Bit 0 - DMA Enable

impl W<u8, Reg<u8, _C1>>

pub fn irefsten(&mut self) -> IREFSTEN_W

Bit 0 - Internal Reference Stop Enable

pub fn irclken(&mut self) -> IRCLKEN_W

Bit 1 - Internal Reference Clock Enable

pub fn irefs(&mut self) -> IREFS_W

Bit 2 - Internal Reference Select

pub fn frdiv(&mut self) -> FRDIV_W

Bits 3:5 - FLL External Reference Divider

pub fn clks(&mut self) -> CLKS_W

Bits 6:7 - Clock Source Select

impl W<u8, Reg<u8, _C2>>

pub fn ircs(&mut self) -> IRCS_W

Bit 0 - Internal Reference Clock Select

pub fn lp(&mut self) -> LP_W

Bit 1 - Low Power Select

pub fn erefs0(&mut self) -> EREFS0_W

Bit 2 - External Reference Select

pub fn hgo0(&mut self) -> HGO0_W

Bit 3 - High Gain Oscillator Select

pub fn range0(&mut self) -> RANGE0_W

Bits 4:5 - Frequency Range Select

pub fn locre0(&mut self) -> LOCRE0_W

Bit 7 - Loss of Clock Reset Enable

impl W<u8, Reg<u8, _C3>>

pub fn sctrim(&mut self) -> SCTRIM_W

Bits 0:7 - Slow Internal Reference Clock Trim Setting

impl W<u8, Reg<u8, _C4>>

pub fn scftrim(&mut self) -> SCFTRIM_W

Bit 0 - Slow Internal Reference Clock Fine Trim

pub fn fctrim(&mut self) -> FCTRIM_W

Bits 1:4 - Fast Internal Reference Clock Trim Setting

pub fn drst_drs(&mut self) -> DRST_DRS_W

Bits 5:6 - DCO Range Select

pub fn dmx32(&mut self) -> DMX32_W

Bit 7 - DCO Maximum Frequency with 32.768 kHz Reference

impl W<u8, Reg<u8, _C5>>

pub fn prdiv0(&mut self) -> PRDIV0_W

Bits 0:4 - PLL External Reference Divider

pub fn pllsten0(&mut self) -> PLLSTEN0_W

Bit 5 - PLL Stop Enable

pub fn pllclken0(&mut self) -> PLLCLKEN0_W

Bit 6 - PLL Clock Enable

impl W<u8, Reg<u8, _C6>>

pub fn vdiv0(&mut self) -> VDIV0_W

Bits 0:4 - VCO 0 Divider

pub fn cme0(&mut self) -> CME0_W

Bit 5 - Clock Monitor Enable

pub fn plls(&mut self) -> PLLS_W

Bit 6 - PLL Select

pub fn lolie0(&mut self) -> LOLIE0_W

Bit 7 - Loss of Lock Interrrupt Enable

impl W<u8, Reg<u8, _S>>

pub fn lols(&mut self) -> LOLS_W

Bit 7 - Loss of Lock Status

impl W<u8, Reg<u8, _SC>>

pub fn locs0(&mut self) -> LOCS0_W

Bit 0 - OSC0 Loss of Clock Status

pub fn fcrdiv(&mut self) -> FCRDIV_W

Bits 1:3 - Fast Clock Internal Reference Divider

pub fn fltprsrv(&mut self) -> FLTPRSRV_W

Bit 4 - FLL Filter Preserve Enable

pub fn atmf(&mut self) -> ATMF_W

Bit 5 - Automatic Trim Machine Fail Flag

pub fn atms(&mut self) -> ATMS_W

Bit 6 - Automatic Trim Machine Select

pub fn atme(&mut self) -> ATME_W

Bit 7 - Automatic Trim Machine Enable

impl W<u8, Reg<u8, _ATCVH>>

pub fn atcvh(&mut self) -> ATCVH_W

Bits 0:7 - ATM Compare Value High

impl W<u8, Reg<u8, _ATCVL>>

pub fn atcvl(&mut self) -> ATCVL_W

Bits 0:7 - ATM Compare Value Low

impl W<u8, Reg<u8, _C7>>

pub fn oscsel(&mut self) -> OSCSEL_W

Bit 0 - MCG OSC Clock Select

impl W<u8, Reg<u8, _C8>>

pub fn locs1(&mut self) -> LOCS1_W

Bit 0 - RTC Loss of Clock Status

pub fn cme1(&mut self) -> CME1_W

Bit 5 - Clock Monitor Enable1

pub fn lolre(&mut self) -> LOLRE_W

Bit 6 - PLL Loss of Lock Reset Enable

pub fn locre1(&mut self) -> LOCRE1_W

Bit 7 - Loss of Clock Reset Enable

impl W<u8, Reg<u8, _CR>>

pub fn sc16p(&mut self) -> SC16P_W

Bit 0 - Oscillator 16 pF Capacitor Load Configure

pub fn sc8p(&mut self) -> SC8P_W

Bit 1 - Oscillator 8 pF Capacitor Load Configure

pub fn sc4p(&mut self) -> SC4P_W

Bit 2 - Oscillator 4 pF Capacitor Load Configure

pub fn sc2p(&mut self) -> SC2P_W

Bit 3 - Oscillator 2 pF Capacitor Load Configure

pub fn erefsten(&mut self) -> EREFSTEN_W

Bit 5 - External Reference Stop Enable

pub fn erclken(&mut self) -> ERCLKEN_W

Bit 7 - External Reference Enable

impl W<u8, Reg<u8, _A1>>

pub fn ad(&mut self) -> AD_W

Bits 1:7 - Address

impl W<u8, Reg<u8, _F>>

pub fn icr(&mut self) -> ICR_W

Bits 0:5 - ClockRate

pub fn mult(&mut self) -> MULT_W

Bits 6:7 - The MULT bits define the multiplier factor mul

impl W<u8, Reg<u8, _C1>>

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable

pub fn wuen(&mut self) -> WUEN_W

Bit 1 - Wakeup Enable

pub fn rsta(&mut self) -> RSTA_W

Bit 2 - Repeat START

pub fn txak(&mut self) -> TXAK_W

Bit 3 - Transmit Acknowledge Enable

pub fn tx(&mut self) -> TX_W

Bit 4 - Transmit Mode Select

pub fn mst(&mut self) -> MST_W

Bit 5 - Master Mode Select

pub fn iicie(&mut self) -> IICIE_W

Bit 6 - I2C Interrupt Enable

pub fn iicen(&mut self) -> IICEN_W

Bit 7 - I2C Enable

impl W<u8, Reg<u8, _S>>

pub fn iicif(&mut self) -> IICIF_W

Bit 1 - Interrupt Flag

pub fn ram(&mut self) -> RAM_W

Bit 3 - Range Address Match

pub fn arbl(&mut self) -> ARBL_W

Bit 4 - Arbitration Lost

pub fn iaas(&mut self) -> IAAS_W

Bit 6 - Addressed As A Slave

impl W<u8, Reg<u8, _D>>

pub fn data(&mut self) -> DATA_W

Bits 0:7 - Data

impl W<u8, Reg<u8, _C2>>

pub fn ad(&mut self) -> AD_W

Bits 0:2 - Slave Address

pub fn rmen(&mut self) -> RMEN_W

Bit 3 - Range Address Matching Enable

pub fn sbrc(&mut self) -> SBRC_W

Bit 4 - Slave Baud Rate Control

pub fn hdrs(&mut self) -> HDRS_W

Bit 5 - High Drive Select

pub fn adext(&mut self) -> ADEXT_W

Bit 6 - Address Extension

pub fn gcaen(&mut self) -> GCAEN_W

Bit 7 - General Call Address Enable

impl W<u8, Reg<u8, _FLT>>

pub fn flt(&mut self) -> FLT_W

Bits 0:3 - I2C Programmable Filter Factor

pub fn startf(&mut self) -> STARTF_W

Bit 4 - I2C Bus Start Detect Flag

pub fn ssie(&mut self) -> SSIE_W

Bit 5 - I2C Bus Stop or Start Interrupt Enable

pub fn stopf(&mut self) -> STOPF_W

Bit 6 - I2C Bus Stop Detect Flag

pub fn shen(&mut self) -> SHEN_W

Bit 7 - Stop Hold Enable

impl W<u8, Reg<u8, _RA>>

pub fn rad(&mut self) -> RAD_W

Bits 1:7 - Range Slave Address

impl W<u8, Reg<u8, _SMB>>

pub fn shtf2ie(&mut self) -> SHTF2IE_W

Bit 0 - SHTF2 Interrupt Enable

pub fn shtf2(&mut self) -> SHTF2_W

Bit 1 - SCL High Timeout Flag 2

pub fn sltf(&mut self) -> SLTF_W

Bit 3 - SCL Low Timeout Flag

pub fn tcksel(&mut self) -> TCKSEL_W

Bit 4 - Timeout Counter Clock Select

pub fn siicaen(&mut self) -> SIICAEN_W

Bit 5 - Second I2C Address Enable

pub fn alerten(&mut self) -> ALERTEN_W

Bit 6 - SMBus Alert Response Address Enable

pub fn fack(&mut self) -> FACK_W

Bit 7 - Fast NACK/ACK Enable

impl W<u8, Reg<u8, _A2>>

pub fn sad(&mut self) -> SAD_W

Bits 1:7 - SMBus Address

impl W<u8, Reg<u8, _SLTH>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Most significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _SLTL>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Least significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _A1>>

pub fn ad(&mut self) -> AD_W

Bits 1:7 - Address

impl W<u8, Reg<u8, _F>>

pub fn icr(&mut self) -> ICR_W

Bits 0:5 - ClockRate

pub fn mult(&mut self) -> MULT_W

Bits 6:7 - The MULT bits define the multiplier factor mul

impl W<u8, Reg<u8, _C1>>

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable

pub fn wuen(&mut self) -> WUEN_W

Bit 1 - Wakeup Enable

pub fn rsta(&mut self) -> RSTA_W

Bit 2 - Repeat START

pub fn txak(&mut self) -> TXAK_W

Bit 3 - Transmit Acknowledge Enable

pub fn tx(&mut self) -> TX_W

Bit 4 - Transmit Mode Select

pub fn mst(&mut self) -> MST_W

Bit 5 - Master Mode Select

pub fn iicie(&mut self) -> IICIE_W

Bit 6 - I2C Interrupt Enable

pub fn iicen(&mut self) -> IICEN_W

Bit 7 - I2C Enable

impl W<u8, Reg<u8, _S>>

pub fn iicif(&mut self) -> IICIF_W

Bit 1 - Interrupt Flag

pub fn ram(&mut self) -> RAM_W

Bit 3 - Range Address Match

pub fn arbl(&mut self) -> ARBL_W

Bit 4 - Arbitration Lost

pub fn iaas(&mut self) -> IAAS_W

Bit 6 - Addressed As A Slave

impl W<u8, Reg<u8, _D>>

pub fn data(&mut self) -> DATA_W

Bits 0:7 - Data

impl W<u8, Reg<u8, _C2>>

pub fn ad(&mut self) -> AD_W

Bits 0:2 - Slave Address

pub fn rmen(&mut self) -> RMEN_W

Bit 3 - Range Address Matching Enable

pub fn sbrc(&mut self) -> SBRC_W

Bit 4 - Slave Baud Rate Control

pub fn hdrs(&mut self) -> HDRS_W

Bit 5 - High Drive Select

pub fn adext(&mut self) -> ADEXT_W

Bit 6 - Address Extension

pub fn gcaen(&mut self) -> GCAEN_W

Bit 7 - General Call Address Enable

impl W<u8, Reg<u8, _FLT>>

pub fn flt(&mut self) -> FLT_W

Bits 0:3 - I2C Programmable Filter Factor

pub fn startf(&mut self) -> STARTF_W

Bit 4 - I2C Bus Start Detect Flag

pub fn ssie(&mut self) -> SSIE_W

Bit 5 - I2C Bus Stop or Start Interrupt Enable

pub fn stopf(&mut self) -> STOPF_W

Bit 6 - I2C Bus Stop Detect Flag

pub fn shen(&mut self) -> SHEN_W

Bit 7 - Stop Hold Enable

impl W<u8, Reg<u8, _RA>>

pub fn rad(&mut self) -> RAD_W

Bits 1:7 - Range Slave Address

impl W<u8, Reg<u8, _SMB>>

pub fn shtf2ie(&mut self) -> SHTF2IE_W

Bit 0 - SHTF2 Interrupt Enable

pub fn shtf2(&mut self) -> SHTF2_W

Bit 1 - SCL High Timeout Flag 2

pub fn sltf(&mut self) -> SLTF_W

Bit 3 - SCL Low Timeout Flag

pub fn tcksel(&mut self) -> TCKSEL_W

Bit 4 - Timeout Counter Clock Select

pub fn siicaen(&mut self) -> SIICAEN_W

Bit 5 - Second I2C Address Enable

pub fn alerten(&mut self) -> ALERTEN_W

Bit 6 - SMBus Alert Response Address Enable

pub fn fack(&mut self) -> FACK_W

Bit 7 - Fast NACK/ACK Enable

impl W<u8, Reg<u8, _A2>>

pub fn sad(&mut self) -> SAD_W

Bits 1:7 - SMBus Address

impl W<u8, Reg<u8, _SLTH>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Most significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _SLTL>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Least significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _A1>>

pub fn ad(&mut self) -> AD_W

Bits 1:7 - Address

impl W<u8, Reg<u8, _F>>

pub fn icr(&mut self) -> ICR_W

Bits 0:5 - ClockRate

pub fn mult(&mut self) -> MULT_W

Bits 6:7 - The MULT bits define the multiplier factor mul

impl W<u8, Reg<u8, _C1>>

pub fn dmaen(&mut self) -> DMAEN_W

Bit 0 - DMA Enable

pub fn wuen(&mut self) -> WUEN_W

Bit 1 - Wakeup Enable

pub fn rsta(&mut self) -> RSTA_W

Bit 2 - Repeat START

pub fn txak(&mut self) -> TXAK_W

Bit 3 - Transmit Acknowledge Enable

pub fn tx(&mut self) -> TX_W

Bit 4 - Transmit Mode Select

pub fn mst(&mut self) -> MST_W

Bit 5 - Master Mode Select

pub fn iicie(&mut self) -> IICIE_W

Bit 6 - I2C Interrupt Enable

pub fn iicen(&mut self) -> IICEN_W

Bit 7 - I2C Enable

impl W<u8, Reg<u8, _S>>

pub fn iicif(&mut self) -> IICIF_W

Bit 1 - Interrupt Flag

pub fn ram(&mut self) -> RAM_W

Bit 3 - Range Address Match

pub fn arbl(&mut self) -> ARBL_W

Bit 4 - Arbitration Lost

pub fn iaas(&mut self) -> IAAS_W

Bit 6 - Addressed As A Slave

impl W<u8, Reg<u8, _D>>

pub fn data(&mut self) -> DATA_W

Bits 0:7 - Data

impl W<u8, Reg<u8, _C2>>

pub fn ad(&mut self) -> AD_W

Bits 0:2 - Slave Address

pub fn rmen(&mut self) -> RMEN_W

Bit 3 - Range Address Matching Enable

pub fn sbrc(&mut self) -> SBRC_W

Bit 4 - Slave Baud Rate Control

pub fn hdrs(&mut self) -> HDRS_W

Bit 5 - High Drive Select

pub fn adext(&mut self) -> ADEXT_W

Bit 6 - Address Extension

pub fn gcaen(&mut self) -> GCAEN_W

Bit 7 - General Call Address Enable

impl W<u8, Reg<u8, _FLT>>

pub fn flt(&mut self) -> FLT_W

Bits 0:3 - I2C Programmable Filter Factor

pub fn startf(&mut self) -> STARTF_W

Bit 4 - I2C Bus Start Detect Flag

pub fn ssie(&mut self) -> SSIE_W

Bit 5 - I2C Bus Stop or Start Interrupt Enable

pub fn stopf(&mut self) -> STOPF_W

Bit 6 - I2C Bus Stop Detect Flag

pub fn shen(&mut self) -> SHEN_W

Bit 7 - Stop Hold Enable

impl W<u8, Reg<u8, _RA>>

pub fn rad(&mut self) -> RAD_W

Bits 1:7 - Range Slave Address

impl W<u8, Reg<u8, _SMB>>

pub fn shtf2ie(&mut self) -> SHTF2IE_W

Bit 0 - SHTF2 Interrupt Enable

pub fn shtf2(&mut self) -> SHTF2_W

Bit 1 - SCL High Timeout Flag 2

pub fn sltf(&mut self) -> SLTF_W

Bit 3 - SCL Low Timeout Flag

pub fn tcksel(&mut self) -> TCKSEL_W

Bit 4 - Timeout Counter Clock Select

pub fn siicaen(&mut self) -> SIICAEN_W

Bit 5 - Second I2C Address Enable

pub fn alerten(&mut self) -> ALERTEN_W

Bit 6 - SMBus Alert Response Address Enable

pub fn fack(&mut self) -> FACK_W

Bit 7 - Fast NACK/ACK Enable

impl W<u8, Reg<u8, _A2>>

pub fn sad(&mut self) -> SAD_W

Bits 1:7 - SMBus Address

impl W<u8, Reg<u8, _SLTH>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Most significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _SLTL>>

pub fn sslt(&mut self) -> SSLT_W

Bits 0:7 - Least significant byte of SCL low timeout value that determines the timeout period of SCL low.

impl W<u8, Reg<u8, _BDH>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:4 - UART Baud Rate Bits

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 6 - RxD Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 7 - LIN Break Detect Interrupt Enable

impl W<u8, Reg<u8, _BDL>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:7 - UART Baud Rate Bits

impl W<u8, Reg<u8, _C1>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-bit or 8-bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn uartswai(&mut self) -> UARTSWAI_W

Bit 6 - UART Stops in Wait Mode

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

impl W<u8, Reg<u8, _C2>>

pub fn sbk(&mut self) -> SBK_W

Bit 0 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 1 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 2 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 3 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 4 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 5 - Receiver Full Interrupt or DMA Transfer Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 6 - Transmission Complete Interrupt Enable

pub fn tie(&mut self) -> TIE_W

Bit 7 - Transmitter Interrupt or DMA Transfer Enable.

impl W<u8, Reg<u8, _S2>>

pub fn lbkde(&mut self) -> LBKDE_W

Bit 1 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 2 - Break Transmit Character Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 3 - Receive Wakeup Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 4 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 5 - Most Significant Bit First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 6 - RxD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 7 - LIN Break Detect Interrupt Flag

impl W<u8, Reg<u8, _C3>>

pub fn peie(&mut self) -> PEIE_W

Bit 0 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 1 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 2 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 3 - Overrun Error Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 4 - Transmit Data Inversion.

pub fn txdir(&mut self) -> TXDIR_W

Bit 5 - Transmitter Pin Data Direction in Single-Wire mode

pub fn t8(&mut self) -> T8_W

Bit 6 - Transmit Bit 8

impl W<u8, Reg<u8, _D>>

pub fn rt(&mut self) -> RT_W

Bits 0:7 - Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register

impl W<u8, Reg<u8, _MA1>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _MA2>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _C4>>

pub fn brfa(&mut self) -> BRFA_W

Bits 0:4 - Baud Rate Fine Adjust

pub fn m10(&mut self) -> M10_W

Bit 5 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 6 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 7 - Match Address Mode Enable 1

impl W<u8, Reg<u8, _C5>>

pub fn rdmas(&mut self) -> RDMAS_W

Bit 5 - Receiver Full DMA Select

pub fn tdmas(&mut self) -> TDMAS_W

Bit 7 - Transmitter DMA Select

impl W<u8, Reg<u8, _MODEM>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

impl W<u8, Reg<u8, _IR>>

pub fn tnp(&mut self) -> TNP_W

Bits 0:1 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 2 - Infrared enable

impl W<u8, Reg<u8, _PFIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

impl W<u8, Reg<u8, _CFIFO>>

pub fn rxufe(&mut self) -> RXUFE_W

Bit 0 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 1 - Transmit FIFO Overflow Interrupt Enable

pub fn rxofe(&mut self) -> RXOFE_W

Bit 2 - Receive FIFO Overflow Interrupt Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 6 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 7 - Transmit FIFO/Buffer Flush

impl W<u8, Reg<u8, _SFIFO>>

pub fn rxuf(&mut self) -> RXUF_W

Bit 0 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 1 - Transmitter Buffer Overflow Flag

pub fn rxof(&mut self) -> RXOF_W

Bit 2 - Receiver Buffer Overflow Flag

impl W<u8, Reg<u8, _TWFIFO>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:7 - Transmit Watermark

impl W<u8, Reg<u8, _RWFIFO>>

pub fn rxwater(&mut self) -> RXWATER_W

Bits 0:7 - Receive Watermark

impl W<u8, Reg<u8, _C7816>>

pub fn iso_7816e(&mut self) -> ISO_7816E_W

Bit 0 - ISO-7816 Functionality Enabled

pub fn ttype(&mut self) -> TTYPE_W

Bit 1 - Transfer Type

pub fn init(&mut self) -> INIT_W

Bit 2 - Detect Initial Character

pub fn anack(&mut self) -> ANACK_W

Bit 3 - Generate NACK on Error

pub fn onack(&mut self) -> ONACK_W

Bit 4 - Generate NACK on Overflow

impl W<u8, Reg<u8, _IE7816>>

pub fn rxte(&mut self) -> RXTE_W

Bit 0 - Receive Threshold Exceeded Interrupt Enable

pub fn txte(&mut self) -> TXTE_W

Bit 1 - Transmit Threshold Exceeded Interrupt Enable

pub fn gtve(&mut self) -> GTVE_W

Bit 2 - Guard Timer Violated Interrupt Enable

pub fn initde(&mut self) -> INITDE_W

Bit 4 - Initial Character Detected Interrupt Enable

pub fn bwte(&mut self) -> BWTE_W

Bit 5 - Block Wait Timer Interrupt Enable

pub fn cwte(&mut self) -> CWTE_W

Bit 6 - Character Wait Timer Interrupt Enable

pub fn wte(&mut self) -> WTE_W

Bit 7 - Wait Timer Interrupt Enable

impl W<u8, Reg<u8, _IS7816>>

pub fn rxt(&mut self) -> RXT_W

Bit 0 - Receive Threshold Exceeded Interrupt

pub fn txt(&mut self) -> TXT_W

Bit 1 - Transmit Threshold Exceeded Interrupt

pub fn gtv(&mut self) -> GTV_W

Bit 2 - Guard Timer Violated Interrupt

pub fn initd(&mut self) -> INITD_W

Bit 4 - Initial Character Detected Interrupt

pub fn bwt(&mut self) -> BWT_W

Bit 5 - Block Wait Timer Interrupt

pub fn cwt(&mut self) -> CWT_W

Bit 6 - Character Wait Timer Interrupt

pub fn wt(&mut self) -> WT_W

Bit 7 - Wait Timer Interrupt

impl W<u8, Reg<u8, _WP7816T0>>

pub fn wi(&mut self) -> WI_W

Bits 0:7 - Wait Time Integer (C7816[TTYPE] = 0)

impl W<u8, Reg<u8, _WP7816T1>>

pub fn bwi(&mut self) -> BWI_W

Bits 0:3 - Block Wait Time Integer(C7816[TTYPE] = 1)

pub fn cwi(&mut self) -> CWI_W

Bits 4:7 - Character Wait Time Integer (C7816[TTYPE] = 1)

impl W<u8, Reg<u8, _WN7816>>

pub fn gtn(&mut self) -> GTN_W

Bits 0:7 - Guard Band N

impl W<u8, Reg<u8, _WF7816>>

pub fn gtfd(&mut self) -> GTFD_W

Bits 0:7 - FD Multiplier

impl W<u8, Reg<u8, _ET7816>>

pub fn rxthreshold(&mut self) -> RXTHRESHOLD_W

Bits 0:3 - Receive NACK Threshold

pub fn txthreshold(&mut self) -> TXTHRESHOLD_W

Bits 4:7 - Transmit NACK Threshold

impl W<u8, Reg<u8, _TL7816>>

pub fn tlen(&mut self) -> TLEN_W

Bits 0:7 - Transmit Length

impl W<u8, Reg<u8, _BDH>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:4 - UART Baud Rate Bits

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 6 - RxD Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 7 - LIN Break Detect Interrupt Enable

impl W<u8, Reg<u8, _BDL>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:7 - UART Baud Rate Bits

impl W<u8, Reg<u8, _C1>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-bit or 8-bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn uartswai(&mut self) -> UARTSWAI_W

Bit 6 - UART Stops in Wait Mode

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

impl W<u8, Reg<u8, _C2>>

pub fn sbk(&mut self) -> SBK_W

Bit 0 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 1 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 2 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 3 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 4 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 5 - Receiver Full Interrupt or DMA Transfer Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 6 - Transmission Complete Interrupt Enable

pub fn tie(&mut self) -> TIE_W

Bit 7 - Transmitter Interrupt or DMA Transfer Enable.

impl W<u8, Reg<u8, _S2>>

pub fn lbkde(&mut self) -> LBKDE_W

Bit 1 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 2 - Break Transmit Character Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 3 - Receive Wakeup Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 4 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 5 - Most Significant Bit First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 6 - RxD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 7 - LIN Break Detect Interrupt Flag

impl W<u8, Reg<u8, _C3>>

pub fn peie(&mut self) -> PEIE_W

Bit 0 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 1 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 2 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 3 - Overrun Error Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 4 - Transmit Data Inversion.

pub fn txdir(&mut self) -> TXDIR_W

Bit 5 - Transmitter Pin Data Direction in Single-Wire mode

pub fn t8(&mut self) -> T8_W

Bit 6 - Transmit Bit 8

impl W<u8, Reg<u8, _D>>

pub fn rt(&mut self) -> RT_W

Bits 0:7 - Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register

impl W<u8, Reg<u8, _MA1>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _MA2>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _C4>>

pub fn brfa(&mut self) -> BRFA_W

Bits 0:4 - Baud Rate Fine Adjust

pub fn m10(&mut self) -> M10_W

Bit 5 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 6 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 7 - Match Address Mode Enable 1

impl W<u8, Reg<u8, _C5>>

pub fn rdmas(&mut self) -> RDMAS_W

Bit 5 - Receiver Full DMA Select

pub fn tdmas(&mut self) -> TDMAS_W

Bit 7 - Transmitter DMA Select

impl W<u8, Reg<u8, _MODEM>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

impl W<u8, Reg<u8, _IR>>

pub fn tnp(&mut self) -> TNP_W

Bits 0:1 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 2 - Infrared enable

impl W<u8, Reg<u8, _PFIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

impl W<u8, Reg<u8, _CFIFO>>

pub fn rxufe(&mut self) -> RXUFE_W

Bit 0 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 1 - Transmit FIFO Overflow Interrupt Enable

pub fn rxofe(&mut self) -> RXOFE_W

Bit 2 - Receive FIFO Overflow Interrupt Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 6 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 7 - Transmit FIFO/Buffer Flush

impl W<u8, Reg<u8, _SFIFO>>

pub fn rxuf(&mut self) -> RXUF_W

Bit 0 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 1 - Transmitter Buffer Overflow Flag

pub fn rxof(&mut self) -> RXOF_W

Bit 2 - Receiver Buffer Overflow Flag

impl W<u8, Reg<u8, _TWFIFO>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:7 - Transmit Watermark

impl W<u8, Reg<u8, _RWFIFO>>

pub fn rxwater(&mut self) -> RXWATER_W

Bits 0:7 - Receive Watermark

impl W<u8, Reg<u8, _BDH>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:4 - UART Baud Rate Bits

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 6 - RxD Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 7 - LIN Break Detect Interrupt Enable

impl W<u8, Reg<u8, _BDL>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:7 - UART Baud Rate Bits

impl W<u8, Reg<u8, _C1>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-bit or 8-bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn uartswai(&mut self) -> UARTSWAI_W

Bit 6 - UART Stops in Wait Mode

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

impl W<u8, Reg<u8, _C2>>

pub fn sbk(&mut self) -> SBK_W

Bit 0 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 1 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 2 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 3 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 4 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 5 - Receiver Full Interrupt or DMA Transfer Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 6 - Transmission Complete Interrupt Enable

pub fn tie(&mut self) -> TIE_W

Bit 7 - Transmitter Interrupt or DMA Transfer Enable.

impl W<u8, Reg<u8, _S2>>

pub fn lbkde(&mut self) -> LBKDE_W

Bit 1 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 2 - Break Transmit Character Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 3 - Receive Wakeup Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 4 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 5 - Most Significant Bit First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 6 - RxD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 7 - LIN Break Detect Interrupt Flag

impl W<u8, Reg<u8, _C3>>

pub fn peie(&mut self) -> PEIE_W

Bit 0 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 1 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 2 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 3 - Overrun Error Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 4 - Transmit Data Inversion.

pub fn txdir(&mut self) -> TXDIR_W

Bit 5 - Transmitter Pin Data Direction in Single-Wire mode

pub fn t8(&mut self) -> T8_W

Bit 6 - Transmit Bit 8

impl W<u8, Reg<u8, _D>>

pub fn rt(&mut self) -> RT_W

Bits 0:7 - Reads return the contents of the read-only receive data register and writes go to the write-only transmit data register

impl W<u8, Reg<u8, _MA1>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _MA2>>

pub fn ma(&mut self) -> MA_W

Bits 0:7 - Match Address

impl W<u8, Reg<u8, _C4>>

pub fn brfa(&mut self) -> BRFA_W

Bits 0:4 - Baud Rate Fine Adjust

pub fn m10(&mut self) -> M10_W

Bit 5 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 6 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 7 - Match Address Mode Enable 1

impl W<u8, Reg<u8, _C5>>

pub fn rdmas(&mut self) -> RDMAS_W

Bit 5 - Receiver Full DMA Select

pub fn tdmas(&mut self) -> TDMAS_W

Bit 7 - Transmitter DMA Select

impl W<u8, Reg<u8, _MODEM>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

impl W<u8, Reg<u8, _IR>>

pub fn tnp(&mut self) -> TNP_W

Bits 0:1 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 2 - Infrared enable

impl W<u8, Reg<u8, _PFIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

impl W<u8, Reg<u8, _CFIFO>>

pub fn rxufe(&mut self) -> RXUFE_W

Bit 0 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 1 - Transmit FIFO Overflow Interrupt Enable

pub fn rxofe(&mut self) -> RXOFE_W

Bit 2 - Receive FIFO Overflow Interrupt Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 6 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 7 - Transmit FIFO/Buffer Flush

impl W<u8, Reg<u8, _SFIFO>>

pub fn rxuf(&mut self) -> RXUF_W

Bit 0 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 1 - Transmitter Buffer Overflow Flag

pub fn rxof(&mut self) -> RXOF_W

Bit 2 - Receiver Buffer Overflow Flag

impl W<u8, Reg<u8, _TWFIFO>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:7 - Transmit Watermark

impl W<u8, Reg<u8, _RWFIFO>>

pub fn rxwater(&mut self) -> RXWATER_W

Bits 0:7 - Receive Watermark

impl W<u8, Reg<u8, _OTGISTAT>>

pub fn avbuschg(&mut self) -> AVBUSCHG_W

Bit 0 - This bit is set when a change in VBUS is detected on an A device.

pub fn b_sess_chg(&mut self) -> B_SESS_CHG_W

Bit 2 - This bit is set when a change in VBUS is detected on a B device.

pub fn sessvldchg(&mut self) -> SESSVLDCHG_W

Bit 3 - This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid

pub fn line_state_chg(&mut self) -> LINE_STATE_CHG_W

Bit 5 - This bit is set when the USB line state changes

pub fn onemsec(&mut self) -> ONEMSEC_W

Bit 6 - This bit is set when the 1 millisecond timer expires

pub fn idchg(&mut self) -> IDCHG_W

Bit 7 - This bit is set when a change in the ID Signal from the USB connector is sensed.

impl W<u8, Reg<u8, _OTGICR>>

pub fn avbusen(&mut self) -> AVBUSEN_W

Bit 0 - A VBUS Valid Interrupt Enable

pub fn bsessen(&mut self) -> BSESSEN_W

Bit 2 - B Session END Interrupt Enable

pub fn sessvlden(&mut self) -> SESSVLDEN_W

Bit 3 - Session Valid Interrupt Enable

pub fn linestateen(&mut self) -> LINESTATEEN_W

Bit 5 - Line State Change Interrupt Enable

pub fn onemsecen(&mut self) -> ONEMSECEN_W

Bit 6 - One Millisecond Interrupt Enable

pub fn iden(&mut self) -> IDEN_W

Bit 7 - ID Interrupt Enable

impl W<u8, Reg<u8, _OTGSTAT>>

pub fn avbusvld(&mut self) -> AVBUSVLD_W

Bit 0 - A VBUS Valid

pub fn bsessend(&mut self) -> BSESSEND_W

Bit 2 - B Session End

pub fn sess_vld(&mut self) -> SESS_VLD_W

Bit 3 - Session Valid

pub fn linestatestable(&mut self) -> LINESTATESTABLE_W

Bit 5 - Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond

pub fn onemsecen(&mut self) -> ONEMSECEN_W

Bit 6 - This bit is reserved for the 1ms count, but it is not useful to software.

pub fn id(&mut self) -> ID_W

Bit 7 - Indicates the current state of the ID pin on the USB connector

impl W<u8, Reg<u8, _OTGCTL>>

pub fn otgen(&mut self) -> OTGEN_W

Bit 2 - On-The-Go pullup/pulldown resistor enable

pub fn dmlow(&mut self) -> DMLOW_W

Bit 4 - D- Data Line pull-down resistor enable

pub fn dplow(&mut self) -> DPLOW_W

Bit 5 - D+ Data Line pull-down resistor enable

pub fn dphigh(&mut self) -> DPHIGH_W

Bit 7 - D+ Data Line pullup resistor enable

impl W<u8, Reg<u8, _ISTAT>>

pub fn usbrst(&mut self) -> USBRST_W

Bit 0 - This bit is set when the USB Module has decoded a valid USB reset

pub fn error(&mut self) -> ERROR_W

Bit 1 - This bit is set when any of the error conditions within Error Interrupt Status (ERRSTAT) register occur

pub fn softok(&mut self) -> SOFTOK_W

Bit 2 - This bit is set when the USB Module receives a Start Of Frame (SOF) token

pub fn tokdne(&mut self) -> TOKDNE_W

Bit 3 - This bit is set when the current token being processed has completed

pub fn sleep(&mut self) -> SLEEP_W

Bit 4 - This bit is set when the USB Module detects a constant idle on the USB bus for 3 ms

pub fn resume(&mut self) -> RESUME_W

Bit 5 - This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the USB bus

pub fn attach(&mut self) -> ATTACH_W

Bit 6 - Attach Interrupt

pub fn stall(&mut self) -> STALL_W

Bit 7 - Stall Interrupt

impl W<u8, Reg<u8, _INTEN>>

pub fn usbrsten(&mut self) -> USBRSTEN_W

Bit 0 - USBRST Interrupt Enable

pub fn erroren(&mut self) -> ERROREN_W

Bit 1 - ERROR Interrupt Enable

pub fn softoken(&mut self) -> SOFTOKEN_W

Bit 2 - SOFTOK Interrupt Enable

pub fn tokdneen(&mut self) -> TOKDNEEN_W

Bit 3 - TOKDNE Interrupt Enable

pub fn sleepen(&mut self) -> SLEEPEN_W

Bit 4 - SLEEP Interrupt Enable

pub fn resumeen(&mut self) -> RESUMEEN_W

Bit 5 - RESUME Interrupt Enable

pub fn attachen(&mut self) -> ATTACHEN_W

Bit 6 - ATTACH Interrupt Enable

pub fn stallen(&mut self) -> STALLEN_W

Bit 7 - STALL Interrupt Enable

impl W<u8, Reg<u8, _ERRSTAT>>

pub fn piderr(&mut self) -> PIDERR_W

Bit 0 - This bit is set when the PID check field fails.

pub fn crc5eof(&mut self) -> CRC5EOF_W

Bit 1 - This error interrupt has two functions

pub fn crc16(&mut self) -> CRC16_W

Bit 2 - This bit is set when a data packet is rejected due to a CRC16 error.

pub fn dfn8(&mut self) -> DFN8_W

Bit 3 - This bit is set if the data field received was not 8 bits in length

pub fn btoerr(&mut self) -> BTOERR_W

Bit 4 - This bit is set when a bus turnaround timeout error occurs

pub fn dmaerr(&mut self) -> DMAERR_W

Bit 5 - This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given the bus before it needs to receive or transmit data

pub fn btserr(&mut self) -> BTSERR_W

Bit 7 - This bit is set when a bit stuff error is detected

impl W<u8, Reg<u8, _ERREN>>

pub fn piderren(&mut self) -> PIDERREN_W

Bit 0 - PIDERR Interrupt Enable

pub fn crc5eofen(&mut self) -> CRC5EOFEN_W

Bit 1 - CRC5/EOF Interrupt Enable

pub fn crc16en(&mut self) -> CRC16EN_W

Bit 2 - CRC16 Interrupt Enable

pub fn dfn8en(&mut self) -> DFN8EN_W

Bit 3 - DFN8 Interrupt Enable

pub fn btoerren(&mut self) -> BTOERREN_W

Bit 4 - BTOERR Interrupt Enable

pub fn dmaerren(&mut self) -> DMAERREN_W

Bit 5 - DMAERR Interrupt Enable

pub fn btserren(&mut self) -> BTSERREN_W

Bit 7 - BTSERR Interrupt Enable

impl W<u8, Reg<u8, _CTL>>

pub fn usbensofen(&mut self) -> USBENSOFEN_W

Bit 0 - USB Enable

pub fn oddrst(&mut self) -> ODDRST_W

Bit 1 - Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the EVEN BDT bank

pub fn resume(&mut self) -> RESUME_W

Bit 2 - When set to 1 this bit enables the USB Module to execute resume signaling

pub fn hostmodeen(&mut self) -> HOSTMODEEN_W

Bit 3 - When set to 1, this bit enables the USB Module to operate in Host mode

pub fn reset(&mut self) -> RESET_W

Bit 4 - Setting this bit enables the USB Module to generate USB reset signaling

pub fn txsuspendtokenbusy(&mut self) -> TXSUSPENDTOKENBUSY_W

Bit 5 - In Host mode, TOKEN_BUSY is set when the USB module is busy executing a USB token

pub fn se0(&mut self) -> SE0_W

Bit 6 - Live USB Single Ended Zero signal

pub fn jstate(&mut self) -> JSTATE_W

Bit 7 - Live USB differential receiver JSTATE signal

impl W<u8, Reg<u8, _ADDR>>

pub fn addr(&mut self) -> ADDR_W

Bits 0:6 - USB Address

pub fn lsen(&mut self) -> LSEN_W

Bit 7 - Low Speed Enable bit

impl W<u8, Reg<u8, _BDTPAGE1>>

pub fn bdtba(&mut self) -> BDTBA_W

Bits 1:7 - Provides address bits 15 through 9 of the BDT base address.

impl W<u8, Reg<u8, _FRMNUML>>

pub fn frm(&mut self) -> FRM_W

Bits 0:7 - This 8-bit field and the 3-bit field in the Frame Number Register High are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory

impl W<u8, Reg<u8, _FRMNUMH>>

pub fn frm(&mut self) -> FRM_W

Bits 0:2 - This 3-bit field and the 8-bit field in the Frame Number Register Low are used to compute the address where the current Buffer Descriptor Table (BDT) resides in system memory

impl W<u8, Reg<u8, _TOKEN>>

pub fn tokenendpt(&mut self) -> TOKENENDPT_W

Bits 0:3 - Holds the Endpoint address for the token command

pub fn tokenpid(&mut self) -> TOKENPID_W

Bits 4:7 - Contains the token type executed by the USB module.

impl W<u8, Reg<u8, _SOFTHLD>>

pub fn cnt(&mut self) -> CNT_W

Bits 0:7 - Represents the SOF count threshold in byte times.

impl W<u8, Reg<u8, _BDTPAGE2>>

pub fn bdtba(&mut self) -> BDTBA_W

Bits 0:7 - Provides address bits 23 through 16 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory

impl W<u8, Reg<u8, _BDTPAGE3>>

pub fn bdtba(&mut self) -> BDTBA_W

Bits 0:7 - Provides address bits 31 through 24 of the BDT base address that defines the location of Buffer Descriptor Table resides in system memory

impl W<u8, Reg<u8, _ENDPT>>

pub fn ephshk(&mut self) -> EPHSHK_W

Bit 0 - When set this bit enables an endpoint to perform handshaking during a transaction to this endpoint

pub fn epstall(&mut self) -> EPSTALL_W

Bit 1 - When set this bit indicates that the endpoint is called

pub fn eptxen(&mut self) -> EPTXEN_W

Bit 2 - This bit, when set, enables the endpoint for TX transfers.

pub fn eprxen(&mut self) -> EPRXEN_W

Bit 3 - This bit, when set, enables the endpoint for RX transfers.

pub fn epctldis(&mut self) -> EPCTLDIS_W

Bit 4 - This bit, when set, disables control (SETUP) transfers

pub fn retrydis(&mut self) -> RETRYDIS_W

Bit 6 - This is a Host mode only bit and is present in the control register for endpoint 0 (ENDPT0) only

pub fn hostwohub(&mut self) -> HOSTWOHUB_W

Bit 7 - This is a Host mode only field and is present in the control register for endpoint 0 (ENDPT0) only

impl W<u8, Reg<u8, _USBCTRL>>

pub fn pde(&mut self) -> PDE_W

Bit 6 - Enables the weak pulldowns on the USB transceiver.

pub fn susp(&mut self) -> SUSP_W

Bit 7 - Places the USB transceiver into the suspend state.

impl W<u8, Reg<u8, _CONTROL>>

pub fn dppullupnonotg(&mut self) -> DPPULLUPNONOTG_W

Bit 4 - Provides control of the DP Pullup in the USB OTG module, if USB is configured in non-OTG device mode

impl W<u8, Reg<u8, _USBTRC0>>

pub fn usbresmen(&mut self) -> USBRESMEN_W

Bit 5 - Asynchronous Resume Interrupt Enable

pub fn usbreset(&mut self) -> USBRESET_W

Bit 7 - USB Reset

impl W<u8, Reg<u8, _USBFRMADJUST>>

pub fn adj(&mut self) -> ADJ_W

Bits 0:7 - Frame Adjustment

impl W<u8, Reg<u8, _CR0>>

pub fn hystctr(&mut self) -> HYSTCTR_W

Bits 0:1 - Comparator hard block hysteresis control

pub fn filter_cnt(&mut self) -> FILTER_CNT_W

Bits 4:6 - Filter Sample Count

impl W<u8, Reg<u8, _CR1>>

pub fn en(&mut self) -> EN_W

Bit 0 - Comparator Module Enable

pub fn ope(&mut self) -> OPE_W

Bit 1 - Comparator Output Pin Enable

pub fn cos(&mut self) -> COS_W

Bit 2 - Comparator Output Select

pub fn inv(&mut self) -> INV_W

Bit 3 - Comparator INVERT

pub fn pmode(&mut self) -> PMODE_W

Bit 4 - Power Mode Select

pub fn we(&mut self) -> WE_W

Bit 6 - Windowing Enable

pub fn se(&mut self) -> SE_W

Bit 7 - Sample Enable

impl W<u8, Reg<u8, _FPR>>

pub fn filt_per(&mut self) -> FILT_PER_W

Bits 0:7 - Filter Sample Period

impl W<u8, Reg<u8, _SCR>>

pub fn cff(&mut self) -> CFF_W

Bit 1 - Analog Comparator Flag Falling

pub fn cfr(&mut self) -> CFR_W

Bit 2 - Analog Comparator Flag Rising

pub fn ief(&mut self) -> IEF_W

Bit 3 - Comparator Interrupt Enable Falling

pub fn ier(&mut self) -> IER_W

Bit 4 - Comparator Interrupt Enable Rising

pub fn dmaen(&mut self) -> DMAEN_W

Bit 6 - DMA Enable Control

impl W<u8, Reg<u8, _DACCR>>

pub fn vosel(&mut self) -> VOSEL_W

Bits 0:5 - DAC Output Voltage Select

pub fn vrsel(&mut self) -> VRSEL_W

Bit 6 - Supply Voltage Reference Source Select

pub fn dacen(&mut self) -> DACEN_W

Bit 7 - DAC Enable

impl W<u8, Reg<u8, _MUXCR>>

pub fn msel(&mut self) -> MSEL_W

Bits 0:2 - Minus Input Mux Control

pub fn psel(&mut self) -> PSEL_W

Bits 3:5 - Plus Input Mux Control

pub fn pstm(&mut self) -> PSTM_W

Bit 7 - Pass Through Mode Enable

impl W<u8, Reg<u8, _CR0>>

pub fn hystctr(&mut self) -> HYSTCTR_W

Bits 0:1 - Comparator hard block hysteresis control

pub fn filter_cnt(&mut self) -> FILTER_CNT_W

Bits 4:6 - Filter Sample Count

impl W<u8, Reg<u8, _CR1>>

pub fn en(&mut self) -> EN_W

Bit 0 - Comparator Module Enable

pub fn ope(&mut self) -> OPE_W

Bit 1 - Comparator Output Pin Enable

pub fn cos(&mut self) -> COS_W

Bit 2 - Comparator Output Select

pub fn inv(&mut self) -> INV_W

Bit 3 - Comparator INVERT

pub fn pmode(&mut self) -> PMODE_W

Bit 4 - Power Mode Select

pub fn we(&mut self) -> WE_W

Bit 6 - Windowing Enable

pub fn se(&mut self) -> SE_W

Bit 7 - Sample Enable

impl W<u8, Reg<u8, _FPR>>

pub fn filt_per(&mut self) -> FILT_PER_W

Bits 0:7 - Filter Sample Period

impl W<u8, Reg<u8, _SCR>>

pub fn cff(&mut self) -> CFF_W

Bit 1 - Analog Comparator Flag Falling

pub fn cfr(&mut self) -> CFR_W

Bit 2 - Analog Comparator Flag Rising

pub fn ief(&mut self) -> IEF_W

Bit 3 - Comparator Interrupt Enable Falling

pub fn ier(&mut self) -> IER_W

Bit 4 - Comparator Interrupt Enable Rising

pub fn dmaen(&mut self) -> DMAEN_W

Bit 6 - DMA Enable Control

impl W<u8, Reg<u8, _DACCR>>

pub fn vosel(&mut self) -> VOSEL_W

Bits 0:5 - DAC Output Voltage Select

pub fn vrsel(&mut self) -> VRSEL_W

Bit 6 - Supply Voltage Reference Source Select

pub fn dacen(&mut self) -> DACEN_W

Bit 7 - DAC Enable

impl W<u8, Reg<u8, _MUXCR>>

pub fn msel(&mut self) -> MSEL_W

Bits 0:2 - Minus Input Mux Control

pub fn psel(&mut self) -> PSEL_W

Bits 3:5 - Plus Input Mux Control

pub fn pstm(&mut self) -> PSTM_W

Bit 7 - Pass Through Mode Enable

impl W<u8, Reg<u8, _CR0>>

pub fn hystctr(&mut self) -> HYSTCTR_W

Bits 0:1 - Comparator hard block hysteresis control

pub fn filter_cnt(&mut self) -> FILTER_CNT_W

Bits 4:6 - Filter Sample Count

impl W<u8, Reg<u8, _CR1>>

pub fn en(&mut self) -> EN_W

Bit 0 - Comparator Module Enable

pub fn ope(&mut self) -> OPE_W

Bit 1 - Comparator Output Pin Enable

pub fn cos(&mut self) -> COS_W

Bit 2 - Comparator Output Select

pub fn inv(&mut self) -> INV_W

Bit 3 - Comparator INVERT

pub fn pmode(&mut self) -> PMODE_W

Bit 4 - Power Mode Select

pub fn we(&mut self) -> WE_W

Bit 6 - Windowing Enable

pub fn se(&mut self) -> SE_W

Bit 7 - Sample Enable

impl W<u8, Reg<u8, _FPR>>

pub fn filt_per(&mut self) -> FILT_PER_W

Bits 0:7 - Filter Sample Period

impl W<u8, Reg<u8, _SCR>>

pub fn cff(&mut self) -> CFF_W

Bit 1 - Analog Comparator Flag Falling

pub fn cfr(&mut self) -> CFR_W

Bit 2 - Analog Comparator Flag Rising

pub fn ief(&mut self) -> IEF_W

Bit 3 - Comparator Interrupt Enable Falling

pub fn ier(&mut self) -> IER_W

Bit 4 - Comparator Interrupt Enable Rising

pub fn dmaen(&mut self) -> DMAEN_W

Bit 6 - DMA Enable Control

impl W<u8, Reg<u8, _DACCR>>

pub fn vosel(&mut self) -> VOSEL_W

Bits 0:5 - DAC Output Voltage Select

pub fn vrsel(&mut self) -> VRSEL_W

Bit 6 - Supply Voltage Reference Source Select

pub fn dacen(&mut self) -> DACEN_W

Bit 7 - DAC Enable

impl W<u8, Reg<u8, _MUXCR>>

pub fn msel(&mut self) -> MSEL_W

Bits 0:2 - Minus Input Mux Control

pub fn psel(&mut self) -> PSEL_W

Bits 3:5 - Plus Input Mux Control

pub fn pstm(&mut self) -> PSTM_W

Bit 7 - Pass Through Mode Enable

impl W<u8, Reg<u8, _TRM>>

pub fn trim(&mut self) -> TRIM_W

Bits 0:5 - Trim bits

pub fn chopen(&mut self) -> CHOPEN_W

Bit 6 - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.

impl W<u8, Reg<u8, _SC>>

pub fn mode_lv(&mut self) -> MODE_LV_W

Bits 0:1 - Buffer Mode selection

pub fn icompen(&mut self) -> ICOMPEN_W

Bit 5 - Second order curvature compensation enable

pub fn regen(&mut self) -> REGEN_W

Bit 6 - Regulator enable

pub fn vrefen(&mut self) -> VREFEN_W

Bit 7 - Internal Voltage Reference enable

impl W<u8, Reg<u8, _PE1>>

pub fn wupe0(&mut self) -> WUPE0_W

Bits 0:1 - Wakeup Pin Enable For LLWU_P0

pub fn wupe1(&mut self) -> WUPE1_W

Bits 2:3 - Wakeup Pin Enable For LLWU_P1

pub fn wupe2(&mut self) -> WUPE2_W

Bits 4:5 - Wakeup Pin Enable For LLWU_P2

pub fn wupe3(&mut self) -> WUPE3_W

Bits 6:7 - Wakeup Pin Enable For LLWU_P3

impl W<u8, Reg<u8, _PE2>>

pub fn wupe4(&mut self) -> WUPE4_W

Bits 0:1 - Wakeup Pin Enable For LLWU_P4

pub fn wupe5(&mut self) -> WUPE5_W

Bits 2:3 - Wakeup Pin Enable For LLWU_P5

pub fn wupe6(&mut self) -> WUPE6_W

Bits 4:5 - Wakeup Pin Enable For LLWU_P6

pub fn wupe7(&mut self) -> WUPE7_W

Bits 6:7 - Wakeup Pin Enable For LLWU_P7

impl W<u8, Reg<u8, _PE3>>

pub fn wupe8(&mut self) -> WUPE8_W

Bits 0:1 - Wakeup Pin Enable For LLWU_P8

pub fn wupe9(&mut self) -> WUPE9_W

Bits 2:3 - Wakeup Pin Enable For LLWU_P9

pub fn wupe10(&mut self) -> WUPE10_W

Bits 4:5 - Wakeup Pin Enable For LLWU_P10

pub fn wupe11(&mut self) -> WUPE11_W

Bits 6:7 - Wakeup Pin Enable For LLWU_P11

impl W<u8, Reg<u8, _PE4>>

pub fn wupe12(&mut self) -> WUPE12_W

Bits 0:1 - Wakeup Pin Enable For LLWU_P12

pub fn wupe13(&mut self) -> WUPE13_W

Bits 2:3 - Wakeup Pin Enable For LLWU_P13

pub fn wupe14(&mut self) -> WUPE14_W

Bits 4:5 - Wakeup Pin Enable For LLWU_P14

pub fn wupe15(&mut self) -> WUPE15_W

Bits 6:7 - Wakeup Pin Enable For LLWU_P15

impl W<u8, Reg<u8, _ME>>

pub fn wume0(&mut self) -> WUME0_W

Bit 0 - Wakeup Module Enable For Module 0

pub fn wume1(&mut self) -> WUME1_W

Bit 1 - Wakeup Module Enable for Module 1

pub fn wume2(&mut self) -> WUME2_W

Bit 2 - Wakeup Module Enable For Module 2

pub fn wume3(&mut self) -> WUME3_W

Bit 3 - Wakeup Module Enable For Module 3

pub fn wume4(&mut self) -> WUME4_W

Bit 4 - Wakeup Module Enable For Module 4

pub fn wume5(&mut self) -> WUME5_W

Bit 5 - Wakeup Module Enable For Module 5

pub fn wume6(&mut self) -> WUME6_W

Bit 6 - Wakeup Module Enable For Module 6

pub fn wume7(&mut self) -> WUME7_W

Bit 7 - Wakeup Module Enable For Module 7

impl W<u8, Reg<u8, _F1>>

pub fn wuf0(&mut self) -> WUF0_W

Bit 0 - Wakeup Flag For LLWU_P0

pub fn wuf1(&mut self) -> WUF1_W

Bit 1 - Wakeup Flag For LLWU_P1

pub fn wuf2(&mut self) -> WUF2_W

Bit 2 - Wakeup Flag For LLWU_P2

pub fn wuf3(&mut self) -> WUF3_W

Bit 3 - Wakeup Flag For LLWU_P3

pub fn wuf4(&mut self) -> WUF4_W

Bit 4 - Wakeup Flag For LLWU_P4

pub fn wuf5(&mut self) -> WUF5_W

Bit 5 - Wakeup Flag For LLWU_P5

pub fn wuf6(&mut self) -> WUF6_W

Bit 6 - Wakeup Flag For LLWU_P6

pub fn wuf7(&mut self) -> WUF7_W

Bit 7 - Wakeup Flag For LLWU_P7

impl W<u8, Reg<u8, _F2>>

pub fn wuf8(&mut self) -> WUF8_W

Bit 0 - Wakeup Flag For LLWU_P8

pub fn wuf9(&mut self) -> WUF9_W

Bit 1 - Wakeup Flag For LLWU_P9

pub fn wuf10(&mut self) -> WUF10_W

Bit 2 - Wakeup Flag For LLWU_P10

pub fn wuf11(&mut self) -> WUF11_W

Bit 3 - Wakeup Flag For LLWU_P11

pub fn wuf12(&mut self) -> WUF12_W

Bit 4 - Wakeup Flag For LLWU_P12

pub fn wuf13(&mut self) -> WUF13_W

Bit 5 - Wakeup Flag For LLWU_P13

pub fn wuf14(&mut self) -> WUF14_W

Bit 6 - Wakeup Flag For LLWU_P14

pub fn wuf15(&mut self) -> WUF15_W

Bit 7 - Wakeup Flag For LLWU_P15

impl W<u8, Reg<u8, _FILT1>>

pub fn filtsel(&mut self) -> FILTSEL_W

Bits 0:3 - Filter Pin Select

pub fn filte(&mut self) -> FILTE_W

Bits 5:6 - Digital Filter On External Pin

pub fn filtf(&mut self) -> FILTF_W

Bit 7 - Filter Detect Flag

impl W<u8, Reg<u8, _FILT2>>

pub fn filtsel(&mut self) -> FILTSEL_W

Bits 0:3 - Filter Pin Select

pub fn filte(&mut self) -> FILTE_W

Bits 5:6 - Digital Filter On External Pin

pub fn filtf(&mut self) -> FILTF_W

Bit 7 - Filter Detect Flag

impl W<u8, Reg<u8, _RST>>

pub fn rstfilt(&mut self) -> RSTFILT_W

Bit 0 - Digital Filter On RESET Pin

pub fn llrste(&mut self) -> LLRSTE_W

Bit 1 - Low-Leakage Mode RESET Enable

impl W<u8, Reg<u8, _LVDSC1>>

pub fn lvdv(&mut self) -> LVDV_W

Bits 0:1 - Low-Voltage Detect Voltage Select

pub fn lvdre(&mut self) -> LVDRE_W

Bit 4 - Low-Voltage Detect Reset Enable

pub fn lvdie(&mut self) -> LVDIE_W

Bit 5 - Low-Voltage Detect Interrupt Enable

pub fn lvdack(&mut self) -> LVDACK_W

Bit 6 - Low-Voltage Detect Acknowledge

impl W<u8, Reg<u8, _LVDSC2>>

pub fn lvwv(&mut self) -> LVWV_W

Bits 0:1 - Low-Voltage Warning Voltage Select

pub fn lvwie(&mut self) -> LVWIE_W

Bit 5 - Low-Voltage Warning Interrupt Enable

pub fn lvwack(&mut self) -> LVWACK_W

Bit 6 - Low-Voltage Warning Acknowledge

impl W<u8, Reg<u8, _REGSC>>

pub fn bgbe(&mut self) -> BGBE_W

Bit 0 - Bandgap Buffer Enable

pub fn ackiso(&mut self) -> ACKISO_W

Bit 3 - Acknowledge Isolation

pub fn bgen(&mut self) -> BGEN_W

Bit 4 - Bandgap Enable In VLPx Operation

impl W<u8, Reg<u8, _PMPROT>>

pub fn avlls(&mut self) -> AVLLS_W

Bit 1 - Allow Very-Low-Leakage Stop Mode

pub fn alls(&mut self) -> ALLS_W

Bit 3 - Allow Low-Leakage Stop Mode

pub fn avlp(&mut self) -> AVLP_W

Bit 5 - Allow Very-Low-Power Modes

impl W<u8, Reg<u8, _PMCTRL>>

pub fn stopm(&mut self) -> STOPM_W

Bits 0:2 - Stop Mode Control

pub fn runm(&mut self) -> RUNM_W

Bits 5:6 - Run Mode Control

pub fn lpwui(&mut self) -> LPWUI_W

Bit 7 - Low-Power Wake Up On Interrupt

impl W<u8, Reg<u8, _VLLSCTRL>>

pub fn vllsm(&mut self) -> VLLSM_W

Bits 0:2 - VLLS Mode Control

pub fn lpopo(&mut self) -> LPOPO_W

Bit 3 - LPO Power Option

pub fn ram2po(&mut self) -> RAM2PO_W

Bit 4 - RAM2 Power Option

pub fn porpo(&mut self) -> PORPO_W

Bit 5 - POR Power Option

impl W<u8, Reg<u8, _RPFC>>

pub fn rstfltsrw(&mut self) -> RSTFLTSRW_W

Bits 0:1 - Reset Pin Filter Select in Run and Wait Modes

pub fn rstfltss(&mut self) -> RSTFLTSS_W

Bit 2 - Reset Pin Filter Select in Stop Mode

impl W<u8, Reg<u8, _RPFW>>

pub fn rstfltsel(&mut self) -> RSTFLTSEL_W

Bits 0:4 - Reset Pin Filter Bus Clock Select

impl W<u8, Reg<u8, _DATL>>

pub fn data0(&mut self) -> DATA0_W

Bits 0:7 - When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer

impl W<u8, Reg<u8, _DATH>>

pub fn data1(&mut self) -> DATA1_W

Bits 0:3 - When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula

impl W<u8, Reg<u8, _SR>>

pub fn dacbfrpbf(&mut self) -> DACBFRPBF_W

Bit 0 - DAC Buffer Read Pointer Bottom Position Flag

pub fn dacbfrptf(&mut self) -> DACBFRPTF_W

Bit 1 - DAC Buffer Read Pointer Top Position Flag

pub fn dacbfwmf(&mut self) -> DACBFWMF_W

Bit 2 - DAC Buffer Watermark Flag

impl W<u8, Reg<u8, _C0>>

pub fn dacbbien(&mut self) -> DACBBIEN_W

Bit 0 - DAC Buffer Read Pointer Bottom Flag Interrupt Enable

pub fn dacbtien(&mut self) -> DACBTIEN_W

Bit 1 - DAC Buffer Read Pointer Top Flag Interrupt Enable

pub fn dacbwien(&mut self) -> DACBWIEN_W

Bit 2 - DAC Buffer Watermark Interrupt Enable

pub fn lpen(&mut self) -> LPEN_W

Bit 3 - DAC Low Power Control

pub fn dacswtrg(&mut self) -> DACSWTRG_W

Bit 4 - DAC Software Trigger

pub fn dactrgsel(&mut self) -> DACTRGSEL_W

Bit 5 - DAC Trigger Select

pub fn dacrfs(&mut self) -> DACRFS_W

Bit 6 - DAC Reference Select

pub fn dacen(&mut self) -> DACEN_W

Bit 7 - DAC Enable

impl W<u8, Reg<u8, _C1>>

pub fn dacbfen(&mut self) -> DACBFEN_W

Bit 0 - DAC Buffer Enable

pub fn dacbfmd(&mut self) -> DACBFMD_W

Bits 1:2 - DAC Buffer Work Mode Select

pub fn dacbfwm(&mut self) -> DACBFWM_W

Bits 3:4 - DAC Buffer Watermark Select

pub fn dmaen(&mut self) -> DMAEN_W

Bit 7 - DMA Enable Select

impl W<u8, Reg<u8, _C2>>

pub fn dacbfup(&mut self) -> DACBFUP_W

Bits 0:3 - DAC Buffer Upper Limit

pub fn dacbfrp(&mut self) -> DACBFRP_W

Bits 4:7 - DAC Buffer Read Pointer

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _PDOR>>

pub fn pdo(&mut self) -> PDO_W

Bits 0:31 - Port Data Output

impl W<u32, Reg<u32, _PSOR>>

pub fn ptso(&mut self) -> PTSO_W

Bits 0:31 - Port Set Output

impl W<u32, Reg<u32, _PCOR>>

pub fn ptco(&mut self) -> PTCO_W

Bits 0:31 - Port Clear Output

impl W<u32, Reg<u32, _PTOR>>

pub fn ptto(&mut self) -> PTTO_W

Bits 0:31 - Port Toggle Output

impl W<u32, Reg<u32, _PDDR>>

pub fn pdd(&mut self) -> PDD_W

Bits 0:31 - Port Data Direction

impl W<u32, Reg<u32, _ACTLR>>

pub fn dismcycint(&mut self) -> DISMCYCINT_W

Bit 0 - Disables interruption of multi-cycle instructions.

pub fn disdefwbuf(&mut self) -> DISDEFWBUF_W

Bit 1 - Disables write buffer use during default memory map accesses.

pub fn disfold(&mut self) -> DISFOLD_W

Bit 2 - Disables folding of IT instructions.

impl W<u32, Reg<u32, _ICSR>>

pub fn pendstclr(&mut self) -> PENDSTCLR_W

Bit 25 - no description available

pub fn pendstset(&mut self) -> PENDSTSET_W

Bit 26 - no description available

pub fn pendsvclr(&mut self) -> PENDSVCLR_W

Bit 27 - no description available

pub fn pendsvset(&mut self) -> PENDSVSET_W

Bit 28 - no description available

pub fn nmipendset(&mut self) -> NMIPENDSET_W

Bit 31 - no description available

impl W<u32, Reg<u32, _VTOR>>

pub fn tbloff(&mut self) -> TBLOFF_W

Bits 7:31 - Vector table base offset

impl W<u32, Reg<u32, _AIRCR>>

pub fn vectreset(&mut self) -> VECTRESET_W

Bit 0 - no description available

pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W

Bit 1 - no description available

pub fn sysresetreq(&mut self) -> SYSRESETREQ_W

Bit 2 - no description available

pub fn prigroup(&mut self) -> PRIGROUP_W

Bits 8:10 - Interrupt priority grouping field. This field determines the split of group priority from subpriority.

pub fn vectkey(&mut self) -> VECTKEY_W

Bits 16:31 - Register key

impl W<u32, Reg<u32, _SCR>>

pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W

Bit 1 - no description available

pub fn sleepdeep(&mut self) -> SLEEPDEEP_W

Bit 2 - no description available

pub fn sevonpend(&mut self) -> SEVONPEND_W

Bit 4 - no description available

impl W<u32, Reg<u32, _CCR>>

pub fn nonbasethrdena(&mut self) -> NONBASETHRDENA_W

Bit 0 - no description available

pub fn usersetmpend(&mut self) -> USERSETMPEND_W

Bit 1 - Enables unprivileged software access to the STIR

pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W

Bit 3 - Enables unaligned access traps

pub fn div_0_trp(&mut self) -> DIV_0_TRP_W

Bit 4 - Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0

pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W

Bit 8 - Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions.

pub fn stkalign(&mut self) -> STKALIGN_W

Bit 9 - Indicates stack alignment on exception entry

impl W<u32, Reg<u32, _SHPR1>>

pub fn pri_4(&mut self) -> PRI_4_W

Bits 0:7 - Priority of system handler 4, MemManage

pub fn pri_5(&mut self) -> PRI_5_W

Bits 8:15 - Priority of system handler 5, BusFault

pub fn pri_6(&mut self) -> PRI_6_W

Bits 16:23 - Priority of system handler 6, UsageFault

impl W<u32, Reg<u32, _SHPR2>>

pub fn pri_11(&mut self) -> PRI_11_W

Bits 24:31 - Priority of system handler 11, SVCall

impl W<u32, Reg<u32, _SHPR3>>

pub fn pri_14(&mut self) -> PRI_14_W

Bits 16:23 - Priority of system handler 14, PendSV

pub fn pri_15(&mut self) -> PRI_15_W

Bits 24:31 - Priority of system handler 15, SysTick exception

impl W<u32, Reg<u32, _SHCSR>>

pub fn memfaultact(&mut self) -> MEMFAULTACT_W

Bit 0 - no description available

pub fn busfaultact(&mut self) -> BUSFAULTACT_W

Bit 1 - no description available

pub fn usgfaultact(&mut self) -> USGFAULTACT_W

Bit 3 - no description available

pub fn svcallact(&mut self) -> SVCALLACT_W

Bit 7 - no description available

pub fn monitoract(&mut self) -> MONITORACT_W

Bit 8 - no description available

pub fn pendsvact(&mut self) -> PENDSVACT_W

Bit 10 - no description available

pub fn systickact(&mut self) -> SYSTICKACT_W

Bit 11 - no description available

pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W

Bit 12 - no description available

pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W

Bit 13 - no description available

pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W

Bit 14 - no description available

pub fn svcallpended(&mut self) -> SVCALLPENDED_W

Bit 15 - no description available

pub fn memfaultena(&mut self) -> MEMFAULTENA_W

Bit 16 - no description available

pub fn busfaultena(&mut self) -> BUSFAULTENA_W

Bit 17 - no description available

pub fn usgfaultena(&mut self) -> USGFAULTENA_W

Bit 18 - no description available

impl W<u32, Reg<u32, _CFSR>>

pub fn iaccviol(&mut self) -> IACCVIOL_W

Bit 0 - no description available

pub fn daccviol(&mut self) -> DACCVIOL_W

Bit 1 - no description available

pub fn munstkerr(&mut self) -> MUNSTKERR_W

Bit 3 - no description available

pub fn mstkerr(&mut self) -> MSTKERR_W

Bit 4 - no description available

pub fn mlsperr(&mut self) -> MLSPERR_W

Bit 5 - no description available

pub fn mmarvalid(&mut self) -> MMARVALID_W

Bit 7 - no description available

pub fn ibuserr(&mut self) -> IBUSERR_W

Bit 8 - no description available

pub fn preciserr(&mut self) -> PRECISERR_W

Bit 9 - no description available

pub fn impreciserr(&mut self) -> IMPRECISERR_W

Bit 10 - no description available

pub fn unstkerr(&mut self) -> UNSTKERR_W

Bit 11 - no description available

pub fn stkerr(&mut self) -> STKERR_W

Bit 12 - no description available

pub fn lsperr(&mut self) -> LSPERR_W

Bit 13 - no description available

pub fn bfarvalid(&mut self) -> BFARVALID_W

Bit 15 - no description available

pub fn undefinstr(&mut self) -> UNDEFINSTR_W

Bit 16 - no description available

pub fn invstate(&mut self) -> INVSTATE_W

Bit 17 - no description available

pub fn invpc(&mut self) -> INVPC_W

Bit 18 - no description available

pub fn nocp(&mut self) -> NOCP_W

Bit 19 - no description available

pub fn unaligned(&mut self) -> UNALIGNED_W

Bit 24 - no description available

pub fn divbyzero(&mut self) -> DIVBYZERO_W

Bit 25 - no description available

impl W<u32, Reg<u32, _HFSR>>

pub fn vecttbl(&mut self) -> VECTTBL_W

Bit 1 - no description available

pub fn forced(&mut self) -> FORCED_W

Bit 30 - no description available

pub fn debugevt(&mut self) -> DEBUGEVT_W

Bit 31 - no description available

impl W<u32, Reg<u32, _DFSR>>

pub fn halted(&mut self) -> HALTED_W

Bit 0 - no description available

pub fn bkpt(&mut self) -> BKPT_W

Bit 1 - no description available

pub fn dwttrap(&mut self) -> DWTTRAP_W

Bit 2 - no description available

pub fn vcatch(&mut self) -> VCATCH_W

Bit 3 - no description available

pub fn external(&mut self) -> EXTERNAL_W

Bit 4 - no description available

impl W<u32, Reg<u32, _MMFAR>>

pub fn address(&mut self) -> ADDRESS_W

Bits 0:31 - Address of MemManage fault location

impl W<u32, Reg<u32, _BFAR>>

pub fn address(&mut self) -> ADDRESS_W

Bits 0:31 - Address of the BusFault location

impl W<u32, Reg<u32, _AFSR>>

pub fn auxfault(&mut self) -> AUXFAULT_W

Bits 0:31 - Latched version of the AUXFAULT inputs

impl W<u32, Reg<u32, _CPACR>>

pub fn cp10(&mut self) -> CP10_W

Bits 20:21 - Access privileges for coprocessor 10.

pub fn cp11(&mut self) -> CP11_W

Bits 22:23 - Access privileges for coprocessor 11.

impl W<u32, Reg<u32, _FPCCR>>

pub fn lspact(&mut self) -> LSPACT_W

Bit 0 - Lazy state preservation.

pub fn user(&mut self) -> USER_W

Bit 1 - Privilege level when the floating-point stack frame was allocated.

pub fn thread(&mut self) -> THREAD_W

Bit 3 - Mode when the floating-point stack frame was allocated.

pub fn hfrdy(&mut self) -> HFRDY_W

Bit 4 - Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated.

pub fn mmrdy(&mut self) -> MMRDY_W

Bit 5 - Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated.

pub fn bfrdy(&mut self) -> BFRDY_W

Bit 6 - Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated.

pub fn monrdy(&mut self) -> MONRDY_W

Bit 8 - Permission to set the MON_PEND when the floating-point stack frame was allocated.

pub fn lspen(&mut self) -> LSPEN_W

Bit 30 - Lazy state preservation for floating-point context.

pub fn aspen(&mut self) -> ASPEN_W

Bit 31 - Enables CONTROL2 setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit.

impl W<u32, Reg<u32, _FPCAR>>

pub fn address(&mut self) -> ADDRESS_W

Bits 3:31 - The location of the unpopulated floating-point register space allocated on an exception stack frame.

impl W<u32, Reg<u32, _FPDSCR>>

pub fn rmode(&mut self) -> RMODE_W

Bits 22:23 - Default value for FPSCR.RMode (Rounding Mode control field).

pub fn fz(&mut self) -> FZ_W

Bit 24 - Default value for FPSCR.FZ (Flush-to-zero mode control bit).

pub fn dn(&mut self) -> DN_W

Bit 25 - Default value for FPSCR.DN (Default NaN mode control bit).

pub fn ahp(&mut self) -> AHP_W

Bit 26 - Default value for FPSCR.AHP (Alternative half-precision control bit).

impl W<u32, Reg<u32, _CSR>>

pub fn enable(&mut self) -> ENABLE_W

Bit 0 - no description available

pub fn tickint(&mut self) -> TICKINT_W

Bit 1 - no description available

pub fn clksource(&mut self) -> CLKSOURCE_W

Bit 2 - no description available

pub fn countflag(&mut self) -> COUNTFLAG_W

Bit 16 - no description available

impl W<u32, Reg<u32, _RVR>>

pub fn reload(&mut self) -> RELOAD_W

Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0

impl W<u32, Reg<u32, _CVR>>

pub fn current(&mut self) -> CURRENT_W

Bits 0:23 - Current value at the time the register is accessed

impl W<u32, Reg<u32, _CR>>

pub fn sramuap(&mut self) -> SRAMUAP_W

Bits 24:25 - SRAM_U arbitration priority

pub fn sramuwp(&mut self) -> SRAMUWP_W

Bit 26 - SRAM_U write protect

pub fn sramlap(&mut self) -> SRAMLAP_W

Bits 28:29 - SRAM_L arbitration priority

pub fn sramlwp(&mut self) -> SRAMLWP_W

Bit 30 - SRAM_L Write Protect

impl W<u32, Reg<u32, _ISCR>>

pub fn irq(&mut self) -> IRQ_W

Bit 1 - Normal Interrupt Pending

pub fn nmi(&mut self) -> NMI_W

Bit 2 - Non-maskable Interrupt Pending

pub fn fioce(&mut self) -> FIOCE_W

Bit 24 - FPU invalid operation interrupt enable

pub fn fdzce(&mut self) -> FDZCE_W

Bit 25 - FPU divide-by-zero interrupt enable

pub fn fofce(&mut self) -> FOFCE_W

Bit 26 - FPU overflow interrupt enable

pub fn fufce(&mut self) -> FUFCE_W

Bit 27 - FPU underflow interrupt enable

pub fn fixce(&mut self) -> FIXCE_W

Bit 28 - FPU inexact interrupt enable

pub fn fidce(&mut self) -> FIDCE_W

Bit 31 - FPU input denormal interrupt enable

impl W<u32, Reg<u32, _ETBCC>>

pub fn cnten(&mut self) -> CNTEN_W

Bit 0 - Counter Enable

pub fn rspt(&mut self) -> RSPT_W

Bits 1:2 - Response Type

pub fn rlrq(&mut self) -> RLRQ_W

Bit 3 - Reload Request

pub fn etdis(&mut self) -> ETDIS_W

Bit 4 - ETM-To-TPIU Disable

pub fn itdis(&mut self) -> ITDIS_W

Bit 5 - ITM-To-TPIU Disable

impl W<u32, Reg<u32, _ETBRL>>

pub fn reload(&mut self) -> RELOAD_W

Bits 0:10 - Byte Count Reload Value

impl W<u32, Reg<u32, _PID>>

pub fn pid(&mut self) -> PID_W

Bits 0:7 - M0_PID And M1_PID For MPU