[][src]Type Definition k22f::ftm1::synconf::W

type W = W<u32, SYNCONF>;

Writer for register SYNCONF

Methods

impl W[src]

pub fn hwtrigmode(&mut self) -> HWTRIGMODE_W[src]

Bit 0 - Hardware Trigger Mode

pub fn cntinc(&mut self) -> CNTINC_W[src]

Bit 2 - CNTIN Register Synchronization

pub fn invc(&mut self) -> INVC_W[src]

Bit 4 - INVCTRL Register Synchronization

pub fn swoc(&mut self) -> SWOC_W[src]

Bit 5 - SWOCTRL Register Synchronization

pub fn syncmode(&mut self) -> SYNCMODE_W[src]

Bit 7 - Synchronization Mode

pub fn swrstcnt(&mut self) -> SWRSTCNT_W[src]

Bit 8 - FTM counter synchronization is activated by the software trigger.

pub fn swwrbuf(&mut self) -> SWWRBUF_W[src]

Bit 9 - MOD, CNTIN, and CV registers synchronization is activated by the software trigger.

pub fn swom(&mut self) -> SWOM_W[src]

Bit 10 - Output mask synchronization is activated by the software trigger.

pub fn swinvc(&mut self) -> SWINVC_W[src]

Bit 11 - Inverting control synchronization is activated by the software trigger.

pub fn swsoc(&mut self) -> SWSOC_W[src]

Bit 12 - Software output control synchronization is activated by the software trigger.

pub fn hwrstcnt(&mut self) -> HWRSTCNT_W[src]

Bit 16 - FTM counter synchronization is activated by a hardware trigger.

pub fn hwwrbuf(&mut self) -> HWWRBUF_W[src]

Bit 17 - MOD, CNTIN, and CV registers synchronization is activated by a hardware trigger.

pub fn hwom(&mut self) -> HWOM_W[src]

Bit 18 - Output mask synchronization is activated by a hardware trigger.

pub fn hwinvc(&mut self) -> HWINVC_W[src]

Bit 19 - Inverting control synchronization is activated by a hardware trigger.

pub fn hwsoc(&mut self) -> HWSOC_W[src]

Bit 20 - Software output control synchronization is activated by a hardware trigger.